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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6; Ensure we rely on the reduction's implicit zero filling.7define <vscale x 16 x i8> @andv_zero_fill(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) #0 {8; CHECK-LABEL: andv_zero_fill:9; CHECK: // %bb.0:10; CHECK-NEXT: andv b0, p0, z0.b11; CHECK-NEXT: ret12 %t1 = call i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a)13 %t2 = insertelement <vscale x 16 x i8> zeroinitializer, i8 %t1, i64 014 ret <vscale x 16 x i8> %t215}16 17; Ensure we rely on the reduction's implicit zero filling.18define <vscale x 8 x i16> @eorv_zero_fill(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) #0 {19; CHECK-LABEL: eorv_zero_fill:20; CHECK: // %bb.0:21; CHECK-NEXT: eorv h0, p0, z0.h22; CHECK-NEXT: ret23 %t1 = call i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a)24 %t2 = insertelement <vscale x 8 x i16> zeroinitializer, i16 %t1, i64 025 ret <vscale x 8 x i16> %t226}27 28; Ensure we rely on the reduction's implicit zero filling.29define <vscale x 2 x double> @fadda_zero_fill(<vscale x 2 x i1> %pg, double %init, <vscale x 2 x double> %a) #0 {30; CHECK-LABEL: fadda_zero_fill:31; CHECK: // %bb.0:32; CHECK-NEXT: // kill: def $d0 killed $d0 def $z033; CHECK-NEXT: fadda d0, p0, d0, z1.d34; CHECK-NEXT: ret35 %t1 = call double @llvm.aarch64.sve.fadda.nxv2f64(<vscale x 2 x i1> %pg, double %init, <vscale x 2 x double> %a)36 %t2 = insertelement <vscale x 2 x double> zeroinitializer, double %t1, i64 037 ret <vscale x 2 x double> %t238}39 40; Ensure we rely on the reduction's implicit zero filling.41define <vscale x 4 x float> @faddv_zero_fill(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) #0 {42; CHECK-LABEL: faddv_zero_fill:43; CHECK: // %bb.0:44; CHECK-NEXT: faddv s0, p0, z0.s45; CHECK-NEXT: ret46 %t1 = call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a)47 %t2 = insertelement <vscale x 4 x float> zeroinitializer, float %t1, i64 048 ret <vscale x 4 x float> %t249}50 51; Ensure we rely on the reduction's implicit zero filling.52define <vscale x 8 x half> @fmaxv_zero_fill(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) #0 {53; CHECK-LABEL: fmaxv_zero_fill:54; CHECK: // %bb.0:55; CHECK-NEXT: fmaxv h0, p0, z0.h56; CHECK-NEXT: ret57 %t1 = call half @llvm.aarch64.sve.fmaxv.nxv8f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a)58 %t2 = insertelement <vscale x 8 x half> zeroinitializer, half %t1, i64 059 ret <vscale x 8 x half> %t260}61 62; Ensure we rely on the reduction's implicit zero filling.63define <vscale x 2 x float> @fmaxnmv_zero_fill(<vscale x 2 x i1> %pg, <vscale x 2 x float> %a) #0 {64; CHECK-LABEL: fmaxnmv_zero_fill:65; CHECK: // %bb.0:66; CHECK-NEXT: fmaxnmv s0, p0, z0.s67; CHECK-NEXT: ret68 %t1 = call float @llvm.aarch64.sve.fmaxnmv.nxv2f32(<vscale x 2 x i1> %pg, <vscale x 2 x float> %a)69 %t2 = insertelement <vscale x 2 x float> zeroinitializer, float %t1, i64 070 ret <vscale x 2 x float> %t271}72 73; Ensure we rely on the reduction's implicit zero filling.74define <vscale x 2 x float> @fminnmv_zero_fill(<vscale x 2 x i1> %pg, <vscale x 2 x float> %a) #0 {75; CHECK-LABEL: fminnmv_zero_fill:76; CHECK: // %bb.0:77; CHECK-NEXT: fminnmv s0, p0, z0.s78; CHECK-NEXT: ret79 %t1 = call float @llvm.aarch64.sve.fminnmv.nxv2f32(<vscale x 2 x i1> %pg, <vscale x 2 x float> %a)80 %t2 = insertelement <vscale x 2 x float> zeroinitializer, float %t1, i64 081 ret <vscale x 2 x float> %t282}83 84; Ensure we rely on the reduction's implicit zero filling.85define <vscale x 2 x float> @fminv_zero_fill(<vscale x 2 x i1> %pg, <vscale x 2 x float> %a) #0 {86; CHECK-LABEL: fminv_zero_fill:87; CHECK: // %bb.0:88; CHECK-NEXT: fminv s0, p0, z0.s89; CHECK-NEXT: ret90 %t1 = call float @llvm.aarch64.sve.fminv.nxv2f32(<vscale x 2 x i1> %pg, <vscale x 2 x float> %a)91 %t2 = insertelement <vscale x 2 x float> zeroinitializer, float %t1, i64 092 ret <vscale x 2 x float> %t293}94 95; Ensure we rely on the reduction's implicit zero filling.96define <vscale x 4 x i32> @orv_zero_fill(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) #0 {97; CHECK-LABEL: orv_zero_fill:98; CHECK: // %bb.0:99; CHECK-NEXT: orv s0, p0, z0.s100; CHECK-NEXT: ret101 %t1 = call i32 @llvm.aarch64.sve.orv.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a)102 %t2 = insertelement <vscale x 4 x i32> zeroinitializer, i32 %t1, i64 0103 ret <vscale x 4 x i32> %t2104}105 106; Ensure we rely on the reduction's implicit zero filling.107define <vscale x 2 x i64> @saddv_zero_fill(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) #0 {108; CHECK-LABEL: saddv_zero_fill:109; CHECK: // %bb.0:110; CHECK-NEXT: saddv d0, p0, z0.b111; CHECK-NEXT: ret112 %t1 = call i64 @llvm.aarch64.sve.saddv.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a)113 %t2 = insertelement <vscale x 2 x i64> zeroinitializer, i64 %t1, i64 0114 ret <vscale x 2 x i64> %t2115}116 117; Ensure we rely on the reduction's implicit zero filling.118define <vscale x 2 x i64> @smaxv_zero_fill(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) #0 {119; CHECK-LABEL: smaxv_zero_fill:120; CHECK: // %bb.0:121; CHECK-NEXT: smaxv d0, p0, z0.d122; CHECK-NEXT: ret123 %t1 = call i64 @llvm.aarch64.sve.smaxv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)124 %t2 = insertelement <vscale x 2 x i64> zeroinitializer, i64 %t1, i64 0125 ret <vscale x 2 x i64> %t2126}127 128; Ensure we rely on the reduction's implicit zero filling.129define <vscale x 4 x i32> @sminv_zero_fill(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) #0 {130; CHECK-LABEL: sminv_zero_fill:131; CHECK: // %bb.0:132; CHECK-NEXT: sminv s0, p0, z0.s133; CHECK-NEXT: ret134 %t1 = call i32 @llvm.aarch64.sve.sminv.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a)135 %t2 = insertelement <vscale x 4 x i32> zeroinitializer, i32 %t1, i64 0136 ret <vscale x 4 x i32> %t2137}138 139; Ensure we rely on the reduction's implicit zero filling.140define <vscale x 2 x i64> @uaddv_zero_fill(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) #0 {141; CHECK-LABEL: uaddv_zero_fill:142; CHECK: // %bb.0:143; CHECK-NEXT: uaddv d0, p0, z0.h144; CHECK-NEXT: ret145 %t1 = call i64 @llvm.aarch64.sve.uaddv.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a)146 %t2 = insertelement <vscale x 2 x i64> zeroinitializer, i64 %t1, i64 0147 ret <vscale x 2 x i64> %t2148}149 150; Ensure we rely on the reduction's implicit zero filling.151define <vscale x 16 x i8> @umaxv_zero_fill(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) #0 {152; CHECK-LABEL: umaxv_zero_fill:153; CHECK: // %bb.0:154; CHECK-NEXT: umaxv b0, p0, z0.b155; CHECK-NEXT: ret156 %t1 = call i8 @llvm.aarch64.sve.umaxv.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a)157 %t2 = insertelement <vscale x 16 x i8> zeroinitializer, i8 %t1, i64 0158 ret <vscale x 16 x i8> %t2159}160 161; Ensure we rely on the reduction's implicit zero filling.162define <vscale x 2 x i64> @uminv_zero_fill(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) #0 {163; CHECK-LABEL: uminv_zero_fill:164; CHECK: // %bb.0:165; CHECK-NEXT: uminv d0, p0, z0.d166; CHECK-NEXT: ret167 %t1 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)168 %t2 = insertelement <vscale x 2 x i64> zeroinitializer, i64 %t1, i64 0169 ret <vscale x 2 x i64> %t2170}171 172; Ensure explicit zeroing when inserting into a lane other than 0.173; NOTE: This test doesn't care about the exact way an insert is code generated,174; so only checks the presence of one instruction from the expected chain.175define <vscale x 2 x i64> @zero_fill_non_zero_index(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) #0 {176; CHECK-LABEL: zero_fill_non_zero_index:177; CHECK: // %bb.0:178; CHECK-NEXT: mov w8, #1 // =0x1179; CHECK-NEXT: index z1.d, #0, #1180; CHECK-NEXT: uminv d3, p0, z0.d181; CHECK-NEXT: mov z2.d, x8182; CHECK-NEXT: ptrue p1.d183; CHECK-NEXT: movi v0.2d, #0000000000000000184; CHECK-NEXT: cmpeq p0.d, p1/z, z1.d, z2.d185; CHECK-NEXT: fmov x8, d3186; CHECK-NEXT: mov z0.d, p0/m, x8187; CHECK-NEXT: ret188 %t1 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)189 %t2 = insertelement <vscale x 2 x i64> zeroinitializer, i64 %t1, i64 1190 ret <vscale x 2 x i64> %t2191}192 193; Ensure explicit zeroing when the result vector is larger than that produced by194; the reduction instruction.195define <vscale x 4 x i64> @zero_fill_type_mismatch(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) #0 {196; CHECK-LABEL: zero_fill_type_mismatch:197; CHECK: // %bb.0:198; CHECK-NEXT: uminv d0, p0, z0.d199; CHECK-NEXT: movi v1.2d, #0000000000000000200; CHECK-NEXT: ret201 %t1 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)202 %t2 = insertelement <vscale x 4 x i64> zeroinitializer, i64 %t1, i64 0203 ret <vscale x 4 x i64> %t2204}205 206; Ensure explicit zeroing when extracting an element from an operation that207; cannot guarantee lanes 1-N are zero.208; NOTE: This test doesn't care about the exact way an insert is code generated,209; so only checks the presence of one instruction from the expected chain.210define <vscale x 2 x i64> @zero_fill_no_zero_upper_lanes(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) #0 {211; CHECK-LABEL: zero_fill_no_zero_upper_lanes:212; CHECK: // %bb.0:213; CHECK-NEXT: umin z0.d, p0/m, z0.d, z0.d214; CHECK-NEXT: movi v1.2d, #0000000000000000215; CHECK-NEXT: ptrue p0.d, vl1216; CHECK-NEXT: fmov x8, d0217; CHECK-NEXT: mov z1.d, p0/m, x8218; CHECK-NEXT: mov z0.d, z1.d219; CHECK-NEXT: ret220 %t1 = call <vscale x 2 x i64> @llvm.aarch64.sve.umin.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %a)221 %t2 = extractelement <vscale x 2 x i64> %t1, i64 0222 %t3 = insertelement <vscale x 2 x i64> zeroinitializer, i64 %t2, i64 0223 ret <vscale x 2 x i64> %t3224}225 226declare i8 @llvm.aarch64.sve.andv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)227declare i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)228 229declare i8 @llvm.aarch64.sve.eorv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)230declare i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)231 232declare float @llvm.aarch64.sve.fadda.nxv2f32(<vscale x 2 x i1>, float, <vscale x 2 x float>)233declare double @llvm.aarch64.sve.fadda.nxv2f64(<vscale x 2 x i1>, double, <vscale x 2 x double>)234 235declare float @llvm.aarch64.sve.faddv.nxv2f32(<vscale x 2 x i1>, <vscale x 2 x float>)236declare float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>)237 238declare float @llvm.aarch64.sve.fmaxnmv.nxv2f32(<vscale x 2 x i1>, <vscale x 2 x float>)239 240declare half @llvm.aarch64.sve.fmaxv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>)241declare float @llvm.aarch64.sve.fmaxv.nxv2f32(<vscale x 2 x i1>, <vscale x 2 x float>)242 243declare float @llvm.aarch64.sve.fminv.nxv2f32(<vscale x 2 x i1>, <vscale x 2 x float>)244 245declare float @llvm.aarch64.sve.fminnmv.nxv2f32(<vscale x 2 x i1>, <vscale x 2 x float>)246 247declare i8 @llvm.aarch64.sve.orv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)248declare i32 @llvm.aarch64.sve.orv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>)249 250declare i64 @llvm.aarch64.sve.saddv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)251declare i64 @llvm.aarch64.sve.saddv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)252 253declare i8 @llvm.aarch64.sve.smaxv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)254declare i64 @llvm.aarch64.sve.smaxv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>)255 256declare i8 @llvm.aarch64.sve.sminv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)257declare i32 @llvm.aarch64.sve.sminv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>)258 259declare i64 @llvm.aarch64.sve.uaddv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)260declare i64 @llvm.aarch64.sve.uaddv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)261 262declare i8 @llvm.aarch64.sve.umaxv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)263declare i8 @llvm.aarch64.sve.umaxv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)264 265declare i8 @llvm.aarch64.sve.uminv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)266declare i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>)267 268declare <vscale x 2 x i64> @llvm.aarch64.sve.umin.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)269 270attributes #0 = { "target-features"="+sve" }271