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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s3 4define void @fmul_indexed_f16_256b(ptr %a, ptr %b, ptr %c) #0 {5; CHECK-LABEL: fmul_indexed_f16_256b:6; CHECK: // %bb.0:7; CHECK-NEXT: ldr z0, [x0]8; CHECK-NEXT: ldr z1, [x1]9; CHECK-NEXT: fmul z0.h, z1.h, z0.h[2]10; CHECK-NEXT: str z0, [x2]11; CHECK-NEXT: ret12 %ld.a = load <16 x half>, ptr %a13 %ld.b = load <16 x half>, ptr %b14 %splat.lanes = shufflevector <16 x half> %ld.a, <16 x half> poison, <16 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2,15 i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10>16 %res = fmul <16 x half> %ld.b, %splat.lanes17 store <16 x half> %res, ptr %c18 ret void19}20 21define void @fmul_indexed_bf16_256b(ptr %a, ptr %b, ptr %c) #0 {22; CHECK-LABEL: fmul_indexed_bf16_256b:23; CHECK: // %bb.0:24; CHECK-NEXT: ldp q0, q1, [x0]25; CHECK-NEXT: ptrue p0.h, vl826; CHECK-NEXT: ldp q2, q3, [x1]27; CHECK-NEXT: dup v0.8h, v0.h[2]28; CHECK-NEXT: dup v1.8h, v1.h[2]29; CHECK-NEXT: bfmul z0.h, p0/m, z0.h, z2.h30; CHECK-NEXT: bfmul z1.h, p0/m, z1.h, z3.h31; CHECK-NEXT: stp q0, q1, [x2]32; CHECK-NEXT: ret33 %ld.a = load <16 x bfloat>, ptr %a34 %ld.b = load <16 x bfloat>, ptr %b35 %splat.lanes = shufflevector <16 x bfloat> %ld.a, <16 x bfloat> poison, <16 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2,36 i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10>37 %res = fmul <16 x bfloat> %ld.b, %splat.lanes38 store <16 x bfloat> %res, ptr %c39 ret void40}41 42define void @fmul_indexed_f32_256b(ptr %a, ptr %b, ptr %c) #0 {43; CHECK-LABEL: fmul_indexed_f32_256b:44; CHECK: // %bb.0:45; CHECK-NEXT: ldr z0, [x0]46; CHECK-NEXT: ldr z1, [x1]47; CHECK-NEXT: fmul z0.s, z1.s, z0.s[3]48; CHECK-NEXT: str z0, [x2]49; CHECK-NEXT: ret50 %ld.a = load <8 x float>, ptr %a51 %ld.b = load <8 x float>, ptr %b52 %splat.lanes = shufflevector <8 x float> %ld.a, <8 x float> poison, <8 x i32> <i32 3, i32 3, i32 3, i32 3,53 i32 7, i32 7, i32 7, i32 7>54 %res = fmul <8 x float> %splat.lanes, %ld.b55 store <8 x float> %res, ptr %c56 ret void57}58 59define void @fmul_indexed_f64_256b_trn1(ptr %a, ptr %b, ptr %c) #0 {60; CHECK-LABEL: fmul_indexed_f64_256b_trn1:61; CHECK: // %bb.0:62; CHECK-NEXT: ldr z0, [x0]63; CHECK-NEXT: ldr z1, [x1]64; CHECK-NEXT: fmul z0.d, z1.d, z0.d[0]65; CHECK-NEXT: str z0, [x2]66; CHECK-NEXT: ret67 %ld.a = load <4 x double>, ptr %a68 %ld.b = load <4 x double>, ptr %b69 %splat.lanes = shufflevector <4 x double> %ld.a, <4 x double> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 2>70 %res = fmul <4 x double> %splat.lanes, %ld.b71 store <4 x double> %res, ptr %c72 ret void73}74 75define void @fmul_indexed_f64_256b_trn2(ptr %a, ptr %b, ptr %c) #0 {76; CHECK-LABEL: fmul_indexed_f64_256b_trn2:77; CHECK: // %bb.0:78; CHECK-NEXT: ldr z0, [x0]79; CHECK-NEXT: ldr z1, [x1]80; CHECK-NEXT: fmul z0.d, z1.d, z0.d[1]81; CHECK-NEXT: str z0, [x2]82; CHECK-NEXT: ret83 %ld.a = load <4 x double>, ptr %a84 %ld.b = load <4 x double>, ptr %b85 %splat.lanes = shufflevector <4 x double> %ld.a, <4 x double> poison, <4 x i32> <i32 1, i32 1, i32 3, i32 3>86 %res = fmul <4 x double> %ld.b, %splat.lanes87 store <4 x double> %res, ptr %c88 ret void89}90 91define void @fmla_indexed_f16_256b(ptr %a, ptr %b, ptr %c) #0 {92; CHECK-LABEL: fmla_indexed_f16_256b:93; CHECK: // %bb.0:94; CHECK-NEXT: ldr z0, [x0]95; CHECK-NEXT: ldr z1, [x1]96; CHECK-NEXT: ldr z2, [x2]97; CHECK-NEXT: fmla z2.h, z1.h, z0.h[2]98; CHECK-NEXT: str z2, [x2]99; CHECK-NEXT: ret100 %ld.a = load <16 x half>, ptr %a101 %ld.b = load <16 x half>, ptr %b102 %ld.c = load <16 x half>, ptr %c103 %splat.lanes = shufflevector <16 x half> %ld.a, <16 x half> poison, <16 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2,104 i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10>105 %res = call <16 x half> @llvm.fmuladd.v16f16(<16 x half> %ld.b, <16 x half> %splat.lanes, <16 x half> %ld.c)106 store <16 x half> %res, ptr %c107 ret void108}109 110define void @fmla_indexed_bf16_256b(ptr %a, ptr %b, ptr %c) #0 {111; CHECK-LABEL: fmla_indexed_bf16_256b:112; CHECK: // %bb.0:113; CHECK-NEXT: ldp q0, q1, [x0]114; CHECK-NEXT: ptrue p0.h, vl8115; CHECK-NEXT: ldp q2, q3, [x1]116; CHECK-NEXT: ldp q4, q5, [x2]117; CHECK-NEXT: dup v0.8h, v0.h[2]118; CHECK-NEXT: dup v1.8h, v1.h[2]119; CHECK-NEXT: bfmul z0.h, p0/m, z0.h, z2.h120; CHECK-NEXT: bfmul z1.h, p0/m, z1.h, z3.h121; CHECK-NEXT: bfadd z0.h, p0/m, z0.h, z4.h122; CHECK-NEXT: bfadd z1.h, p0/m, z1.h, z5.h123; CHECK-NEXT: stp q0, q1, [x2]124; CHECK-NEXT: ret125 %ld.a = load <16 x bfloat>, ptr %a126 %ld.b = load <16 x bfloat>, ptr %b127 %ld.c = load <16 x bfloat>, ptr %c128 %splat.lanes = shufflevector <16 x bfloat> %ld.a, <16 x bfloat> poison, <16 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2,129 i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10>130 %res = call <16 x bfloat> @llvm.fmuladd.v16bf16(<16 x bfloat> %ld.b, <16 x bfloat> %splat.lanes, <16 x bfloat> %ld.c)131 store <16 x bfloat> %res, ptr %c132 ret void133}134 135define void @fmla_indexed_f32_256b(ptr %a, ptr %b, ptr %c) #0 {136; CHECK-LABEL: fmla_indexed_f32_256b:137; CHECK: // %bb.0:138; CHECK-NEXT: ldr z0, [x0]139; CHECK-NEXT: ldr z1, [x1]140; CHECK-NEXT: ldr z2, [x2]141; CHECK-NEXT: fmla z2.s, z1.s, z0.s[3]142; CHECK-NEXT: str z2, [x2]143; CHECK-NEXT: ret144 %ld.a = load <8 x float>, ptr %a145 %ld.b = load <8 x float>, ptr %b146 %ld.c = load <8 x float>, ptr %c147 %splat.lanes = shufflevector <8 x float> %ld.a, <8 x float> poison, <8 x i32> <i32 3, i32 3, i32 3, i32 3,148 i32 7, i32 7, i32 7, i32 7>149 %res = call <8 x float> @llvm.fmuladd.v8f32(<8 x float> %splat.lanes, <8 x float> %ld.b, <8 x float> %ld.c)150 store <8 x float> %res, ptr %c151 ret void152}153 154define void @fmla_indexed_f64_256b_trn1(ptr %a, ptr %b, ptr %c) #0 {155; CHECK-LABEL: fmla_indexed_f64_256b_trn1:156; CHECK: // %bb.0:157; CHECK-NEXT: ldr z0, [x0]158; CHECK-NEXT: ldr z1, [x1]159; CHECK-NEXT: ldr z2, [x2]160; CHECK-NEXT: fmla z2.d, z1.d, z0.d[0]161; CHECK-NEXT: str z2, [x2]162; CHECK-NEXT: ret163 %ld.a = load <4 x double>, ptr %a164 %ld.b = load <4 x double>, ptr %b165 %ld.c = load <4 x double>, ptr %c166 %splat.lanes = shufflevector <4 x double> %ld.a, <4 x double> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 2>167 %res = call <4 x double> @llvm.fmuladd.v4f64(<4 x double> %splat.lanes, <4 x double> %ld.b, <4 x double> %ld.c)168 store <4 x double> %res, ptr %c169 ret void170}171 172define void @fmla_indexed_f64_256b_trn2(ptr %a, ptr %b, ptr %c) #0 {173; CHECK-LABEL: fmla_indexed_f64_256b_trn2:174; CHECK: // %bb.0:175; CHECK-NEXT: ldr z0, [x0]176; CHECK-NEXT: ldr z1, [x1]177; CHECK-NEXT: ldr z2, [x2]178; CHECK-NEXT: fmla z2.d, z1.d, z0.d[1]179; CHECK-NEXT: str z2, [x2]180; CHECK-NEXT: ret181 %ld.a = load <4 x double>, ptr %a182 %ld.b = load <4 x double>, ptr %b183 %ld.c = load <4 x double>, ptr %c184 %splat.lanes = shufflevector <4 x double> %ld.a, <4 x double> poison, <4 x i32> <i32 1, i32 1, i32 3, i32 3>185 %res = call <4 x double> @llvm.fmuladd.v4f64(<4 x double> %ld.b, <4 x double> %splat.lanes, <4 x double> %ld.c)186 store <4 x double> %res, ptr %c187 ret void188}189 190define void @fmls_indexed_f16_256b(ptr %a, ptr %b, ptr %c) #0 {191; CHECK-LABEL: fmls_indexed_f16_256b:192; CHECK: // %bb.0:193; CHECK-NEXT: ldr z0, [x0]194; CHECK-NEXT: ldr z1, [x1]195; CHECK-NEXT: ldr z2, [x2]196; CHECK-NEXT: fmls z2.h, z1.h, z0.h[2]197; CHECK-NEXT: str z2, [x2]198; CHECK-NEXT: ret199 %ld.a = load <16 x half>, ptr %a200 %ld.b = load <16 x half>, ptr %b201 %ld.c = load <16 x half>, ptr %c202 %splat.lanes = shufflevector <16 x half> %ld.a, <16 x half> poison, <16 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2,203 i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10>204 %neg.b = fneg <16 x half> %ld.b205 %res = call <16 x half> @llvm.fmuladd.v16f16(<16 x half> %neg.b, <16 x half> %splat.lanes, <16 x half> %ld.c)206 store <16 x half> %res, ptr %c207 ret void208}209 210define void @fmls_indexed_bf16_256b(ptr %a, ptr %b, ptr %c) #0 {211; CHECK-LABEL: fmls_indexed_bf16_256b:212; CHECK: // %bb.0:213; CHECK-NEXT: ldp q0, q1, [x0]214; CHECK-NEXT: ptrue p0.h, vl8215; CHECK-NEXT: ldp q2, q3, [x1]216; CHECK-NEXT: ldp q4, q5, [x2]217; CHECK-NEXT: dup v0.8h, v0.h[2]218; CHECK-NEXT: dup v1.8h, v1.h[2]219; CHECK-NEXT: bfmul z0.h, p0/m, z0.h, z2.h220; CHECK-NEXT: bfmul z1.h, p0/m, z1.h, z3.h221; CHECK-NEXT: bfsub z0.h, p0/m, z0.h, z4.h222; CHECK-NEXT: bfsub z1.h, p0/m, z1.h, z5.h223; CHECK-NEXT: stp q0, q1, [x2]224; CHECK-NEXT: ret225 %ld.a = load <16 x bfloat>, ptr %a226 %ld.b = load <16 x bfloat>, ptr %b227 %ld.c = load <16 x bfloat>, ptr %c228 %splat.lanes = shufflevector <16 x bfloat> %ld.a, <16 x bfloat> poison, <16 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2,229 i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10>230 %neg.b = fneg <16 x bfloat> %ld.b231 %res = call <16 x bfloat> @llvm.fmuladd.v16bf16(<16 x bfloat> %neg.b, <16 x bfloat> %splat.lanes, <16 x bfloat> %ld.c)232 store <16 x bfloat> %res, ptr %c233 ret void234}235 236define void @fmls_indexed_f32_256b(ptr %a, ptr %b, ptr %c) #0 {237; CHECK-LABEL: fmls_indexed_f32_256b:238; CHECK: // %bb.0:239; CHECK-NEXT: ldr z0, [x0]240; CHECK-NEXT: ldr z1, [x1]241; CHECK-NEXT: ldr z2, [x2]242; CHECK-NEXT: fmls z2.s, z1.s, z0.s[3]243; CHECK-NEXT: str z2, [x2]244; CHECK-NEXT: ret245 %ld.a = load <8 x float>, ptr %a246 %ld.b = load <8 x float>, ptr %b247 %ld.c = load <8 x float>, ptr %c248 %splat.lanes = shufflevector <8 x float> %ld.a, <8 x float> poison, <8 x i32> <i32 3, i32 3, i32 3, i32 3,249 i32 7, i32 7, i32 7, i32 7>250 %neg.b = fneg <8 x float> %ld.b251 %res = call <8 x float> @llvm.fmuladd.v8f32(<8 x float> %splat.lanes, <8 x float> %neg.b, <8 x float> %ld.c)252 store <8 x float> %res, ptr %c253 ret void254}255 256define void @fmls_indexed_f64_256b_trn1(ptr %a, ptr %b, ptr %c) #0 {257; CHECK-LABEL: fmls_indexed_f64_256b_trn1:258; CHECK: // %bb.0:259; CHECK-NEXT: ldr z0, [x0]260; CHECK-NEXT: ldr z1, [x1]261; CHECK-NEXT: ldr z2, [x2]262; CHECK-NEXT: fmls z2.d, z1.d, z0.d[0]263; CHECK-NEXT: str z2, [x2]264; CHECK-NEXT: ret265 %ld.a = load <4 x double>, ptr %a266 %ld.b = load <4 x double>, ptr %b267 %ld.c = load <4 x double>, ptr %c268 %splat.lanes = shufflevector <4 x double> %ld.a, <4 x double> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 2>269 %neg.b = fneg <4 x double> %ld.b270 %res = call <4 x double> @llvm.fmuladd.v4f64(<4 x double> %splat.lanes, <4 x double> %neg.b, <4 x double> %ld.c)271 store <4 x double> %res, ptr %c272 ret void273}274 275define void @fmls_indexed_f64_256b_trn2(ptr %a, ptr %b, ptr %c) #0 {276; CHECK-LABEL: fmls_indexed_f64_256b_trn2:277; CHECK: // %bb.0:278; CHECK-NEXT: ldr z0, [x0]279; CHECK-NEXT: ldr z1, [x1]280; CHECK-NEXT: ldr z2, [x2]281; CHECK-NEXT: fmls z2.d, z1.d, z0.d[1]282; CHECK-NEXT: str z2, [x2]283; CHECK-NEXT: ret284 %ld.a = load <4 x double>, ptr %a285 %ld.b = load <4 x double>, ptr %b286 %ld.c = load <4 x double>, ptr %c287 %splat.lanes = shufflevector <4 x double> %ld.a, <4 x double> poison, <4 x i32> <i32 1, i32 1, i32 3, i32 3>288 %neg.b = fneg <4 x double> %ld.b289 %res = call <4 x double> @llvm.fmuladd.v4f64(<4 x double> %neg.b, <4 x double> %splat.lanes, <4 x double> %ld.c)290 store <4 x double> %res, ptr %c291 ret void292}293 294declare <16 x half> @llvm.fmuladd.v16f16(<16 x half>, <16 x half>, <16 x half>);295declare <16 x bfloat> @llvm.fmuladd.v16bf16(<16 x bfloat>, <16 x bfloat>, <16 x bfloat>);296declare <8 x float> @llvm.fmuladd.v8f32(<8 x float>, <8 x float>, <8 x float>);297declare <4 x double> @llvm.fmuladd.v4f64(<4 x double>, <4 x double>, <4 x double>);298 299attributes #0 = { noinline vscale_range(2,2) "target-features"="+sve2p1,+bf16,+sve-b16b16" }300