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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -mattr=+bf16 < %s | FileCheck %s --check-prefixes=CHECK3 4define <vscale x 2 x i64> @insert_v2i64_nxv2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind {5; CHECK-LABEL: insert_v2i64_nxv2i64:6; CHECK: // %bb.0:7; CHECK-NEXT: ptrue p0.d, vl28; CHECK-NEXT: // kill: def $q1 killed $q1 def $z19; CHECK-NEXT: mov z0.d, p0/m, z1.d10; CHECK-NEXT: ret11 %retval = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 0)12 ret <vscale x 2 x i64> %retval13}14 15define <vscale x 2 x i64> @insert_v2i64_nxv2i64_idx2(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind {16; CHECK-LABEL: insert_v2i64_nxv2i64_idx2:17; CHECK: // %bb.0:18; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill19; CHECK-NEXT: addvl sp, sp, #-120; CHECK-NEXT: cntd x821; CHECK-NEXT: mov w9, #2 // =0x222; CHECK-NEXT: str z0, [sp]23; CHECK-NEXT: sub x8, x8, #224; CHECK-NEXT: cmp x8, #225; CHECK-NEXT: csel x8, x8, x9, lo26; CHECK-NEXT: mov x9, sp27; CHECK-NEXT: lsl x8, x8, #328; CHECK-NEXT: str q1, [x9, x8]29; CHECK-NEXT: ldr z0, [sp]30; CHECK-NEXT: addvl sp, sp, #131; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload32; CHECK-NEXT: ret33 %retval = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 2)34 ret <vscale x 2 x i64> %retval35}36 37define <vscale x 4 x i32> @insert_v4i32_nxv4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind {38; CHECK-LABEL: insert_v4i32_nxv4i32:39; CHECK: // %bb.0:40; CHECK-NEXT: ptrue p0.s, vl441; CHECK-NEXT: // kill: def $q1 killed $q1 def $z142; CHECK-NEXT: mov z0.s, p0/m, z1.s43; CHECK-NEXT: ret44 %retval = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 0)45 ret <vscale x 4 x i32> %retval46}47 48define <vscale x 4 x i32> @insert_v4i32_nxv4i32_idx4(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind {49; CHECK-LABEL: insert_v4i32_nxv4i32_idx4:50; CHECK: // %bb.0:51; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill52; CHECK-NEXT: addvl sp, sp, #-153; CHECK-NEXT: cntw x854; CHECK-NEXT: mov w9, #4 // =0x455; CHECK-NEXT: str z0, [sp]56; CHECK-NEXT: sub x8, x8, #457; CHECK-NEXT: cmp x8, #458; CHECK-NEXT: csel x8, x8, x9, lo59; CHECK-NEXT: mov x9, sp60; CHECK-NEXT: lsl x8, x8, #261; CHECK-NEXT: str q1, [x9, x8]62; CHECK-NEXT: ldr z0, [sp]63; CHECK-NEXT: addvl sp, sp, #164; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload65; CHECK-NEXT: ret66 %retval = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 4)67 ret <vscale x 4 x i32> %retval68}69 70define <vscale x 8 x i16> @insert_v8i16_nxv8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind {71; CHECK-LABEL: insert_v8i16_nxv8i16:72; CHECK: // %bb.0:73; CHECK-NEXT: ptrue p0.h, vl874; CHECK-NEXT: // kill: def $q1 killed $q1 def $z175; CHECK-NEXT: mov z0.h, p0/m, z1.h76; CHECK-NEXT: ret77 %retval = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec, i64 0)78 ret <vscale x 8 x i16> %retval79}80 81define <vscale x 8 x i16> @insert_v8i16_nxv8i16_idx8(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind {82; CHECK-LABEL: insert_v8i16_nxv8i16_idx8:83; CHECK: // %bb.0:84; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill85; CHECK-NEXT: addvl sp, sp, #-186; CHECK-NEXT: cnth x887; CHECK-NEXT: mov w9, #8 // =0x888; CHECK-NEXT: str z0, [sp]89; CHECK-NEXT: sub x8, x8, #890; CHECK-NEXT: cmp x8, #891; CHECK-NEXT: csel x8, x8, x9, lo92; CHECK-NEXT: mov x9, sp93; CHECK-NEXT: lsl x8, x8, #194; CHECK-NEXT: str q1, [x9, x8]95; CHECK-NEXT: ldr z0, [sp]96; CHECK-NEXT: addvl sp, sp, #197; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload98; CHECK-NEXT: ret99 %retval = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec, i64 8)100 ret <vscale x 8 x i16> %retval101}102 103define <vscale x 16 x i8> @insert_v16i8_nxv16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind {104; CHECK-LABEL: insert_v16i8_nxv16i8:105; CHECK: // %bb.0:106; CHECK-NEXT: ptrue p0.b, vl16107; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1108; CHECK-NEXT: mov z0.b, p0/m, z1.b109; CHECK-NEXT: ret110 %retval = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec, i64 0)111 ret <vscale x 16 x i8> %retval112}113 114define <vscale x 16 x i8> @insert_v16i8_nxv16i8_idx16(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind {115; CHECK-LABEL: insert_v16i8_nxv16i8_idx16:116; CHECK: // %bb.0:117; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill118; CHECK-NEXT: addvl sp, sp, #-1119; CHECK-NEXT: rdvl x8, #1120; CHECK-NEXT: mov w9, #16 // =0x10121; CHECK-NEXT: str z0, [sp]122; CHECK-NEXT: sub x8, x8, #16123; CHECK-NEXT: cmp x8, #16124; CHECK-NEXT: csel x8, x8, x9, lo125; CHECK-NEXT: mov x9, sp126; CHECK-NEXT: str q1, [x9, x8]127; CHECK-NEXT: ldr z0, [sp]128; CHECK-NEXT: addvl sp, sp, #1129; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload130; CHECK-NEXT: ret131 %retval = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec, i64 16)132 ret <vscale x 16 x i8> %retval133}134 135 136; Insert subvectors into illegal vectors137 138define void @insert_nxv8i64_nxv16i64(<vscale x 8 x i64> %sv0, <vscale x 8 x i64> %sv1, ptr %out) {139; CHECK-LABEL: insert_nxv8i64_nxv16i64:140; CHECK: // %bb.0:141; CHECK-NEXT: str z7, [x0, #7, mul vl]142; CHECK-NEXT: str z6, [x0, #6, mul vl]143; CHECK-NEXT: str z5, [x0, #5, mul vl]144; CHECK-NEXT: str z4, [x0, #4, mul vl]145; CHECK-NEXT: str z3, [x0, #3, mul vl]146; CHECK-NEXT: str z2, [x0, #2, mul vl]147; CHECK-NEXT: str z1, [x0, #1, mul vl]148; CHECK-NEXT: str z0, [x0]149; CHECK-NEXT: ret150 %v0 = call <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> poison, <vscale x 8 x i64> %sv0, i64 0)151 %v = call <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> %v0, <vscale x 8 x i64> %sv1, i64 8)152 store <vscale x 16 x i64> %v, ptr %out153 ret void154}155 156define void @insert_nxv8i64_nxv16i64_lo(<vscale x 8 x i64> %sv0, ptr %out) {157; CHECK-LABEL: insert_nxv8i64_nxv16i64_lo:158; CHECK: // %bb.0:159; CHECK-NEXT: str z3, [x0, #3, mul vl]160; CHECK-NEXT: str z2, [x0, #2, mul vl]161; CHECK-NEXT: str z1, [x0, #1, mul vl]162; CHECK-NEXT: str z0, [x0]163; CHECK-NEXT: ret164 %v = call <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> poison, <vscale x 8 x i64> %sv0, i64 0)165 store <vscale x 16 x i64> %v, ptr %out166 ret void167}168 169define void @insert_nxv8i64_nxv16i64_hi(<vscale x 8 x i64> %sv0, ptr %out) {170; CHECK-LABEL: insert_nxv8i64_nxv16i64_hi:171; CHECK: // %bb.0:172; CHECK-NEXT: str z3, [x0, #7, mul vl]173; CHECK-NEXT: str z2, [x0, #6, mul vl]174; CHECK-NEXT: str z1, [x0, #5, mul vl]175; CHECK-NEXT: str z0, [x0, #4, mul vl]176; CHECK-NEXT: ret177 %v = call <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> poison, <vscale x 8 x i64> %sv0, i64 8)178 store <vscale x 16 x i64> %v, ptr %out179 ret void180}181 182define void @insert_v2i64_nxv16i64(<2 x i64> %sv0, <2 x i64> %sv1, ptr %out) uwtable {183; CHECK-LABEL: insert_v2i64_nxv16i64:184; CHECK: // %bb.0:185; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill186; CHECK-NEXT: .cfi_def_cfa_offset 16187; CHECK-NEXT: .cfi_offset w29, -16188; CHECK-NEXT: addvl sp, sp, #-4189; CHECK-NEXT: .cfi_escape 0x0f, 0x09, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0x20, 0x1e, 0x22 // sp + 16 + 32 * VG190; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0191; CHECK-NEXT: str z0, [sp]192; CHECK-NEXT: str q1, [sp, #32]193; CHECK-NEXT: ldr z0, [sp, #3, mul vl]194; CHECK-NEXT: ldr z1, [sp, #2, mul vl]195; CHECK-NEXT: ldr z2, [sp, #1, mul vl]196; CHECK-NEXT: ldr z3, [sp]197; CHECK-NEXT: str z0, [x0, #3, mul vl]198; CHECK-NEXT: str z1, [x0, #2, mul vl]199; CHECK-NEXT: str z2, [x0, #1, mul vl]200; CHECK-NEXT: str z3, [x0]201; CHECK-NEXT: addvl sp, sp, #4202; CHECK-NEXT: .cfi_def_cfa wsp, 16203; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload204; CHECK-NEXT: .cfi_def_cfa_offset 0205; CHECK-NEXT: .cfi_restore w29206; CHECK-NEXT: ret207 %v0 = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> poison, <2 x i64> %sv0, i64 0)208 %v = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> %v0, <2 x i64> %sv1, i64 4)209 store <vscale x 16 x i64> %v, ptr %out210 ret void211}212 213define void @insert_v2i64_nxv16i64_lo0(ptr %psv, ptr %out) {214; CHECK-LABEL: insert_v2i64_nxv16i64_lo0:215; CHECK: // %bb.0:216; CHECK-NEXT: ldr q0, [x0]217; CHECK-NEXT: str z0, [x1]218; CHECK-NEXT: ret219 %sv = load <2 x i64>, ptr %psv220 %v = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> poison, <2 x i64> %sv, i64 0)221 store <vscale x 16 x i64> %v, ptr %out222 ret void223}224 225define void @insert_v2i64_nxv16i64_lo2(ptr %psv, ptr %out) uwtable {226; CHECK-LABEL: insert_v2i64_nxv16i64_lo2:227; CHECK: // %bb.0:228; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill229; CHECK-NEXT: .cfi_def_cfa_offset 16230; CHECK-NEXT: .cfi_offset w29, -16231; CHECK-NEXT: addvl sp, sp, #-2232; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x40, 0x1e, 0x22 // sp + 16 + 16 * VG233; CHECK-NEXT: ldr q0, [x0]234; CHECK-NEXT: str q0, [sp, #16]235; CHECK-NEXT: ldr z0, [sp, #1, mul vl]236; CHECK-NEXT: ldr z1, [sp]237; CHECK-NEXT: str z0, [x1, #1, mul vl]238; CHECK-NEXT: str z1, [x1]239; CHECK-NEXT: addvl sp, sp, #2240; CHECK-NEXT: .cfi_def_cfa wsp, 16241; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload242; CHECK-NEXT: .cfi_def_cfa_offset 0243; CHECK-NEXT: .cfi_restore w29244; CHECK-NEXT: ret245 %sv = load <2 x i64>, ptr %psv246 %v = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> poison, <2 x i64> %sv, i64 2)247 store <vscale x 16 x i64> %v, ptr %out248 ret void249}250 251 252; Insert subvectors that need widening253 254define <vscale x 4 x i32> @insert_nxv1i32_nxv4i32_undef() nounwind {255; CHECK-LABEL: insert_nxv1i32_nxv4i32_undef:256; CHECK: // %bb.0: // %entry257; CHECK-NEXT: mov z0.s, #1 // =0x1258; CHECK-NEXT: ret259entry:260 %retval = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> poison, <vscale x 1 x i32> splat(i32 1), i64 0)261 ret <vscale x 4 x i32> %retval262}263 264define <vscale x 6 x i16> @insert_nxv1i16_nxv6i16_undef() nounwind {265; CHECK-LABEL: insert_nxv1i16_nxv6i16_undef:266; CHECK: // %bb.0: // %entry267; CHECK-NEXT: mov z0.h, #1 // =0x1268; CHECK-NEXT: ret269entry:270 %retval = call <vscale x 6 x i16> @llvm.vector.insert.nxv6i16.nxv1i16(<vscale x 6 x i16> poison, <vscale x 1 x i16> splat(i16 1), i64 0)271 ret <vscale x 6 x i16> %retval272}273 274define <vscale x 4 x float> @insert_nxv1f32_nxv4f32_undef(<vscale x 1 x float> %subvec) nounwind {275; CHECK-LABEL: insert_nxv1f32_nxv4f32_undef:276; CHECK: // %bb.0: // %entry277; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s278; CHECK-NEXT: ret279entry:280 %retval = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv1f32(<vscale x 4 x float> poison, <vscale x 1 x float> %subvec, i64 0)281 ret <vscale x 4 x float> %retval282}283 284; This tests promotion of the input operand to INSERT_SUBVECTOR.285define <vscale x 8 x i16> @insert_nxv8i16_nxv2i16(<vscale x 8 x i16> %vec, <vscale x 2 x i16> %in) nounwind {286; CHECK-LABEL: insert_nxv8i16_nxv2i16:287; CHECK: // %bb.0:288; CHECK-NEXT: uunpklo z2.s, z0.h289; CHECK-NEXT: uunpkhi z0.s, z0.h290; CHECK-NEXT: uunpklo z2.d, z2.s291; CHECK-NEXT: uzp1 z1.s, z2.s, z1.s292; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h293; CHECK-NEXT: ret294 %r = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv2i16(<vscale x 8 x i16> %vec, <vscale x 2 x i16> %in, i64 2)295 ret <vscale x 8 x i16> %r296}297 298define <vscale x 4 x half> @insert_nxv4f16_nxv2f16_0(<vscale x 4 x half> %sv0, <vscale x 2 x half> %sv1) nounwind {299; CHECK-LABEL: insert_nxv4f16_nxv2f16_0:300; CHECK: // %bb.0:301; CHECK-NEXT: uunpkhi z0.d, z0.s302; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s303; CHECK-NEXT: ret304 %v0 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> %sv0, <vscale x 2 x half> %sv1, i64 0)305 ret <vscale x 4 x half> %v0306}307 308define <vscale x 4 x half> @insert_nxv4f16_nxv2f16_2(<vscale x 4 x half> %sv0, <vscale x 2 x half> %sv1) nounwind {309; CHECK-LABEL: insert_nxv4f16_nxv2f16_2:310; CHECK: // %bb.0:311; CHECK-NEXT: uunpklo z0.d, z0.s312; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s313; CHECK-NEXT: ret314 %v0 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> %sv0, <vscale x 2 x half> %sv1, i64 2)315 ret <vscale x 4 x half> %v0316}317 318; Test that the index is scaled by vscale if the subvector is scalable.319define <vscale x 8 x half> @insert_nxv8f16_nxv2f16(<vscale x 8 x half> %vec, <vscale x 2 x half> %in) nounwind {320; CHECK-LABEL: insert_nxv8f16_nxv2f16:321; CHECK: // %bb.0:322; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill323; CHECK-NEXT: addvl sp, sp, #-1324; CHECK-NEXT: ptrue p0.d325; CHECK-NEXT: str z0, [sp]326; CHECK-NEXT: st1h { z1.d }, p0, [sp, #1, mul vl]327; CHECK-NEXT: ldr z0, [sp]328; CHECK-NEXT: addvl sp, sp, #1329; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload330; CHECK-NEXT: ret331 %r = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> %vec, <vscale x 2 x half> %in, i64 2)332 ret <vscale x 8 x half> %r333}334 335define <vscale x 8 x half> @insert_nxv8f16_nxv4f16_0(<vscale x 8 x half> %sv0, <vscale x 4 x half> %sv1) nounwind {336; CHECK-LABEL: insert_nxv8f16_nxv4f16_0:337; CHECK: // %bb.0:338; CHECK-NEXT: uunpkhi z0.s, z0.h339; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h340; CHECK-NEXT: ret341 %v0 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> %sv0, <vscale x 4 x half> %sv1, i64 0)342 ret <vscale x 8 x half> %v0343}344 345define <vscale x 8 x half> @insert_nxv8f16_nxv4f16_4(<vscale x 8 x half> %sv0, <vscale x 4 x half> %sv1) nounwind {346; CHECK-LABEL: insert_nxv8f16_nxv4f16_4:347; CHECK: // %bb.0:348; CHECK-NEXT: uunpklo z0.s, z0.h349; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h350; CHECK-NEXT: ret351 %v0 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> %sv0, <vscale x 4 x half> %sv1, i64 4)352 ret <vscale x 8 x half> %v0353}354 355; Fixed length clamping356 357define <vscale x 2 x i64> @insert_fixed_v2i64_nxv2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind #0 {358; CHECK-LABEL: insert_fixed_v2i64_nxv2i64:359; CHECK: // %bb.0:360; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill361; CHECK-NEXT: addvl sp, sp, #-1362; CHECK-NEXT: str z0, [sp]363; CHECK-NEXT: str q1, [sp, #16]364; CHECK-NEXT: ldr z0, [sp]365; CHECK-NEXT: addvl sp, sp, #1366; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload367; CHECK-NEXT: ret368 %retval = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 2)369 ret <vscale x 2 x i64> %retval370}371 372define <vscale x 2 x i64> @insert_fixed_v4i64_nxv2i64(<vscale x 2 x i64> %vec, ptr %ptr) nounwind #0 {373; CHECK-LABEL: insert_fixed_v4i64_nxv2i64:374; CHECK: // %bb.0:375; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill376; CHECK-NEXT: addvl sp, sp, #-1377; CHECK-NEXT: ldr z0, [x0]378; CHECK-NEXT: addvl sp, sp, #1379; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload380; CHECK-NEXT: ret381 %subvec = load <4 x i64>, ptr %ptr382 %retval = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> %vec, <4 x i64> %subvec, i64 4)383 ret <vscale x 2 x i64> %retval384}385 386;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;387;; Upacked types that need result widening388;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;389 390define <vscale x 3 x i32> @insert_nxv3i32_nxv2i32(<vscale x 2 x i32> %sv0) {391; CHECK-LABEL: insert_nxv3i32_nxv2i32:392; CHECK: // %bb.0:393; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s394; CHECK-NEXT: ret395 %v0 = call <vscale x 3 x i32> @llvm.vector.insert.nxv3i32.nxv2i32(<vscale x 3 x i32> poison, <vscale x 2 x i32> %sv0, i64 0)396 ret <vscale x 3 x i32> %v0397}398 399;; Check that the Subvector is not widen so it does not crash.400define <vscale x 3 x i32> @insert_nxv3i32_nxv2i32_2(<vscale x 3 x i32> %sv0, <vscale x 2 x i32> %sv1) {401; CHECK-LABEL: insert_nxv3i32_nxv2i32_2:402; CHECK: // %bb.0:403; CHECK-NEXT: uunpkhi z0.d, z0.s404; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s405; CHECK-NEXT: ret406 %v0 = call <vscale x 3 x i32> @llvm.vector.insert.nxv3i32.nxv2i32(<vscale x 3 x i32> %sv0, <vscale x 2 x i32> %sv1, i64 0)407 ret <vscale x 3 x i32> %v0408}409 410define <vscale x 3 x float> @insert_nxv3f32_nxv2f32(<vscale x 2 x float> %sv0) nounwind {411; CHECK-LABEL: insert_nxv3f32_nxv2f32:412; CHECK: // %bb.0:413; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s414; CHECK-NEXT: ret415 %v0 = call <vscale x 3 x float> @llvm.vector.insert.nxv3f32.nxv2f32(<vscale x 3 x float> poison, <vscale x 2 x float> %sv0, i64 0)416 ret <vscale x 3 x float> %v0417}418 419define <vscale x 4 x float> @insert_nxv4f32_nxv2f32_0(<vscale x 4 x float> %sv0, <vscale x 2 x float> %sv1) nounwind {420; CHECK-LABEL: insert_nxv4f32_nxv2f32_0:421; CHECK: // %bb.0:422; CHECK-NEXT: uunpkhi z0.d, z0.s423; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s424; CHECK-NEXT: ret425 %v0 = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> %sv0, <vscale x 2 x float> %sv1, i64 0)426 ret <vscale x 4 x float> %v0427}428 429define <vscale x 4 x float> @insert_nxv4f32_nxv2f32_2(<vscale x 4 x float> %sv0, <vscale x 2 x float> %sv1) nounwind {430; CHECK-LABEL: insert_nxv4f32_nxv2f32_2:431; CHECK: // %bb.0:432; CHECK-NEXT: uunpklo z0.d, z0.s433; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s434; CHECK-NEXT: ret435 %v0 = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> %sv0, <vscale x 2 x float> %sv1, i64 2)436 ret <vscale x 4 x float> %v0437}438 439define <vscale x 6 x i32> @insert_nxv6i32_nxv2i32(<vscale x 2 x i32> %sv0, <vscale x 2 x i32> %sv1) nounwind {440; CHECK-LABEL: insert_nxv6i32_nxv2i32:441; CHECK: // %bb.0:442; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill443; CHECK-NEXT: addvl sp, sp, #-2444; CHECK-NEXT: ldr z2, [sp, #1, mul vl]445; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s446; CHECK-NEXT: mov z1.d, z2.d447; CHECK-NEXT: str z0, [sp]448; CHECK-NEXT: addvl sp, sp, #2449; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload450; CHECK-NEXT: ret451 %v0 = call <vscale x 6 x i32> @llvm.vector.insert.nxv6i32.nxv2i32(<vscale x 6 x i32> poison, <vscale x 2 x i32> %sv0, i64 0)452 %v1 = call <vscale x 6 x i32> @llvm.vector.insert.nxv6i32.nxv2i32(<vscale x 6 x i32> %v0, <vscale x 2 x i32> %sv1, i64 2)453 ret <vscale x 6 x i32> %v1454}455 456;; This only works because the input vector is undef and index is zero457define <vscale x 6 x i32> @insert_nxv6i32_nxv3i32(<vscale x 3 x i32> %sv0) {458; CHECK-LABEL: insert_nxv6i32_nxv3i32:459; CHECK: // %bb.0:460; CHECK-NEXT: ret461 %v0 = call <vscale x 6 x i32> @llvm.vector.insert.nxv6i32.nxv3i32(<vscale x 6 x i32> poison, <vscale x 3 x i32> %sv0, i64 0)462 ret <vscale x 6 x i32> %v0463}464 465define <vscale x 12 x i32> @insert_nxv12i32_nxv4i32(<vscale x 4 x i32> %sv0, <vscale x 4 x i32> %sv1, <vscale x 4 x i32> %sv2) {466; CHECK-LABEL: insert_nxv12i32_nxv4i32:467; CHECK: // %bb.0:468; CHECK-NEXT: ret469 %v0 = call <vscale x 12 x i32> @llvm.vector.insert.nxv4i32.nxv12i32(<vscale x 12 x i32> poison, <vscale x 4 x i32> %sv0, i64 0)470 %v1 = call <vscale x 12 x i32> @llvm.vector.insert.nxv4i32.nxv12i32(<vscale x 12 x i32> %v0, <vscale x 4 x i32> %sv1, i64 4)471 %v2 = call <vscale x 12 x i32> @llvm.vector.insert.nxv4i32.nxv12i32(<vscale x 12 x i32> %v1, <vscale x 4 x i32> %sv2, i64 8)472 ret <vscale x 12 x i32> %v2473}474 475define <vscale x 2 x bfloat> @insert_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1) nounwind {476; CHECK-LABEL: insert_nxv2bf16_nxv2bf16:477; CHECK: // %bb.0:478; CHECK-NEXT: mov z0.d, z1.d479; CHECK-NEXT: ret480 %v0 = call <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv2bf16(<vscale x 2 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1, i64 0)481 ret <vscale x 2 x bfloat> %v0482}483 484define <vscale x 4 x bfloat> @insert_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1) nounwind {485; CHECK-LABEL: insert_nxv4bf16_nxv4bf16:486; CHECK: // %bb.0:487; CHECK-NEXT: mov z0.d, z1.d488; CHECK-NEXT: ret489 %v0 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv4bf16(<vscale x 4 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1, i64 0)490 ret <vscale x 4 x bfloat> %v0491}492 493define <vscale x 4 x bfloat> @insert_nxv4bf16_v4bf16(<vscale x 4 x bfloat> %sv0, <4 x bfloat> %v1) nounwind {494; CHECK-LABEL: insert_nxv4bf16_v4bf16:495; CHECK: // %bb.0:496; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill497; CHECK-NEXT: addvl sp, sp, #-1498; CHECK-NEXT: ptrue p0.s499; CHECK-NEXT: addpl x8, sp, #4500; CHECK-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]501; CHECK-NEXT: str d1, [x8]502; CHECK-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]503; CHECK-NEXT: addvl sp, sp, #1504; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload505; CHECK-NEXT: ret506 %v0 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.v4bf16(<vscale x 4 x bfloat> %sv0, <4 x bfloat> %v1, i64 0)507 ret <vscale x 4 x bfloat> %v0508}509 510define <vscale x 8 x bfloat> @insert_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %sv0, <vscale x 8 x bfloat> %sv1) nounwind {511; CHECK-LABEL: insert_nxv8bf16_nxv8bf16:512; CHECK: // %bb.0:513; CHECK-NEXT: mov z0.d, z1.d514; CHECK-NEXT: ret515 %v0 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv8bf16(<vscale x 8 x bfloat> %sv0, <vscale x 8 x bfloat> %sv1, i64 0)516 ret <vscale x 8 x bfloat> %v0517}518 519define <vscale x 8 x bfloat> @insert_nxv8bf16_v8bf16(<vscale x 8 x bfloat> %sv0, <8 x bfloat> %v1) nounwind {520; CHECK-LABEL: insert_nxv8bf16_v8bf16:521; CHECK: // %bb.0:522; CHECK-NEXT: ptrue p0.h, vl8523; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1524; CHECK-NEXT: mov z0.h, p0/m, z1.h525; CHECK-NEXT: ret526 %v0 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> %sv0, <8 x bfloat> %v1, i64 0)527 ret <vscale x 8 x bfloat> %v0528}529 530define <vscale x 8 x bfloat> @insert_nxv8bf16_nxv4bf16_0(<vscale x 8 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1) nounwind {531; CHECK-LABEL: insert_nxv8bf16_nxv4bf16_0:532; CHECK: // %bb.0:533; CHECK-NEXT: uunpkhi z0.s, z0.h534; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h535; CHECK-NEXT: ret536 %v0 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1, i64 0)537 ret <vscale x 8 x bfloat> %v0538}539 540define <vscale x 8 x bfloat> @insert_nxv8bf16_nxv4bf16_4(<vscale x 8 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1) nounwind {541; CHECK-LABEL: insert_nxv8bf16_nxv4bf16_4:542; CHECK: // %bb.0:543; CHECK-NEXT: uunpklo z0.s, z0.h544; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h545; CHECK-NEXT: ret546 %v0 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1, i64 4)547 ret <vscale x 8 x bfloat> %v0548}549 550define <vscale x 4 x bfloat> @insert_nxv4bf16_nxv2bf16_0(<vscale x 4 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1) nounwind {551; CHECK-LABEL: insert_nxv4bf16_nxv2bf16_0:552; CHECK: // %bb.0:553; CHECK-NEXT: uunpkhi z0.d, z0.s554; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s555; CHECK-NEXT: ret556 %v0 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1, i64 0)557 ret <vscale x 4 x bfloat> %v0558}559 560define <vscale x 4 x bfloat> @insert_nxv4bf16_nxv2bf16_2(<vscale x 4 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1) nounwind {561; CHECK-LABEL: insert_nxv4bf16_nxv2bf16_2:562; CHECK: // %bb.0:563; CHECK-NEXT: uunpklo z0.d, z0.s564; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s565; CHECK-NEXT: ret566 %v0 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1, i64 2)567 ret <vscale x 4 x bfloat> %v0568}569 570; Test predicate inserts of half size.571define <vscale x 16 x i1> @insert_nxv16i1_nxv8i1_0(<vscale x 16 x i1> %vec, <vscale x 8 x i1> %sv) {572; CHECK-LABEL: insert_nxv16i1_nxv8i1_0:573; CHECK: // %bb.0:574; CHECK-NEXT: punpkhi p0.h, p0.b575; CHECK-NEXT: uzp1 p0.b, p1.b, p0.b576; CHECK-NEXT: ret577 %v0 = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv8i1(<vscale x 16 x i1> %vec, <vscale x 8 x i1> %sv, i64 0)578 ret <vscale x 16 x i1> %v0579}580 581define <vscale x 16 x i1> @insert_nxv16i1_nxv8i1_8(<vscale x 16 x i1> %vec, <vscale x 8 x i1> %sv) {582; CHECK-LABEL: insert_nxv16i1_nxv8i1_8:583; CHECK: // %bb.0:584; CHECK-NEXT: punpklo p0.h, p0.b585; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b586; CHECK-NEXT: ret587 %v0 = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv8i1(<vscale x 16 x i1> %vec, <vscale x 8 x i1> %sv, i64 8)588 ret <vscale x 16 x i1> %v0589}590 591; Test predicate inserts of less than half the size.592define <vscale x 16 x i1> @insert_nxv16i1_nxv4i1_0(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %sv) {593; CHECK-LABEL: insert_nxv16i1_nxv4i1_0:594; CHECK: // %bb.0:595; CHECK-NEXT: punpklo p2.h, p0.b596; CHECK-NEXT: punpkhi p0.h, p0.b597; CHECK-NEXT: punpkhi p2.h, p2.b598; CHECK-NEXT: uzp1 p1.h, p1.h, p2.h599; CHECK-NEXT: uzp1 p0.b, p1.b, p0.b600; CHECK-NEXT: ret601 %v0 = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %sv, i64 0)602 ret <vscale x 16 x i1> %v0603}604 605define <vscale x 16 x i1> @insert_nxv16i1_nxv4i1_12(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %sv) {606; CHECK-LABEL: insert_nxv16i1_nxv4i1_12:607; CHECK: // %bb.0:608; CHECK-NEXT: punpkhi p2.h, p0.b609; CHECK-NEXT: punpklo p0.h, p0.b610; CHECK-NEXT: punpklo p2.h, p2.b611; CHECK-NEXT: uzp1 p1.h, p2.h, p1.h612; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b613; CHECK-NEXT: ret614 %v0 = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %sv, i64 12)615 ret <vscale x 16 x i1> %v0616}617 618; Test predicate insert into undef/zero619define <vscale x 16 x i1> @insert_nxv16i1_nxv4i1_into_zero(<vscale x 4 x i1> %sv) {620; CHECK-LABEL: insert_nxv16i1_nxv4i1_into_zero:621; CHECK: // %bb.0:622; CHECK-NEXT: pfalse p1.b623; CHECK-NEXT: uzp1 p0.h, p0.h, p1.h624; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b625; CHECK-NEXT: ret626 %v0 = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> zeroinitializer, <vscale x 4 x i1> %sv, i64 0)627 ret <vscale x 16 x i1> %v0628}629 630define <vscale x 16 x i1> @insert_nxv16i1_nxv4i1_into_poison(<vscale x 4 x i1> %sv) {631; CHECK-LABEL: insert_nxv16i1_nxv4i1_into_poison:632; CHECK: // %bb.0:633; CHECK-NEXT: uzp1 p0.h, p0.h, p0.h634; CHECK-NEXT: uzp1 p0.b, p0.b, p0.b635; CHECK-NEXT: ret636 %v0 = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> poison, <vscale x 4 x i1> %sv, i64 0)637 ret <vscale x 16 x i1> %v0638}639 640; Test constant predicate insert into undef641define <vscale x 2 x i1> @insert_nxv2i1_v8i1_const_true_into_undef() vscale_range(4,8) {642; CHECK-LABEL: insert_nxv2i1_v8i1_const_true_into_undef:643; CHECK: // %bb.0:644; CHECK-NEXT: ptrue p0.d645; CHECK-NEXT: ret646 %v0 = call <vscale x 2 x i1> @llvm.vector.insert.nxv2i1.v8i1 (<vscale x 2 x i1> poison, <8 x i1> splat (i1 true), i64 0)647 ret <vscale x 2 x i1> %v0648}649 650define <vscale x 4 x i1> @insert_nxv4i1_v16i1_const_true_into_undef() vscale_range(4,8) {651; CHECK-LABEL: insert_nxv4i1_v16i1_const_true_into_undef:652; CHECK: // %bb.0:653; CHECK-NEXT: ptrue p0.s654; CHECK-NEXT: ret655 %v0 = call <vscale x 4 x i1> @llvm.vector.insert.nxv4i1.v16i1 (<vscale x 4 x i1> poison, <16 x i1> splat (i1 true), i64 0)656 ret <vscale x 4 x i1> %v0657}658 659define <vscale x 8 x i1> @insert_nxv8i1_v32i1_const_true_into_undef() vscale_range(4,8) {660; CHECK-LABEL: insert_nxv8i1_v32i1_const_true_into_undef:661; CHECK: // %bb.0:662; CHECK-NEXT: ptrue p0.h663; CHECK-NEXT: ret664 %v0 = call <vscale x 8 x i1> @llvm.vector.insert.nxv8i1.v32i1 (<vscale x 8 x i1> poison, <32 x i1> splat (i1 true), i64 0)665 ret <vscale x 8 x i1> %v0666}667 668define <vscale x 16 x i1> @insert_nxv16i1_v64i1_const_true_into_undef() vscale_range(4,8) {669; CHECK-LABEL: insert_nxv16i1_v64i1_const_true_into_undef:670; CHECK: // %bb.0:671; CHECK-NEXT: ptrue p0.b672; CHECK-NEXT: ret673 %v0 = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.v64i1 (<vscale x 16 x i1> poison, <64 x i1> splat (i1 true), i64 0)674 ret <vscale x 16 x i1> %v0675}676 677;678; Insert nxv1i1 type into: nxv2i1679;680 681define <vscale x 2 x i1> @insert_nxv1i1_nxv2i1_0(<vscale x 2 x i1> %vec, <vscale x 1 x i1> %sv) {682; CHECK-LABEL: insert_nxv1i1_nxv2i1_0:683; CHECK: // %bb.0:684; CHECK-NEXT: punpkhi p0.h, p0.b685; CHECK-NEXT: uzp1 p0.d, p1.d, p0.d686; CHECK-NEXT: ret687 %res = call <vscale x 2 x i1> @llvm.vector.insert.nxv2i1.nxv1i1(<vscale x 2 x i1> %vec, <vscale x 1 x i1> %sv, i64 0)688 ret <vscale x 2 x i1> %res689}690 691define <vscale x 2 x i1> @insert_nxv1i1_nxv2i1_1(<vscale x 2 x i1> %vec, <vscale x 1 x i1> %sv) {692; CHECK-LABEL: insert_nxv1i1_nxv2i1_1:693; CHECK: // %bb.0:694; CHECK-NEXT: punpklo p0.h, p0.b695; CHECK-NEXT: uzp1 p0.d, p0.d, p1.d696; CHECK-NEXT: ret697 %res = call <vscale x 2 x i1> @llvm.vector.insert.nxv2i1.nxv1i1(<vscale x 2 x i1> %vec, <vscale x 1 x i1> %sv, i64 1)698 ret <vscale x 2 x i1> %res699}700 701;702; Insert nxv1i1 type into: nxv4i1703;704 705define <vscale x 4 x i1> @insert_nxv1i1_nxv4i1_0(<vscale x 4 x i1> %vec, <vscale x 1 x i1> %sv) {706; CHECK-LABEL: insert_nxv1i1_nxv4i1_0:707; CHECK: // %bb.0:708; CHECK-NEXT: punpklo p2.h, p0.b709; CHECK-NEXT: punpkhi p0.h, p0.b710; CHECK-NEXT: punpkhi p2.h, p2.b711; CHECK-NEXT: uzp1 p1.d, p1.d, p2.d712; CHECK-NEXT: uzp1 p0.s, p1.s, p0.s713; CHECK-NEXT: ret714 %res = call <vscale x 4 x i1> @llvm.vector.insert.nxv4i1.nxv1i1(<vscale x 4 x i1> %vec, <vscale x 1 x i1> %sv, i64 0)715 ret <vscale x 4 x i1> %res716}717 718define <vscale x 4 x i1> @insert_nxv1i1_nxv4i1_1(<vscale x 4 x i1> %vec, <vscale x 1 x i1> %sv) {719; CHECK-LABEL: insert_nxv1i1_nxv4i1_1:720; CHECK: // %bb.0:721; CHECK-NEXT: punpklo p2.h, p0.b722; CHECK-NEXT: punpkhi p0.h, p0.b723; CHECK-NEXT: punpklo p2.h, p2.b724; CHECK-NEXT: uzp1 p1.d, p2.d, p1.d725; CHECK-NEXT: uzp1 p0.s, p1.s, p0.s726; CHECK-NEXT: ret727 %res = call <vscale x 4 x i1> @llvm.vector.insert.nxv4i1.nxv1i1(<vscale x 4 x i1> %vec, <vscale x 1 x i1> %sv, i64 1)728 ret <vscale x 4 x i1> %res729}730 731define <vscale x 4 x i1> @insert_nxv1i1_nxv4i1_2(<vscale x 4 x i1> %vec, <vscale x 1 x i1> %sv) {732; CHECK-LABEL: insert_nxv1i1_nxv4i1_2:733; CHECK: // %bb.0:734; CHECK-NEXT: punpkhi p2.h, p0.b735; CHECK-NEXT: punpklo p0.h, p0.b736; CHECK-NEXT: punpkhi p2.h, p2.b737; CHECK-NEXT: uzp1 p1.d, p1.d, p2.d738; CHECK-NEXT: uzp1 p0.s, p0.s, p1.s739; CHECK-NEXT: ret740 %res = call <vscale x 4 x i1> @llvm.vector.insert.nxv4i1.nxv1i1(<vscale x 4 x i1> %vec, <vscale x 1 x i1> %sv, i64 2)741 ret <vscale x 4 x i1> %res742}743 744define <vscale x 4 x i1> @insert_nxv1i1_nxv4i1_3(<vscale x 4 x i1> %vec, <vscale x 1 x i1> %sv) {745; CHECK-LABEL: insert_nxv1i1_nxv4i1_3:746; CHECK: // %bb.0:747; CHECK-NEXT: punpkhi p2.h, p0.b748; CHECK-NEXT: punpklo p0.h, p0.b749; CHECK-NEXT: punpklo p2.h, p2.b750; CHECK-NEXT: uzp1 p1.d, p2.d, p1.d751; CHECK-NEXT: uzp1 p0.s, p0.s, p1.s752; CHECK-NEXT: ret753 %res = call <vscale x 4 x i1> @llvm.vector.insert.nxv4i1.nxv1i1(<vscale x 4 x i1> %vec, <vscale x 1 x i1> %sv, i64 3)754 ret <vscale x 4 x i1> %res755}756 757;758; Insert nxv1i1 type into: nxv8i1759;760 761define <vscale x 8 x i1> @insert_nxv1i1_nxv8i1_0(<vscale x 8 x i1> %vec, <vscale x 1 x i1> %sv) {762; CHECK-LABEL: insert_nxv1i1_nxv8i1_0:763; CHECK: // %bb.0:764; CHECK-NEXT: punpklo p2.h, p0.b765; CHECK-NEXT: punpkhi p0.h, p0.b766; CHECK-NEXT: punpklo p3.h, p2.b767; CHECK-NEXT: punpkhi p2.h, p2.b768; CHECK-NEXT: punpkhi p3.h, p3.b769; CHECK-NEXT: uzp1 p1.d, p1.d, p3.d770; CHECK-NEXT: uzp1 p1.s, p1.s, p2.s771; CHECK-NEXT: uzp1 p0.h, p1.h, p0.h772; CHECK-NEXT: ret773 %res = call <vscale x 8 x i1> @llvm.vector.insert.nxv8i1.nxv1i1(<vscale x 8 x i1> %vec, <vscale x 1 x i1> %sv, i64 0)774 ret <vscale x 8 x i1> %res775}776 777define <vscale x 8 x i1> @insert_nxv1i1_nxv8i1_1(<vscale x 8 x i1> %vec, <vscale x 1 x i1> %sv) {778; CHECK-LABEL: insert_nxv1i1_nxv8i1_1:779; CHECK: // %bb.0:780; CHECK-NEXT: punpklo p2.h, p0.b781; CHECK-NEXT: punpkhi p0.h, p0.b782; CHECK-NEXT: punpklo p3.h, p2.b783; CHECK-NEXT: punpkhi p2.h, p2.b784; CHECK-NEXT: punpklo p3.h, p3.b785; CHECK-NEXT: uzp1 p1.d, p3.d, p1.d786; CHECK-NEXT: uzp1 p1.s, p1.s, p2.s787; CHECK-NEXT: uzp1 p0.h, p1.h, p0.h788; CHECK-NEXT: ret789 %res = call <vscale x 8 x i1> @llvm.vector.insert.nxv8i1.nxv1i1(<vscale x 8 x i1> %vec, <vscale x 1 x i1> %sv, i64 1)790 ret <vscale x 8 x i1> %res791}792 793define <vscale x 8 x i1> @insert_nxv1i1_nxv8i1_2(<vscale x 8 x i1> %vec, <vscale x 1 x i1> %sv) {794; CHECK-LABEL: insert_nxv1i1_nxv8i1_2:795; CHECK: // %bb.0:796; CHECK-NEXT: punpklo p2.h, p0.b797; CHECK-NEXT: punpkhi p0.h, p0.b798; CHECK-NEXT: punpkhi p3.h, p2.b799; CHECK-NEXT: punpklo p2.h, p2.b800; CHECK-NEXT: punpkhi p3.h, p3.b801; CHECK-NEXT: uzp1 p1.d, p1.d, p3.d802; CHECK-NEXT: uzp1 p1.s, p2.s, p1.s803; CHECK-NEXT: uzp1 p0.h, p1.h, p0.h804; CHECK-NEXT: ret805 %res = call <vscale x 8 x i1> @llvm.vector.insert.nxv8i1.nxv1i1(<vscale x 8 x i1> %vec, <vscale x 1 x i1> %sv, i64 2)806 ret <vscale x 8 x i1> %res807}808 809define <vscale x 8 x i1> @insert_nxv1i1_nxv8i1_3(<vscale x 8 x i1> %vec, <vscale x 1 x i1> %sv) {810; CHECK-LABEL: insert_nxv1i1_nxv8i1_3:811; CHECK: // %bb.0:812; CHECK-NEXT: punpklo p2.h, p0.b813; CHECK-NEXT: punpkhi p0.h, p0.b814; CHECK-NEXT: punpkhi p3.h, p2.b815; CHECK-NEXT: punpklo p2.h, p2.b816; CHECK-NEXT: punpklo p3.h, p3.b817; CHECK-NEXT: uzp1 p1.d, p3.d, p1.d818; CHECK-NEXT: uzp1 p1.s, p2.s, p1.s819; CHECK-NEXT: uzp1 p0.h, p1.h, p0.h820; CHECK-NEXT: ret821 %res = call <vscale x 8 x i1> @llvm.vector.insert.nxv8i1.nxv1i1(<vscale x 8 x i1> %vec, <vscale x 1 x i1> %sv, i64 3)822 ret <vscale x 8 x i1> %res823}824 825define <vscale x 8 x i1> @insert_nxv1i1_nxv8i1_4(<vscale x 8 x i1> %vec, <vscale x 1 x i1> %sv) {826; CHECK-LABEL: insert_nxv1i1_nxv8i1_4:827; CHECK: // %bb.0:828; CHECK-NEXT: punpkhi p2.h, p0.b829; CHECK-NEXT: punpklo p0.h, p0.b830; CHECK-NEXT: punpklo p3.h, p2.b831; CHECK-NEXT: punpkhi p2.h, p2.b832; CHECK-NEXT: punpkhi p3.h, p3.b833; CHECK-NEXT: uzp1 p1.d, p1.d, p3.d834; CHECK-NEXT: uzp1 p1.s, p1.s, p2.s835; CHECK-NEXT: uzp1 p0.h, p0.h, p1.h836; CHECK-NEXT: ret837 %res = call <vscale x 8 x i1> @llvm.vector.insert.nxv8i1.nxv1i1(<vscale x 8 x i1> %vec, <vscale x 1 x i1> %sv, i64 4)838 ret <vscale x 8 x i1> %res839}840 841define <vscale x 8 x i1> @insert_nxv1i1_nxv8i1_5(<vscale x 8 x i1> %vec, <vscale x 1 x i1> %sv) {842; CHECK-LABEL: insert_nxv1i1_nxv8i1_5:843; CHECK: // %bb.0:844; CHECK-NEXT: punpkhi p2.h, p0.b845; CHECK-NEXT: punpklo p0.h, p0.b846; CHECK-NEXT: punpklo p3.h, p2.b847; CHECK-NEXT: punpkhi p2.h, p2.b848; CHECK-NEXT: punpklo p3.h, p3.b849; CHECK-NEXT: uzp1 p1.d, p3.d, p1.d850; CHECK-NEXT: uzp1 p1.s, p1.s, p2.s851; CHECK-NEXT: uzp1 p0.h, p0.h, p1.h852; CHECK-NEXT: ret853 %res = call <vscale x 8 x i1> @llvm.vector.insert.nxv8i1.nxv1i1(<vscale x 8 x i1> %vec, <vscale x 1 x i1> %sv, i64 5)854 ret <vscale x 8 x i1> %res855}856 857define <vscale x 8 x i1> @insert_nxv1i1_nxv8i1_6(<vscale x 8 x i1> %vec, <vscale x 1 x i1> %sv) {858; CHECK-LABEL: insert_nxv1i1_nxv8i1_6:859; CHECK: // %bb.0:860; CHECK-NEXT: punpkhi p2.h, p0.b861; CHECK-NEXT: punpklo p0.h, p0.b862; CHECK-NEXT: punpkhi p3.h, p2.b863; CHECK-NEXT: punpklo p2.h, p2.b864; CHECK-NEXT: punpkhi p3.h, p3.b865; CHECK-NEXT: uzp1 p1.d, p1.d, p3.d866; CHECK-NEXT: uzp1 p1.s, p2.s, p1.s867; CHECK-NEXT: uzp1 p0.h, p0.h, p1.h868; CHECK-NEXT: ret869 %res = call <vscale x 8 x i1> @llvm.vector.insert.nxv8i1.nxv1i1(<vscale x 8 x i1> %vec, <vscale x 1 x i1> %sv, i64 6)870 ret <vscale x 8 x i1> %res871}872 873define <vscale x 8 x i1> @insert_nxv1i1_nxv8i1_7(<vscale x 8 x i1> %vec, <vscale x 1 x i1> %sv) {874; CHECK-LABEL: insert_nxv1i1_nxv8i1_7:875; CHECK: // %bb.0:876; CHECK-NEXT: punpkhi p2.h, p0.b877; CHECK-NEXT: punpklo p0.h, p0.b878; CHECK-NEXT: punpkhi p3.h, p2.b879; CHECK-NEXT: punpklo p2.h, p2.b880; CHECK-NEXT: punpklo p3.h, p3.b881; CHECK-NEXT: uzp1 p1.d, p3.d, p1.d882; CHECK-NEXT: uzp1 p1.s, p2.s, p1.s883; CHECK-NEXT: uzp1 p0.h, p0.h, p1.h884; CHECK-NEXT: ret885 %res = call <vscale x 8 x i1> @llvm.vector.insert.nxv8i1.nxv1i1(<vscale x 8 x i1> %vec, <vscale x 1 x i1> %sv, i64 7)886 ret <vscale x 8 x i1> %res887}888 889;890; Insert nxv1i1 type into: nxv16i1891;892 893define <vscale x 16 x i1> @insert_nxv1i1_nxv16i1_0(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv) {894; CHECK-LABEL: insert_nxv1i1_nxv16i1_0:895; CHECK: // %bb.0:896; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill897; CHECK-NEXT: addvl sp, sp, #-1898; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill899; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG900; CHECK-NEXT: .cfi_offset w29, -16901; CHECK-NEXT: punpklo p2.h, p0.b902; CHECK-NEXT: punpkhi p0.h, p0.b903; CHECK-NEXT: punpklo p3.h, p2.b904; CHECK-NEXT: punpkhi p2.h, p2.b905; CHECK-NEXT: punpklo p4.h, p3.b906; CHECK-NEXT: punpkhi p3.h, p3.b907; CHECK-NEXT: punpkhi p4.h, p4.b908; CHECK-NEXT: uzp1 p1.d, p1.d, p4.d909; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload910; CHECK-NEXT: uzp1 p1.s, p1.s, p3.s911; CHECK-NEXT: uzp1 p1.h, p1.h, p2.h912; CHECK-NEXT: uzp1 p0.b, p1.b, p0.b913; CHECK-NEXT: addvl sp, sp, #1914; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload915; CHECK-NEXT: ret916 %res = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv1i1(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv, i64 0)917 ret <vscale x 16 x i1> %res918}919 920define <vscale x 16 x i1> @insert_nxv1i1_nxv16i1_1(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv) {921; CHECK-LABEL: insert_nxv1i1_nxv16i1_1:922; CHECK: // %bb.0:923; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill924; CHECK-NEXT: addvl sp, sp, #-1925; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill926; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG927; CHECK-NEXT: .cfi_offset w29, -16928; CHECK-NEXT: punpklo p2.h, p0.b929; CHECK-NEXT: punpkhi p0.h, p0.b930; CHECK-NEXT: punpklo p3.h, p2.b931; CHECK-NEXT: punpkhi p2.h, p2.b932; CHECK-NEXT: punpklo p4.h, p3.b933; CHECK-NEXT: punpkhi p3.h, p3.b934; CHECK-NEXT: punpklo p4.h, p4.b935; CHECK-NEXT: uzp1 p1.d, p4.d, p1.d936; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload937; CHECK-NEXT: uzp1 p1.s, p1.s, p3.s938; CHECK-NEXT: uzp1 p1.h, p1.h, p2.h939; CHECK-NEXT: uzp1 p0.b, p1.b, p0.b940; CHECK-NEXT: addvl sp, sp, #1941; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload942; CHECK-NEXT: ret943 %res = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv1i1(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv, i64 1)944 ret <vscale x 16 x i1> %res945}946 947define <vscale x 16 x i1> @insert_nxv1i1_nxv16i1_2(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv) {948; CHECK-LABEL: insert_nxv1i1_nxv16i1_2:949; CHECK: // %bb.0:950; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill951; CHECK-NEXT: addvl sp, sp, #-1952; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill953; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG954; CHECK-NEXT: .cfi_offset w29, -16955; CHECK-NEXT: punpklo p2.h, p0.b956; CHECK-NEXT: punpkhi p0.h, p0.b957; CHECK-NEXT: punpklo p3.h, p2.b958; CHECK-NEXT: punpkhi p2.h, p2.b959; CHECK-NEXT: punpkhi p4.h, p3.b960; CHECK-NEXT: punpklo p3.h, p3.b961; CHECK-NEXT: punpkhi p4.h, p4.b962; CHECK-NEXT: uzp1 p1.d, p1.d, p4.d963; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload964; CHECK-NEXT: uzp1 p1.s, p3.s, p1.s965; CHECK-NEXT: uzp1 p1.h, p1.h, p2.h966; CHECK-NEXT: uzp1 p0.b, p1.b, p0.b967; CHECK-NEXT: addvl sp, sp, #1968; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload969; CHECK-NEXT: ret970 %res = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv1i1(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv, i64 2)971 ret <vscale x 16 x i1> %res972}973 974define <vscale x 16 x i1> @insert_nxv1i1_nxv16i1_3(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv) {975; CHECK-LABEL: insert_nxv1i1_nxv16i1_3:976; CHECK: // %bb.0:977; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill978; CHECK-NEXT: addvl sp, sp, #-1979; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill980; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG981; CHECK-NEXT: .cfi_offset w29, -16982; CHECK-NEXT: punpklo p2.h, p0.b983; CHECK-NEXT: punpkhi p0.h, p0.b984; CHECK-NEXT: punpklo p3.h, p2.b985; CHECK-NEXT: punpkhi p2.h, p2.b986; CHECK-NEXT: punpkhi p4.h, p3.b987; CHECK-NEXT: punpklo p3.h, p3.b988; CHECK-NEXT: punpklo p4.h, p4.b989; CHECK-NEXT: uzp1 p1.d, p4.d, p1.d990; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload991; CHECK-NEXT: uzp1 p1.s, p3.s, p1.s992; CHECK-NEXT: uzp1 p1.h, p1.h, p2.h993; CHECK-NEXT: uzp1 p0.b, p1.b, p0.b994; CHECK-NEXT: addvl sp, sp, #1995; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload996; CHECK-NEXT: ret997 %res = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv1i1(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv, i64 3)998 ret <vscale x 16 x i1> %res999}1000 1001define <vscale x 16 x i1> @insert_nxv1i1_nxv16i1_4(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv) {1002; CHECK-LABEL: insert_nxv1i1_nxv16i1_4:1003; CHECK: // %bb.0:1004; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1005; CHECK-NEXT: addvl sp, sp, #-11006; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill1007; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG1008; CHECK-NEXT: .cfi_offset w29, -161009; CHECK-NEXT: punpklo p2.h, p0.b1010; CHECK-NEXT: punpkhi p0.h, p0.b1011; CHECK-NEXT: punpkhi p3.h, p2.b1012; CHECK-NEXT: punpklo p2.h, p2.b1013; CHECK-NEXT: punpklo p4.h, p3.b1014; CHECK-NEXT: punpkhi p3.h, p3.b1015; CHECK-NEXT: punpkhi p4.h, p4.b1016; CHECK-NEXT: uzp1 p1.d, p1.d, p4.d1017; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload1018; CHECK-NEXT: uzp1 p1.s, p1.s, p3.s1019; CHECK-NEXT: uzp1 p1.h, p2.h, p1.h1020; CHECK-NEXT: uzp1 p0.b, p1.b, p0.b1021; CHECK-NEXT: addvl sp, sp, #11022; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1023; CHECK-NEXT: ret1024 %res = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv1i1(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv, i64 4)1025 ret <vscale x 16 x i1> %res1026}1027 1028define <vscale x 16 x i1> @insert_nxv1i1_nxv16i1_5(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv) {1029; CHECK-LABEL: insert_nxv1i1_nxv16i1_5:1030; CHECK: // %bb.0:1031; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1032; CHECK-NEXT: addvl sp, sp, #-11033; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill1034; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG1035; CHECK-NEXT: .cfi_offset w29, -161036; CHECK-NEXT: punpklo p2.h, p0.b1037; CHECK-NEXT: punpkhi p0.h, p0.b1038; CHECK-NEXT: punpkhi p3.h, p2.b1039; CHECK-NEXT: punpklo p2.h, p2.b1040; CHECK-NEXT: punpklo p4.h, p3.b1041; CHECK-NEXT: punpkhi p3.h, p3.b1042; CHECK-NEXT: punpklo p4.h, p4.b1043; CHECK-NEXT: uzp1 p1.d, p4.d, p1.d1044; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload1045; CHECK-NEXT: uzp1 p1.s, p1.s, p3.s1046; CHECK-NEXT: uzp1 p1.h, p2.h, p1.h1047; CHECK-NEXT: uzp1 p0.b, p1.b, p0.b1048; CHECK-NEXT: addvl sp, sp, #11049; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1050; CHECK-NEXT: ret1051 %res = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv1i1(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv, i64 5)1052 ret <vscale x 16 x i1> %res1053}1054 1055define <vscale x 16 x i1> @insert_nxv1i1_nxv16i1_6(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv) {1056; CHECK-LABEL: insert_nxv1i1_nxv16i1_6:1057; CHECK: // %bb.0:1058; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1059; CHECK-NEXT: addvl sp, sp, #-11060; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill1061; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG1062; CHECK-NEXT: .cfi_offset w29, -161063; CHECK-NEXT: punpklo p2.h, p0.b1064; CHECK-NEXT: punpkhi p0.h, p0.b1065; CHECK-NEXT: punpkhi p3.h, p2.b1066; CHECK-NEXT: punpklo p2.h, p2.b1067; CHECK-NEXT: punpkhi p4.h, p3.b1068; CHECK-NEXT: punpklo p3.h, p3.b1069; CHECK-NEXT: punpkhi p4.h, p4.b1070; CHECK-NEXT: uzp1 p1.d, p1.d, p4.d1071; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload1072; CHECK-NEXT: uzp1 p1.s, p3.s, p1.s1073; CHECK-NEXT: uzp1 p1.h, p2.h, p1.h1074; CHECK-NEXT: uzp1 p0.b, p1.b, p0.b1075; CHECK-NEXT: addvl sp, sp, #11076; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1077; CHECK-NEXT: ret1078 %res = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv1i1(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv, i64 6)1079 ret <vscale x 16 x i1> %res1080}1081 1082define <vscale x 16 x i1> @insert_nxv1i1_nxv16i1_7(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv) {1083; CHECK-LABEL: insert_nxv1i1_nxv16i1_7:1084; CHECK: // %bb.0:1085; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1086; CHECK-NEXT: addvl sp, sp, #-11087; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill1088; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG1089; CHECK-NEXT: .cfi_offset w29, -161090; CHECK-NEXT: punpklo p2.h, p0.b1091; CHECK-NEXT: punpkhi p0.h, p0.b1092; CHECK-NEXT: punpkhi p3.h, p2.b1093; CHECK-NEXT: punpklo p2.h, p2.b1094; CHECK-NEXT: punpkhi p4.h, p3.b1095; CHECK-NEXT: punpklo p3.h, p3.b1096; CHECK-NEXT: punpklo p4.h, p4.b1097; CHECK-NEXT: uzp1 p1.d, p4.d, p1.d1098; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload1099; CHECK-NEXT: uzp1 p1.s, p3.s, p1.s1100; CHECK-NEXT: uzp1 p1.h, p2.h, p1.h1101; CHECK-NEXT: uzp1 p0.b, p1.b, p0.b1102; CHECK-NEXT: addvl sp, sp, #11103; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1104; CHECK-NEXT: ret1105 %res = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv1i1(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv, i64 7)1106 ret <vscale x 16 x i1> %res1107}1108 1109define <vscale x 16 x i1> @insert_nxv1i1_nxv16i1_8(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv) {1110; CHECK-LABEL: insert_nxv1i1_nxv16i1_8:1111; CHECK: // %bb.0:1112; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1113; CHECK-NEXT: addvl sp, sp, #-11114; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill1115; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG1116; CHECK-NEXT: .cfi_offset w29, -161117; CHECK-NEXT: punpkhi p2.h, p0.b1118; CHECK-NEXT: punpklo p0.h, p0.b1119; CHECK-NEXT: punpklo p3.h, p2.b1120; CHECK-NEXT: punpkhi p2.h, p2.b1121; CHECK-NEXT: punpklo p4.h, p3.b1122; CHECK-NEXT: punpkhi p3.h, p3.b1123; CHECK-NEXT: punpkhi p4.h, p4.b1124; CHECK-NEXT: uzp1 p1.d, p1.d, p4.d1125; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload1126; CHECK-NEXT: uzp1 p1.s, p1.s, p3.s1127; CHECK-NEXT: uzp1 p1.h, p1.h, p2.h1128; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b1129; CHECK-NEXT: addvl sp, sp, #11130; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1131; CHECK-NEXT: ret1132 %res = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv1i1(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv, i64 8)1133 ret <vscale x 16 x i1> %res1134}1135 1136define <vscale x 16 x i1> @insert_nxv1i1_nxv16i1_9(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv) {1137; CHECK-LABEL: insert_nxv1i1_nxv16i1_9:1138; CHECK: // %bb.0:1139; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1140; CHECK-NEXT: addvl sp, sp, #-11141; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill1142; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG1143; CHECK-NEXT: .cfi_offset w29, -161144; CHECK-NEXT: punpkhi p2.h, p0.b1145; CHECK-NEXT: punpklo p0.h, p0.b1146; CHECK-NEXT: punpklo p3.h, p2.b1147; CHECK-NEXT: punpkhi p2.h, p2.b1148; CHECK-NEXT: punpklo p4.h, p3.b1149; CHECK-NEXT: punpkhi p3.h, p3.b1150; CHECK-NEXT: punpklo p4.h, p4.b1151; CHECK-NEXT: uzp1 p1.d, p4.d, p1.d1152; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload1153; CHECK-NEXT: uzp1 p1.s, p1.s, p3.s1154; CHECK-NEXT: uzp1 p1.h, p1.h, p2.h1155; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b1156; CHECK-NEXT: addvl sp, sp, #11157; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1158; CHECK-NEXT: ret1159 %res = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv1i1(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv, i64 9)1160 ret <vscale x 16 x i1> %res1161}1162 1163define <vscale x 16 x i1> @insert_nxv1i1_nxv16i1_10(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv) {1164; CHECK-LABEL: insert_nxv1i1_nxv16i1_10:1165; CHECK: // %bb.0:1166; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1167; CHECK-NEXT: addvl sp, sp, #-11168; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill1169; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG1170; CHECK-NEXT: .cfi_offset w29, -161171; CHECK-NEXT: punpkhi p2.h, p0.b1172; CHECK-NEXT: punpklo p0.h, p0.b1173; CHECK-NEXT: punpklo p3.h, p2.b1174; CHECK-NEXT: punpkhi p2.h, p2.b1175; CHECK-NEXT: punpkhi p4.h, p3.b1176; CHECK-NEXT: punpklo p3.h, p3.b1177; CHECK-NEXT: punpkhi p4.h, p4.b1178; CHECK-NEXT: uzp1 p1.d, p1.d, p4.d1179; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload1180; CHECK-NEXT: uzp1 p1.s, p3.s, p1.s1181; CHECK-NEXT: uzp1 p1.h, p1.h, p2.h1182; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b1183; CHECK-NEXT: addvl sp, sp, #11184; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1185; CHECK-NEXT: ret1186 %res = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv1i1(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv, i64 10)1187 ret <vscale x 16 x i1> %res1188}1189 1190define <vscale x 16 x i1> @insert_nxv1i1_nxv16i1_11(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv) {1191; CHECK-LABEL: insert_nxv1i1_nxv16i1_11:1192; CHECK: // %bb.0:1193; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1194; CHECK-NEXT: addvl sp, sp, #-11195; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill1196; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG1197; CHECK-NEXT: .cfi_offset w29, -161198; CHECK-NEXT: punpkhi p2.h, p0.b1199; CHECK-NEXT: punpklo p0.h, p0.b1200; CHECK-NEXT: punpklo p3.h, p2.b1201; CHECK-NEXT: punpkhi p2.h, p2.b1202; CHECK-NEXT: punpkhi p4.h, p3.b1203; CHECK-NEXT: punpklo p3.h, p3.b1204; CHECK-NEXT: punpklo p4.h, p4.b1205; CHECK-NEXT: uzp1 p1.d, p4.d, p1.d1206; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload1207; CHECK-NEXT: uzp1 p1.s, p3.s, p1.s1208; CHECK-NEXT: uzp1 p1.h, p1.h, p2.h1209; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b1210; CHECK-NEXT: addvl sp, sp, #11211; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1212; CHECK-NEXT: ret1213 %res = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv1i1(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv, i64 11)1214 ret <vscale x 16 x i1> %res1215}1216 1217define <vscale x 16 x i1> @insert_nxv1i1_nxv16i1_12(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv) {1218; CHECK-LABEL: insert_nxv1i1_nxv16i1_12:1219; CHECK: // %bb.0:1220; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1221; CHECK-NEXT: addvl sp, sp, #-11222; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill1223; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG1224; CHECK-NEXT: .cfi_offset w29, -161225; CHECK-NEXT: punpkhi p2.h, p0.b1226; CHECK-NEXT: punpklo p0.h, p0.b1227; CHECK-NEXT: punpkhi p3.h, p2.b1228; CHECK-NEXT: punpklo p2.h, p2.b1229; CHECK-NEXT: punpklo p4.h, p3.b1230; CHECK-NEXT: punpkhi p3.h, p3.b1231; CHECK-NEXT: punpkhi p4.h, p4.b1232; CHECK-NEXT: uzp1 p1.d, p1.d, p4.d1233; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload1234; CHECK-NEXT: uzp1 p1.s, p1.s, p3.s1235; CHECK-NEXT: uzp1 p1.h, p2.h, p1.h1236; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b1237; CHECK-NEXT: addvl sp, sp, #11238; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1239; CHECK-NEXT: ret1240 %res = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv1i1(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv, i64 12)1241 ret <vscale x 16 x i1> %res1242}1243 1244define <vscale x 16 x i1> @insert_nxv1i1_nxv16i1_13(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv) {1245; CHECK-LABEL: insert_nxv1i1_nxv16i1_13:1246; CHECK: // %bb.0:1247; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1248; CHECK-NEXT: addvl sp, sp, #-11249; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill1250; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG1251; CHECK-NEXT: .cfi_offset w29, -161252; CHECK-NEXT: punpkhi p2.h, p0.b1253; CHECK-NEXT: punpklo p0.h, p0.b1254; CHECK-NEXT: punpkhi p3.h, p2.b1255; CHECK-NEXT: punpklo p2.h, p2.b1256; CHECK-NEXT: punpklo p4.h, p3.b1257; CHECK-NEXT: punpkhi p3.h, p3.b1258; CHECK-NEXT: punpklo p4.h, p4.b1259; CHECK-NEXT: uzp1 p1.d, p4.d, p1.d1260; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload1261; CHECK-NEXT: uzp1 p1.s, p1.s, p3.s1262; CHECK-NEXT: uzp1 p1.h, p2.h, p1.h1263; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b1264; CHECK-NEXT: addvl sp, sp, #11265; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1266; CHECK-NEXT: ret1267 %res = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv1i1(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv, i64 13)1268 ret <vscale x 16 x i1> %res1269}1270 1271define <vscale x 16 x i1> @insert_nxv1i1_nxv16i1_14(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv) {1272; CHECK-LABEL: insert_nxv1i1_nxv16i1_14:1273; CHECK: // %bb.0:1274; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1275; CHECK-NEXT: addvl sp, sp, #-11276; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill1277; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG1278; CHECK-NEXT: .cfi_offset w29, -161279; CHECK-NEXT: punpkhi p2.h, p0.b1280; CHECK-NEXT: punpklo p0.h, p0.b1281; CHECK-NEXT: punpkhi p3.h, p2.b1282; CHECK-NEXT: punpklo p2.h, p2.b1283; CHECK-NEXT: punpkhi p4.h, p3.b1284; CHECK-NEXT: punpklo p3.h, p3.b1285; CHECK-NEXT: punpkhi p4.h, p4.b1286; CHECK-NEXT: uzp1 p1.d, p1.d, p4.d1287; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload1288; CHECK-NEXT: uzp1 p1.s, p3.s, p1.s1289; CHECK-NEXT: uzp1 p1.h, p2.h, p1.h1290; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b1291; CHECK-NEXT: addvl sp, sp, #11292; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1293; CHECK-NEXT: ret1294 %res = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv1i1(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv, i64 14)1295 ret <vscale x 16 x i1> %res1296}1297 1298define <vscale x 16 x i1> @insert_nxv1i1_nxv16i1_15(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv) {1299; CHECK-LABEL: insert_nxv1i1_nxv16i1_15:1300; CHECK: // %bb.0:1301; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1302; CHECK-NEXT: addvl sp, sp, #-11303; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill1304; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG1305; CHECK-NEXT: .cfi_offset w29, -161306; CHECK-NEXT: punpkhi p2.h, p0.b1307; CHECK-NEXT: punpklo p0.h, p0.b1308; CHECK-NEXT: punpkhi p3.h, p2.b1309; CHECK-NEXT: punpklo p2.h, p2.b1310; CHECK-NEXT: punpkhi p4.h, p3.b1311; CHECK-NEXT: punpklo p3.h, p3.b1312; CHECK-NEXT: punpklo p4.h, p4.b1313; CHECK-NEXT: uzp1 p1.d, p4.d, p1.d1314; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload1315; CHECK-NEXT: uzp1 p1.s, p3.s, p1.s1316; CHECK-NEXT: uzp1 p1.h, p2.h, p1.h1317; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b1318; CHECK-NEXT: addvl sp, sp, #11319; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1320; CHECK-NEXT: ret1321 %res = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv1i1(<vscale x 16 x i1> %vec, <vscale x 1 x i1> %sv, i64 15)1322 ret <vscale x 16 x i1> %res1323}1324 1325; NOTE: Extract input sub-vector from a legal type to avoid relying on an1326; undefined calling convention.1327define <vscale x 4 x i32> @insert_nxv1i32_nxv4i32_0(<vscale x 4 x i32> %vec, <vscale x 4 x i32> %subvec) nounwind {1328; CHECK-LABEL: insert_nxv1i32_nxv4i32_0:1329; CHECK: // %bb.0:1330; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1331; CHECK-NEXT: addvl sp, sp, #-11332; CHECK-NEXT: rdvl x8, #11333; CHECK-NEXT: str z0, [sp]1334; CHECK-NEXT: lsr x8, x8, #41335; CHECK-NEXT: whilelo p0.s, xzr, x81336; CHECK-NEXT: st1w { z1.s }, p0, [sp]1337; CHECK-NEXT: ldr z0, [sp]1338; CHECK-NEXT: addvl sp, sp, #11339; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1340; CHECK-NEXT: ret1341 %i = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32> %subvec, i64 0)1342 %retval = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> %vec, <vscale x 1 x i32> %i, i64 0)1343 ret <vscale x 4 x i32> %retval1344}1345 1346; NOTE: Extract input sub-vector from a legal type to avoid relying on an1347; undefined calling convention.1348define <vscale x 4 x i32> @insert_nxv1i32_nxv4i32_1(<vscale x 4 x i32> %vec, <vscale x 4 x i32> %subvec) nounwind {1349; CHECK-LABEL: insert_nxv1i32_nxv4i32_1:1350; CHECK: // %bb.0:1351; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1352; CHECK-NEXT: addvl sp, sp, #-11353; CHECK-NEXT: rdvl x8, #11354; CHECK-NEXT: mov x9, sp1355; CHECK-NEXT: str z0, [sp]1356; CHECK-NEXT: lsr x8, x8, #41357; CHECK-NEXT: whilelo p0.s, xzr, x81358; CHECK-NEXT: cntw x81359; CHECK-NEXT: add x8, x9, x81360; CHECK-NEXT: st1w { z1.s }, p0, [x8]1361; CHECK-NEXT: ldr z0, [sp]1362; CHECK-NEXT: addvl sp, sp, #11363; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1364; CHECK-NEXT: ret1365 %i = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32> %subvec, i64 0)1366 %retval = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> %vec, <vscale x 1 x i32> %i, i64 1)1367 ret <vscale x 4 x i32> %retval1368}1369 1370; NOTE: Extract input sub-vector from a legal type to avoid relying on an1371; undefined calling convention.1372define <vscale x 4 x i32> @insert_nxv1i32_nxv4i32_2(<vscale x 4 x i32> %vec, <vscale x 4 x i32> %subvec) nounwind {1373; CHECK-LABEL: insert_nxv1i32_nxv4i32_2:1374; CHECK: // %bb.0:1375; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1376; CHECK-NEXT: addvl sp, sp, #-11377; CHECK-NEXT: rdvl x8, #11378; CHECK-NEXT: mov x9, sp1379; CHECK-NEXT: str z0, [sp]1380; CHECK-NEXT: lsr x8, x8, #41381; CHECK-NEXT: whilelo p0.s, xzr, x81382; CHECK-NEXT: cnth x81383; CHECK-NEXT: add x8, x9, x81384; CHECK-NEXT: st1w { z1.s }, p0, [x8]1385; CHECK-NEXT: ldr z0, [sp]1386; CHECK-NEXT: addvl sp, sp, #11387; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1388; CHECK-NEXT: ret1389 %i = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32> %subvec, i64 0)1390 %retval = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> %vec, <vscale x 1 x i32> %i, i64 2)1391 ret <vscale x 4 x i32> %retval1392}1393 1394; NOTE: Extract input sub-vector from a legal type to avoid relying on an1395; undefined calling convention.1396define <vscale x 4 x i32> @insert_nxv1i32_nxv4i32_3(<vscale x 4 x i32> %vec, <vscale x 4 x i32> %subvec) nounwind {1397; CHECK-LABEL: insert_nxv1i32_nxv4i32_3:1398; CHECK: // %bb.0:1399; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1400; CHECK-NEXT: addvl sp, sp, #-11401; CHECK-NEXT: rdvl x8, #11402; CHECK-NEXT: mov x9, sp1403; CHECK-NEXT: str z0, [sp]1404; CHECK-NEXT: lsr x8, x8, #41405; CHECK-NEXT: whilelo p0.s, xzr, x81406; CHECK-NEXT: cntw x8, all, mul #31407; CHECK-NEXT: add x8, x9, x81408; CHECK-NEXT: st1w { z1.s }, p0, [x8]1409; CHECK-NEXT: ldr z0, [sp]1410; CHECK-NEXT: addvl sp, sp, #11411; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1412; CHECK-NEXT: ret1413 %i = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32> %subvec, i64 0)1414 %retval = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> %vec, <vscale x 1 x i32> %i, i64 3)1415 ret <vscale x 4 x i32> %retval1416}1417 1418; NOTE: Extract input sub-vector from a legal type to avoid relying on an1419; undefined calling convention.1420define <vscale x 2 x float> @insert_nxv1f32_nxv2f32_0(<vscale x 2 x float> %vec, <vscale x 2 x float> %subvec) nounwind {1421; CHECK-LABEL: insert_nxv1f32_nxv2f32_0:1422; CHECK: // %bb.0:1423; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1424; CHECK-NEXT: addvl sp, sp, #-11425; CHECK-NEXT: rdvl x8, #11426; CHECK-NEXT: ptrue p0.d1427; CHECK-NEXT: lsr x8, x8, #41428; CHECK-NEXT: st1w { z0.d }, p0, [sp, #1, mul vl]1429; CHECK-NEXT: whilelo p1.d, xzr, x81430; CHECK-NEXT: st1w { z1.d }, p1, [sp, #1, mul vl]1431; CHECK-NEXT: ld1w { z0.d }, p0/z, [sp, #1, mul vl]1432; CHECK-NEXT: addvl sp, sp, #11433; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1434; CHECK-NEXT: ret1435 %i = call <vscale x 1 x float> @llvm.vector.extract.nxv1f32.nxv2f32(<vscale x 2 x float> %subvec, i64 0)1436 %retval = call <vscale x 2 x float> @llvm.vector.insert.nxv2f32.nxv1f32(<vscale x 2 x float> %vec, <vscale x 1 x float> %i, i64 0)1437 ret <vscale x 2 x float> %retval1438}1439 1440; NOTE: Extract input sub-vector from a legal type to avoid relying on an1441; undefined calling convention.1442define <vscale x 2 x float> @insert_nxv1f32_nxv2f32_1(<vscale x 2 x float> %vec, <vscale x 2 x float> %subvec) nounwind {1443; CHECK-LABEL: insert_nxv1f32_nxv2f32_1:1444; CHECK: // %bb.0:1445; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1446; CHECK-NEXT: addvl sp, sp, #-11447; CHECK-NEXT: rdvl x8, #11448; CHECK-NEXT: ptrue p0.d1449; CHECK-NEXT: addpl x9, sp, #41450; CHECK-NEXT: lsr x8, x8, #41451; CHECK-NEXT: st1w { z0.d }, p0, [sp, #1, mul vl]1452; CHECK-NEXT: whilelo p1.d, xzr, x81453; CHECK-NEXT: cntw x81454; CHECK-NEXT: add x8, x9, x81455; CHECK-NEXT: st1w { z1.d }, p1, [x8]1456; CHECK-NEXT: ld1w { z0.d }, p0/z, [sp, #1, mul vl]1457; CHECK-NEXT: addvl sp, sp, #11458; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1459; CHECK-NEXT: ret1460 %i = call <vscale x 1 x float> @llvm.vector.extract.nxv1f32.nxv2f32(<vscale x 2 x float> %subvec, i64 0)1461 %retval = call <vscale x 2 x float> @llvm.vector.insert.nxv2f32.nxv1f32(<vscale x 2 x float> %vec, <vscale x 1 x float> %i, i64 1)1462 ret <vscale x 2 x float> %retval1463}1464 1465; NOTE: Extract input sub-vector from a legal type to avoid relying on an1466; undefined calling convention.1467define <vscale x 4 x float> @insert_nxv1f32_nxv4f32_0(<vscale x 4 x float> %vec, <vscale x 4 x float> %subvec) nounwind {1468; CHECK-LABEL: insert_nxv1f32_nxv4f32_0:1469; CHECK: // %bb.0:1470; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1471; CHECK-NEXT: addvl sp, sp, #-11472; CHECK-NEXT: rdvl x8, #11473; CHECK-NEXT: uunpklo z1.d, z1.s1474; CHECK-NEXT: str z0, [sp]1475; CHECK-NEXT: lsr x8, x8, #41476; CHECK-NEXT: whilelo p0.d, xzr, x81477; CHECK-NEXT: st1w { z1.d }, p0, [sp]1478; CHECK-NEXT: ldr z0, [sp]1479; CHECK-NEXT: addvl sp, sp, #11480; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1481; CHECK-NEXT: ret1482 %i = call <vscale x 1 x float> @llvm.vector.extract.nxv1f32.nxv4f32(<vscale x 4 x float> %subvec, i64 0)1483 %retval = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv1f32(<vscale x 4 x float> %vec, <vscale x 1 x float> %i, i64 0)1484 ret <vscale x 4 x float> %retval1485}1486 1487; NOTE: Extract input sub-vector from a legal type to avoid relying on an1488; undefined calling convention.1489define <vscale x 4 x float> @insert_nxv1f32_nxv4f32_1(<vscale x 4 x float> %vec, <vscale x 4 x float> %subvec) nounwind {1490; CHECK-LABEL: insert_nxv1f32_nxv4f32_1:1491; CHECK: // %bb.0:1492; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1493; CHECK-NEXT: addvl sp, sp, #-11494; CHECK-NEXT: rdvl x8, #11495; CHECK-NEXT: uunpklo z1.d, z1.s1496; CHECK-NEXT: mov x9, sp1497; CHECK-NEXT: lsr x8, x8, #41498; CHECK-NEXT: str z0, [sp]1499; CHECK-NEXT: whilelo p0.d, xzr, x81500; CHECK-NEXT: cntw x81501; CHECK-NEXT: add x8, x9, x81502; CHECK-NEXT: st1w { z1.d }, p0, [x8]1503; CHECK-NEXT: ldr z0, [sp]1504; CHECK-NEXT: addvl sp, sp, #11505; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1506; CHECK-NEXT: ret1507 %i = call <vscale x 1 x float> @llvm.vector.extract.nxv1f32.nxv4f32(<vscale x 4 x float> %subvec, i64 0)1508 %retval = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv1f32(<vscale x 4 x float> %vec, <vscale x 1 x float> %i, i64 1)1509 ret <vscale x 4 x float> %retval1510}1511 1512; NOTE: Extract input sub-vector from a legal type to avoid relying on an1513; undefined calling convention.1514define <vscale x 4 x float> @insert_nxv1f32_nxv4f32_2(<vscale x 4 x float> %vec, <vscale x 4 x float> %subvec) nounwind {1515; CHECK-LABEL: insert_nxv1f32_nxv4f32_2:1516; CHECK: // %bb.0:1517; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1518; CHECK-NEXT: addvl sp, sp, #-11519; CHECK-NEXT: rdvl x8, #11520; CHECK-NEXT: uunpklo z1.d, z1.s1521; CHECK-NEXT: str z0, [sp]1522; CHECK-NEXT: lsr x8, x8, #41523; CHECK-NEXT: whilelo p0.d, xzr, x81524; CHECK-NEXT: st1w { z1.d }, p0, [sp, #1, mul vl]1525; CHECK-NEXT: ldr z0, [sp]1526; CHECK-NEXT: addvl sp, sp, #11527; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1528; CHECK-NEXT: ret1529 %i = call <vscale x 1 x float> @llvm.vector.extract.nxv1f32.nxv4f32(<vscale x 4 x float> %subvec, i64 0)1530 %retval = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv1f32(<vscale x 4 x float> %vec, <vscale x 1 x float> %i, i64 2)1531 ret <vscale x 4 x float> %retval1532}1533 1534; NOTE: Extract input sub-vector from a legal type to avoid relying on an1535; undefined calling convention.1536define <vscale x 4 x float> @insert_nxv1f32_nxv4f32_3(<vscale x 4 x float> %vec, <vscale x 4 x float> %subvec) nounwind {1537; CHECK-LABEL: insert_nxv1f32_nxv4f32_3:1538; CHECK: // %bb.0:1539; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1540; CHECK-NEXT: addvl sp, sp, #-11541; CHECK-NEXT: rdvl x8, #11542; CHECK-NEXT: uunpklo z1.d, z1.s1543; CHECK-NEXT: mov x9, sp1544; CHECK-NEXT: lsr x8, x8, #41545; CHECK-NEXT: str z0, [sp]1546; CHECK-NEXT: whilelo p0.d, xzr, x81547; CHECK-NEXT: cntw x8, all, mul #31548; CHECK-NEXT: add x8, x9, x81549; CHECK-NEXT: st1w { z1.d }, p0, [x8]1550; CHECK-NEXT: ldr z0, [sp]1551; CHECK-NEXT: addvl sp, sp, #11552; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1553; CHECK-NEXT: ret1554 %i = call <vscale x 1 x float> @llvm.vector.extract.nxv1f32.nxv4f32(<vscale x 4 x float> %subvec, i64 0)1555 %retval = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv1f32(<vscale x 4 x float> %vec, <vscale x 1 x float> %i, i64 3)1556 ret <vscale x 4 x float> %retval1557}1558 1559attributes #0 = { vscale_range(2,2) }1560