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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4;5; SMAX6;7define <vscale x 16 x i8> @smax_i8_pos(<vscale x 16 x i8> %a) {8; CHECK-LABEL: smax_i8_pos:9; CHECK: // %bb.0:10; CHECK-NEXT: smax z0.b, z0.b, #2711; CHECK-NEXT: ret12 %cmp = icmp sgt <vscale x 16 x i8> %a, splat(i8 27)13 %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 27)14 ret <vscale x 16 x i8> %res15}16 17define <vscale x 16 x i8> @smax_i8_neg(<vscale x 16 x i8> %a) {18; CHECK-LABEL: smax_i8_neg:19; CHECK: // %bb.0:20; CHECK-NEXT: smax z0.b, z0.b, #-5821; CHECK-NEXT: ret22 %cmp = icmp sgt <vscale x 16 x i8> %a, splat(i8 -58)23 %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 -58)24 ret <vscale x 16 x i8> %res25}26 27define <vscale x 8 x i16> @smax_i16_pos(<vscale x 8 x i16> %a) {28; CHECK-LABEL: smax_i16_pos:29; CHECK: // %bb.0:30; CHECK-NEXT: smax z0.h, z0.h, #2731; CHECK-NEXT: ret32 %cmp = icmp sgt <vscale x 8 x i16> %a, splat(i16 27)33 %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 27)34 ret <vscale x 8 x i16> %res35}36 37define <vscale x 8 x i16> @smax_i16_neg(<vscale x 8 x i16> %a) {38; CHECK-LABEL: smax_i16_neg:39; CHECK: // %bb.0:40; CHECK-NEXT: smax z0.h, z0.h, #-5841; CHECK-NEXT: ret42 %cmp = icmp sgt <vscale x 8 x i16> %a, splat(i16 -58)43 %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 -58)44 ret <vscale x 8 x i16> %res45}46 47define <vscale x 8 x i16> @smax_i16_out_of_range(<vscale x 8 x i16> %a) {48; CHECK-LABEL: smax_i16_out_of_range:49; CHECK: // %bb.0:50; CHECK-NEXT: dupm z1.b, #0x151; CHECK-NEXT: ptrue p0.h52; CHECK-NEXT: smax z0.h, p0/m, z0.h, z1.h53; CHECK-NEXT: ret54 %cmp = icmp sgt <vscale x 8 x i16> %a, splat(i16 257)55 %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 257)56 ret <vscale x 8 x i16> %res57}58 59define <vscale x 4 x i32> @smax_i32_pos(<vscale x 4 x i32> %a) {60; CHECK-LABEL: smax_i32_pos:61; CHECK: // %bb.0:62; CHECK-NEXT: smax z0.s, z0.s, #2763; CHECK-NEXT: ret64 %cmp = icmp sgt <vscale x 4 x i32> %a, splat(i32 27)65 %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 27)66 ret <vscale x 4 x i32> %res67}68 69define <vscale x 4 x i32> @smax_i32_neg(<vscale x 4 x i32> %a) {70; CHECK-LABEL: smax_i32_neg:71; CHECK: // %bb.0:72; CHECK-NEXT: smax z0.s, z0.s, #-5873; CHECK-NEXT: ret74 %cmp = icmp sgt <vscale x 4 x i32> %a, splat(i32 -58)75 %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 -58)76 ret <vscale x 4 x i32> %res77}78 79define <vscale x 4 x i32> @smax_i32_out_of_range(<vscale x 4 x i32> %a) {80; CHECK-LABEL: smax_i32_out_of_range:81; CHECK: // %bb.0:82; CHECK-NEXT: mov z1.s, #-129 // =0xffffffffffffff7f83; CHECK-NEXT: ptrue p0.s84; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s85; CHECK-NEXT: ret86 %cmp = icmp sgt <vscale x 4 x i32> %a, splat(i32 -129)87 %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 -129)88 ret <vscale x 4 x i32> %res89}90 91define <vscale x 2 x i64> @smax_i64_pos(<vscale x 2 x i64> %a) {92; CHECK-LABEL: smax_i64_pos:93; CHECK: // %bb.0:94; CHECK-NEXT: smax z0.d, z0.d, #2795; CHECK-NEXT: ret96 %cmp = icmp sgt <vscale x 2 x i64> %a, splat(i64 27)97 %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 27)98 ret <vscale x 2 x i64> %res99}100 101define <vscale x 2 x i64> @smax_i64_neg(<vscale x 2 x i64> %a) {102; CHECK-LABEL: smax_i64_neg:103; CHECK: // %bb.0:104; CHECK-NEXT: smax z0.d, z0.d, #-58105; CHECK-NEXT: ret106 %cmp = icmp sgt <vscale x 2 x i64> %a, splat(i64 -58)107 %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 -58)108 ret <vscale x 2 x i64> %res109}110 111define <vscale x 2 x i64> @smax_i64_out_of_range(<vscale x 2 x i64> %a) {112; CHECK-LABEL: smax_i64_out_of_range:113; CHECK: // %bb.0:114; CHECK-NEXT: mov z1.d, #65535 // =0xffff115; CHECK-NEXT: ptrue p0.d116; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d117; CHECK-NEXT: ret118 %cmp = icmp sgt <vscale x 2 x i64> %a, splat(i64 65535)119 %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 65535)120 ret <vscale x 2 x i64> %res121}122 123;124; SMIN125;126define <vscale x 16 x i8> @smin_i8_pos(<vscale x 16 x i8> %a) {127; CHECK-LABEL: smin_i8_pos:128; CHECK: // %bb.0:129; CHECK-NEXT: smin z0.b, z0.b, #27130; CHECK-NEXT: ret131 %cmp = icmp slt <vscale x 16 x i8> %a, splat(i8 27)132 %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 27)133 ret <vscale x 16 x i8> %res134}135 136define <vscale x 16 x i8> @smin_i8_neg(<vscale x 16 x i8> %a) {137; CHECK-LABEL: smin_i8_neg:138; CHECK: // %bb.0:139; CHECK-NEXT: smin z0.b, z0.b, #-58140; CHECK-NEXT: ret141 %cmp = icmp slt <vscale x 16 x i8> %a, splat(i8 -58)142 %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 -58)143 ret <vscale x 16 x i8> %res144}145 146define <vscale x 8 x i16> @smin_i16_pos(<vscale x 8 x i16> %a) {147; CHECK-LABEL: smin_i16_pos:148; CHECK: // %bb.0:149; CHECK-NEXT: smin z0.h, z0.h, #27150; CHECK-NEXT: ret151 %cmp = icmp slt <vscale x 8 x i16> %a, splat(i16 27)152 %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 27)153 ret <vscale x 8 x i16> %res154}155 156define <vscale x 8 x i16> @smin_i16_neg(<vscale x 8 x i16> %a) {157; CHECK-LABEL: smin_i16_neg:158; CHECK: // %bb.0:159; CHECK-NEXT: smin z0.h, z0.h, #-58160; CHECK-NEXT: ret161 %cmp = icmp slt <vscale x 8 x i16> %a, splat(i16 -58)162 %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 -58)163 ret <vscale x 8 x i16> %res164}165 166define <vscale x 8 x i16> @smin_i16_out_of_range(<vscale x 8 x i16> %a) {167; CHECK-LABEL: smin_i16_out_of_range:168; CHECK: // %bb.0:169; CHECK-NEXT: dupm z1.b, #0x1170; CHECK-NEXT: ptrue p0.h171; CHECK-NEXT: smin z0.h, p0/m, z0.h, z1.h172; CHECK-NEXT: ret173 %cmp = icmp slt <vscale x 8 x i16> %a, splat(i16 257)174 %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 257)175 ret <vscale x 8 x i16> %res176}177 178define <vscale x 4 x i32> @smin_i32_pos(<vscale x 4 x i32> %a) {179; CHECK-LABEL: smin_i32_pos:180; CHECK: // %bb.0:181; CHECK-NEXT: smin z0.s, z0.s, #27182; CHECK-NEXT: ret183 %cmp = icmp slt <vscale x 4 x i32> %a, splat(i32 27)184 %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 27)185 ret <vscale x 4 x i32> %res186}187 188define <vscale x 4 x i32> @smin_i32_neg(<vscale x 4 x i32> %a) {189; CHECK-LABEL: smin_i32_neg:190; CHECK: // %bb.0:191; CHECK-NEXT: smin z0.s, z0.s, #-58192; CHECK-NEXT: ret193 %cmp = icmp slt <vscale x 4 x i32> %a, splat(i32 -58)194 %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 -58)195 ret <vscale x 4 x i32> %res196}197 198define <vscale x 4 x i32> @smin_i32_out_of_range(<vscale x 4 x i32> %a) {199; CHECK-LABEL: smin_i32_out_of_range:200; CHECK: // %bb.0:201; CHECK-NEXT: mov z1.s, #-129 // =0xffffffffffffff7f202; CHECK-NEXT: ptrue p0.s203; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s204; CHECK-NEXT: ret205 %cmp = icmp slt <vscale x 4 x i32> %a, splat(i32 -129)206 %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 -129)207 ret <vscale x 4 x i32> %res208}209 210define <vscale x 2 x i64> @smin_i64_pos(<vscale x 2 x i64> %a) {211; CHECK-LABEL: smin_i64_pos:212; CHECK: // %bb.0:213; CHECK-NEXT: smin z0.d, z0.d, #27214; CHECK-NEXT: ret215 %cmp = icmp slt <vscale x 2 x i64> %a, splat(i64 27)216 %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 27)217 ret <vscale x 2 x i64> %res218}219 220define <vscale x 2 x i64> @smin_i64_neg(<vscale x 2 x i64> %a) {221; CHECK-LABEL: smin_i64_neg:222; CHECK: // %bb.0:223; CHECK-NEXT: smin z0.d, z0.d, #-58224; CHECK-NEXT: ret225 %cmp = icmp slt <vscale x 2 x i64> %a, splat(i64 -58)226 %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 -58)227 ret <vscale x 2 x i64> %res228}229 230define <vscale x 2 x i64> @smin_i64_out_of_range(<vscale x 2 x i64> %a) {231; CHECK-LABEL: smin_i64_out_of_range:232; CHECK: // %bb.0:233; CHECK-NEXT: mov z1.d, #65535 // =0xffff234; CHECK-NEXT: ptrue p0.d235; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d236; CHECK-NEXT: ret237 %cmp = icmp slt <vscale x 2 x i64> %a, splat(i64 65535)238 %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 65535)239 ret <vscale x 2 x i64> %res240}241 242;243; UMAX244;245define <vscale x 16 x i8> @umax_i8_pos(<vscale x 16 x i8> %a) {246; CHECK-LABEL: umax_i8_pos:247; CHECK: // %bb.0:248; CHECK-NEXT: umax z0.b, z0.b, #27249; CHECK-NEXT: ret250 %cmp = icmp ugt <vscale x 16 x i8> %a, splat(i8 27)251 %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 27)252 ret <vscale x 16 x i8> %res253}254 255define <vscale x 16 x i8> @umax_i8_large(<vscale x 16 x i8> %a) {256; CHECK-LABEL: umax_i8_large:257; CHECK: // %bb.0:258; CHECK-NEXT: umax z0.b, z0.b, #129259; CHECK-NEXT: ret260 %cmp = icmp ugt <vscale x 16 x i8> %a, splat(i8 129)261 %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 129)262 ret <vscale x 16 x i8> %res263}264 265define <vscale x 8 x i16> @umax_i16_pos(<vscale x 8 x i16> %a) {266; CHECK-LABEL: umax_i16_pos:267; CHECK: // %bb.0:268; CHECK-NEXT: umax z0.h, z0.h, #27269; CHECK-NEXT: ret270 %cmp = icmp ugt <vscale x 8 x i16> %a, splat(i16 27)271 %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 27)272 ret <vscale x 8 x i16> %res273}274 275define <vscale x 8 x i16> @umax_i16_out_of_range(<vscale x 8 x i16> %a) {276; CHECK-LABEL: umax_i16_out_of_range:277; CHECK: // %bb.0:278; CHECK-NEXT: dupm z1.b, #0x1279; CHECK-NEXT: ptrue p0.h280; CHECK-NEXT: umax z0.h, p0/m, z0.h, z1.h281; CHECK-NEXT: ret282 %cmp = icmp ugt <vscale x 8 x i16> %a, splat(i16 257)283 %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 257)284 ret <vscale x 8 x i16> %res285}286 287define <vscale x 4 x i32> @umax_i32_pos(<vscale x 4 x i32> %a) {288; CHECK-LABEL: umax_i32_pos:289; CHECK: // %bb.0:290; CHECK-NEXT: umax z0.s, z0.s, #27291; CHECK-NEXT: ret292 %cmp = icmp ugt <vscale x 4 x i32> %a, splat(i32 27)293 %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 27)294 ret <vscale x 4 x i32> %res295}296 297define <vscale x 4 x i32> @umax_i32_out_of_range(<vscale x 4 x i32> %a) {298; CHECK-LABEL: umax_i32_out_of_range:299; CHECK: // %bb.0:300; CHECK-NEXT: mov w8, #257 // =0x101301; CHECK-NEXT: ptrue p0.s302; CHECK-NEXT: mov z1.s, w8303; CHECK-NEXT: umax z0.s, p0/m, z0.s, z1.s304; CHECK-NEXT: ret305 %cmp = icmp ugt <vscale x 4 x i32> %a, splat(i32 257)306 %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 257)307 ret <vscale x 4 x i32> %res308}309 310define <vscale x 2 x i64> @umax_i64_pos(<vscale x 2 x i64> %a) {311; CHECK-LABEL: umax_i64_pos:312; CHECK: // %bb.0:313; CHECK-NEXT: umax z0.d, z0.d, #27314; CHECK-NEXT: ret315 %cmp = icmp ugt <vscale x 2 x i64> %a, splat(i64 27)316 %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 27)317 ret <vscale x 2 x i64> %res318}319 320define <vscale x 2 x i64> @umax_i64_out_of_range(<vscale x 2 x i64> %a) {321; CHECK-LABEL: umax_i64_out_of_range:322; CHECK: // %bb.0:323; CHECK-NEXT: mov z1.d, #65535 // =0xffff324; CHECK-NEXT: ptrue p0.d325; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d326; CHECK-NEXT: ret327 %cmp = icmp ugt <vscale x 2 x i64> %a, splat(i64 65535)328 %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 65535)329 ret <vscale x 2 x i64> %res330}331 332;333; UMIN334;335define <vscale x 16 x i8> @umin_i8_pos(<vscale x 16 x i8> %a) {336; CHECK-LABEL: umin_i8_pos:337; CHECK: // %bb.0:338; CHECK-NEXT: umin z0.b, z0.b, #27339; CHECK-NEXT: ret340 %cmp = icmp ult <vscale x 16 x i8> %a, splat(i8 27)341 %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 27)342 ret <vscale x 16 x i8> %res343}344 345define <vscale x 16 x i8> @umin_i8_large(<vscale x 16 x i8> %a) {346; CHECK-LABEL: umin_i8_large:347; CHECK: // %bb.0:348; CHECK-NEXT: umin z0.b, z0.b, #129349; CHECK-NEXT: ret350 %cmp = icmp ult <vscale x 16 x i8> %a, splat(i8 129)351 %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 129)352 ret <vscale x 16 x i8> %res353}354 355define <vscale x 8 x i16> @umin_i16_pos(<vscale x 8 x i16> %a) {356; CHECK-LABEL: umin_i16_pos:357; CHECK: // %bb.0:358; CHECK-NEXT: umin z0.h, z0.h, #27359; CHECK-NEXT: ret360 %cmp = icmp ult <vscale x 8 x i16> %a, splat(i16 27)361 %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 27)362 ret <vscale x 8 x i16> %res363}364 365define <vscale x 8 x i16> @umin_i16_out_of_range(<vscale x 8 x i16> %a) {366; CHECK-LABEL: umin_i16_out_of_range:367; CHECK: // %bb.0:368; CHECK-NEXT: dupm z1.b, #0x1369; CHECK-NEXT: ptrue p0.h370; CHECK-NEXT: umin z0.h, p0/m, z0.h, z1.h371; CHECK-NEXT: ret372 %cmp = icmp ult <vscale x 8 x i16> %a, splat(i16 257)373 %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 257)374 ret <vscale x 8 x i16> %res375}376 377define <vscale x 4 x i32> @umin_i32_pos(<vscale x 4 x i32> %a) {378; CHECK-LABEL: umin_i32_pos:379; CHECK: // %bb.0:380; CHECK-NEXT: umin z0.s, z0.s, #27381; CHECK-NEXT: ret382 %cmp = icmp ult <vscale x 4 x i32> %a, splat(i32 27)383 %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 27)384 ret <vscale x 4 x i32> %res385}386 387define <vscale x 4 x i32> @umin_i32_out_of_range(<vscale x 4 x i32> %a) {388; CHECK-LABEL: umin_i32_out_of_range:389; CHECK: // %bb.0:390; CHECK-NEXT: mov w8, #257 // =0x101391; CHECK-NEXT: ptrue p0.s392; CHECK-NEXT: mov z1.s, w8393; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s394; CHECK-NEXT: ret395 %cmp = icmp ult <vscale x 4 x i32> %a, splat(i32 257)396 %res = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 257)397 ret <vscale x 4 x i32> %res398}399 400define <vscale x 2 x i64> @umin_i64_pos(<vscale x 2 x i64> %a) {401; CHECK-LABEL: umin_i64_pos:402; CHECK: // %bb.0:403; CHECK-NEXT: umin z0.d, z0.d, #27404; CHECK-NEXT: ret405 %cmp = icmp ult <vscale x 2 x i64> %a, splat(i64 27)406 %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 27)407 ret <vscale x 2 x i64> %res408}409 410define <vscale x 2 x i64> @umin_i64_out_of_range(<vscale x 2 x i64> %a) {411; CHECK-LABEL: umin_i64_out_of_range:412; CHECK: // %bb.0:413; CHECK-NEXT: mov z1.d, #65535 // =0xffff414; CHECK-NEXT: ptrue p0.d415; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d416; CHECK-NEXT: ret417 %cmp = icmp ult <vscale x 2 x i64> %a, splat(i64 65535)418 %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 65535)419 ret <vscale x 2 x i64> %res420}421 422;423; MUL424;425define <vscale x 16 x i8> @mul_i8_neg(<vscale x 16 x i8> %a) {426; CHECK-LABEL: mul_i8_neg:427; CHECK: // %bb.0:428; CHECK-NEXT: mul z0.b, z0.b, #-17429; CHECK-NEXT: ret430 %res = mul <vscale x 16 x i8> %a, splat(i8 -17)431 ret <vscale x 16 x i8> %res432}433 434define <vscale x 16 x i8> @mul_i8_pos(<vscale x 16 x i8> %a) {435; CHECK-LABEL: mul_i8_pos:436; CHECK: // %bb.0:437; CHECK-NEXT: mul z0.b, z0.b, #105438; CHECK-NEXT: ret439 %res = mul <vscale x 16 x i8> %a, splat(i8 105)440 ret <vscale x 16 x i8> %res441}442 443define <vscale x 8 x i16> @mul_i16_neg(<vscale x 8 x i16> %a) {444; CHECK-LABEL: mul_i16_neg:445; CHECK: // %bb.0:446; CHECK-NEXT: mul z0.h, z0.h, #-17447; CHECK-NEXT: ret448 %res = mul <vscale x 8 x i16> %a, splat(i16 -17)449 ret <vscale x 8 x i16> %res450}451 452define <vscale x 8 x i16> @mul_i16_pos(<vscale x 8 x i16> %a) {453; CHECK-LABEL: mul_i16_pos:454; CHECK: // %bb.0:455; CHECK-NEXT: mul z0.h, z0.h, #105456; CHECK-NEXT: ret457 %res = mul <vscale x 8 x i16> %a, splat(i16 105)458 ret <vscale x 8 x i16> %res459}460 461define <vscale x 4 x i32> @mul_i32_neg(<vscale x 4 x i32> %a) {462; CHECK-LABEL: mul_i32_neg:463; CHECK: // %bb.0:464; CHECK-NEXT: mul z0.s, z0.s, #-17465; CHECK-NEXT: ret466 %res = mul <vscale x 4 x i32> %a, splat(i32 -17)467 ret <vscale x 4 x i32> %res468}469 470define <vscale x 4 x i32> @mul_i32_pos(<vscale x 4 x i32> %a) {471; CHECK-LABEL: mul_i32_pos:472; CHECK: // %bb.0:473; CHECK-NEXT: mul z0.s, z0.s, #105474; CHECK-NEXT: ret475 %res = mul <vscale x 4 x i32> %a, splat(i32 105)476 ret <vscale x 4 x i32> %res477}478 479define <vscale x 2 x i64> @mul_i64_neg(<vscale x 2 x i64> %a) {480; CHECK-LABEL: mul_i64_neg:481; CHECK: // %bb.0:482; CHECK-NEXT: mul z0.d, z0.d, #-17483; CHECK-NEXT: ret484 %res = mul <vscale x 2 x i64> %a, splat(i64 -17)485 ret <vscale x 2 x i64> %res486}487 488define <vscale x 2 x i64> @mul_i64_pos(<vscale x 2 x i64> %a) {489; CHECK-LABEL: mul_i64_pos:490; CHECK: // %bb.0:491; CHECK-NEXT: mul z0.d, z0.d, #105492; CHECK-NEXT: ret493 %res = mul <vscale x 2 x i64> %a, splat(i64 105)494 ret <vscale x 2 x i64> %res495}496 497define <vscale x 8 x i16> @mul_i16_range(<vscale x 8 x i16> %a) {498; CHECK-LABEL: mul_i16_range:499; CHECK: // %bb.0:500; CHECK-NEXT: mov z1.h, #255 // =0xff501; CHECK-NEXT: ptrue p0.h502; CHECK-NEXT: mul z0.h, p0/m, z0.h, z1.h503; CHECK-NEXT: ret504 %res = mul <vscale x 8 x i16> %a, splat(i16 255)505 ret <vscale x 8 x i16> %res506}507 508define <vscale x 4 x i32> @mul_i32_range(<vscale x 4 x i32> %a) {509; CHECK-LABEL: mul_i32_range:510; CHECK: // %bb.0:511; CHECK-NEXT: mov z1.s, #255 // =0xff512; CHECK-NEXT: ptrue p0.s513; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s514; CHECK-NEXT: ret515 %res = mul <vscale x 4 x i32> %a, splat(i32 255)516 ret <vscale x 4 x i32> %res517}518 519define <vscale x 2 x i64> @mul_i64_range(<vscale x 2 x i64> %a) {520; CHECK-LABEL: mul_i64_range:521; CHECK: // %bb.0:522; CHECK-NEXT: mov z1.d, #255 // =0xff523; CHECK-NEXT: ptrue p0.d524; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d525; CHECK-NEXT: ret526 %res = mul <vscale x 2 x i64> %a, splat(i64 255)527 ret <vscale x 2 x i64> %res528}529 530; ASR531 532define <vscale x 16 x i8> @asr_i8(<vscale x 16 x i8> %a){533; CHECK-LABEL: asr_i8:534; CHECK: // %bb.0:535; CHECK-NEXT: asr z0.b, z0.b, #7536; CHECK-NEXT: ret537 %lshr = ashr <vscale x 16 x i8> %a, splat(i8 7)538 ret <vscale x 16 x i8> %lshr539}540 541define <vscale x 8 x i16> @asr_i16(<vscale x 8 x i16> %a){542; CHECK-LABEL: asr_i16:543; CHECK: // %bb.0:544; CHECK-NEXT: asr z0.h, z0.h, #15545; CHECK-NEXT: ret546 %ashr = ashr <vscale x 8 x i16> %a, splat(i16 15)547 ret <vscale x 8 x i16> %ashr548}549 550define <vscale x 4 x i32> @asr_i32(<vscale x 4 x i32> %a){551; CHECK-LABEL: asr_i32:552; CHECK: // %bb.0:553; CHECK-NEXT: asr z0.s, z0.s, #31554; CHECK-NEXT: ret555 %ashr = ashr <vscale x 4 x i32> %a, splat(i32 31)556 ret <vscale x 4 x i32> %ashr557}558 559define <vscale x 2 x i64> @asr_i64(<vscale x 2 x i64> %a){560; CHECK-LABEL: asr_i64:561; CHECK: // %bb.0:562; CHECK-NEXT: asr z0.d, z0.d, #63563; CHECK-NEXT: ret564 %ashr = ashr <vscale x 2 x i64> %a, splat(i64 63)565 ret <vscale x 2 x i64> %ashr566}567 568; LSL569 570define <vscale x 16 x i8> @lsl_i8(<vscale x 16 x i8> %a){571; CHECK-LABEL: lsl_i8:572; CHECK: // %bb.0:573; CHECK-NEXT: lsl z0.b, z0.b, #7574; CHECK-NEXT: ret575 %shl = shl <vscale x 16 x i8> %a, splat(i8 7)576 ret <vscale x 16 x i8> %shl577}578 579define <vscale x 8 x i16> @lsl_i16(<vscale x 8 x i16> %a){580; CHECK-LABEL: lsl_i16:581; CHECK: // %bb.0:582; CHECK-NEXT: lsl z0.h, z0.h, #15583; CHECK-NEXT: ret584 %shl = shl <vscale x 8 x i16> %a, splat(i16 15)585 ret <vscale x 8 x i16> %shl586}587 588define <vscale x 4 x i32> @lsl_i32(<vscale x 4 x i32> %a){589; CHECK-LABEL: lsl_i32:590; CHECK: // %bb.0:591; CHECK-NEXT: lsl z0.s, z0.s, #31592; CHECK-NEXT: ret593 %shl = shl <vscale x 4 x i32> %a, splat(i32 31)594 ret <vscale x 4 x i32> %shl595}596 597define <vscale x 2 x i64> @lsl_i64(<vscale x 2 x i64> %a){598; CHECK-LABEL: lsl_i64:599; CHECK: // %bb.0:600; CHECK-NEXT: lsl z0.d, z0.d, #63601; CHECK-NEXT: ret602 %shl = shl <vscale x 2 x i64> %a, splat(i64 63)603 ret <vscale x 2 x i64> %shl604}605 606; LSR607 608define <vscale x 16 x i8> @lsr_i8(<vscale x 16 x i8> %a){609; CHECK-LABEL: lsr_i8:610; CHECK: // %bb.0:611; CHECK-NEXT: lsr z0.b, z0.b, #7612; CHECK-NEXT: ret613 %lshr = lshr <vscale x 16 x i8> %a, splat(i8 7)614 ret <vscale x 16 x i8> %lshr615}616 617define <vscale x 8 x i16> @lsr_i16(<vscale x 8 x i16> %a){618; CHECK-LABEL: lsr_i16:619; CHECK: // %bb.0:620; CHECK-NEXT: lsr z0.h, z0.h, #15621; CHECK-NEXT: ret622 %lshr = lshr <vscale x 8 x i16> %a, splat(i16 15)623 ret <vscale x 8 x i16> %lshr624}625 626define <vscale x 4 x i32> @lsr_i32(<vscale x 4 x i32> %a){627; CHECK-LABEL: lsr_i32:628; CHECK: // %bb.0:629; CHECK-NEXT: lsr z0.s, z0.s, #31630; CHECK-NEXT: ret631 %lshr = lshr <vscale x 4 x i32> %a, splat(i32 31)632 ret <vscale x 4 x i32> %lshr633}634 635define <vscale x 2 x i64> @lsr_i64(<vscale x 2 x i64> %a){636; CHECK-LABEL: lsr_i64:637; CHECK: // %bb.0:638; CHECK-NEXT: lsr z0.d, z0.d, #63639; CHECK-NEXT: ret640 %lshr = lshr <vscale x 2 x i64> %a, splat(i64 63)641 ret <vscale x 2 x i64> %lshr642}643 644define <vscale x 4 x i32> @sdiv_const(<vscale x 4 x i32> %a) #0 {645; CHECK-LABEL: sdiv_const:646; CHECK: // %bb.0: // %entry647; CHECK-NEXT: mov z1.s, #3 // =0x3648; CHECK-NEXT: ptrue p0.s649; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s650; CHECK-NEXT: ret651entry:652 %div = sdiv <vscale x 4 x i32> %a, splat (i32 3)653 ret <vscale x 4 x i32> %div654}655 656define <vscale x 4 x i32> @udiv_const(<vscale x 4 x i32> %a) #0 {657; CHECK-LABEL: udiv_const:658; CHECK: // %bb.0: // %entry659; CHECK-NEXT: mov z1.s, #3 // =0x3660; CHECK-NEXT: ptrue p0.s661; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s662; CHECK-NEXT: ret663entry:664 %div = udiv <vscale x 4 x i32> %a, splat (i32 3)665 ret <vscale x 4 x i32> %div666}667 668;669; UQSUB670;671define <vscale x 8 x i16> @uqsub(<vscale x 8 x i16> %a) {672; CHECK-LABEL: uqsub:673; CHECK: // %bb.0:674; CHECK-NEXT: uqsub z0.h, z0.h, #32768 // =0x8000675; CHECK-NEXT: ret676 %cmp = icmp slt <vscale x 8 x i16> %a, zeroinitializer677 %sub = xor <vscale x 8 x i16> %a, splat (i16 -32768)678 %sel = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %sub, <vscale x 8 x i16> zeroinitializer679 ret <vscale x 8 x i16> %sel680}681 682attributes #0 = { minsize }683