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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -use-constant-int-for-scalable-splat < %s | FileCheck %s4 5;6; SVE Arith Vector Immediate Unpredicated CodeGen7;8 9; ADD10define <vscale x 16 x i8> @add_i8_low(<vscale x 16 x i8> %a) {11; CHECK-LABEL: add_i8_low:12; CHECK: // %bb.0:13; CHECK-NEXT: add z0.b, z0.b, #30 // =0x1e14; CHECK-NEXT: ret15 %res = add <vscale x 16 x i8> %a, splat(i8 30)16 ret <vscale x 16 x i8> %res17}18 19define <vscale x 8 x i16> @add_i16_low(<vscale x 8 x i16> %a) {20; CHECK-LABEL: add_i16_low:21; CHECK: // %bb.0:22; CHECK-NEXT: add z0.h, z0.h, #30 // =0x1e23; CHECK-NEXT: ret24 %res = add <vscale x 8 x i16> %a, splat(i16 30)25 ret <vscale x 8 x i16> %res26}27 28define <vscale x 8 x i16> @add_i16_high(<vscale x 8 x i16> %a) {29; CHECK-LABEL: add_i16_high:30; CHECK: // %bb.0:31; CHECK-NEXT: add z0.h, z0.h, #1024 // =0x40032; CHECK-NEXT: ret33 %res = add <vscale x 8 x i16> %a, splat(i16 1024)34 ret <vscale x 8 x i16> %res35}36 37define <vscale x 4 x i32> @add_i32_low(<vscale x 4 x i32> %a) {38; CHECK-LABEL: add_i32_low:39; CHECK: // %bb.0:40; CHECK-NEXT: add z0.s, z0.s, #30 // =0x1e41; CHECK-NEXT: ret42 %res = add <vscale x 4 x i32> %a, splat(i32 30)43 ret <vscale x 4 x i32> %res44}45 46define <vscale x 4 x i32> @add_i32_high(<vscale x 4 x i32> %a) {47; CHECK-LABEL: add_i32_high:48; CHECK: // %bb.0:49; CHECK-NEXT: add z0.s, z0.s, #1024 // =0x40050; CHECK-NEXT: ret51 %res = add <vscale x 4 x i32> %a, splat(i32 1024)52 ret <vscale x 4 x i32> %res53}54 55define <vscale x 2 x i64> @add_i64_low(<vscale x 2 x i64> %a) {56; CHECK-LABEL: add_i64_low:57; CHECK: // %bb.0:58; CHECK-NEXT: add z0.d, z0.d, #30 // =0x1e59; CHECK-NEXT: ret60 %res = add <vscale x 2 x i64> %a, splat(i64 30)61 ret <vscale x 2 x i64> %res62}63 64define <vscale x 2 x i64> @add_i64_high(<vscale x 2 x i64> %a) {65; CHECK-LABEL: add_i64_high:66; CHECK: // %bb.0:67; CHECK-NEXT: add z0.d, z0.d, #1024 // =0x40068; CHECK-NEXT: ret69 %res = add <vscale x 2 x i64> %a, splat(i64 1024)70 ret <vscale x 2 x i64> %res71}72 73define <vscale x 16 x i8> @add_i8_signedness(<vscale x 16 x i8> %a) {74; CHECK-LABEL: add_i8_signedness:75; CHECK: // %bb.0:76; CHECK-NEXT: add z0.b, z0.b, #255 // =0xff77; CHECK-NEXT: ret78 %res = add <vscale x 16 x i8> %a, splat(i8 255)79 ret <vscale x 16 x i8> %res80}81 82define <vscale x 8 x i16> @add_i16_signedness(<vscale x 8 x i16> %a) {83; CHECK-LABEL: add_i16_signedness:84; CHECK: // %bb.0:85; CHECK-NEXT: add z0.h, z0.h, #65280 // =0xff0086; CHECK-NEXT: ret87 %res = add <vscale x 8 x i16> %a, splat(i16 65280)88 ret <vscale x 8 x i16> %res89}90 91; SUBR92define <vscale x 16 x i8> @subr_i8_low(<vscale x 16 x i8> %a) {93; CHECK-LABEL: subr_i8_low:94; CHECK: // %bb.0:95; CHECK-NEXT: subr z0.b, z0.b, #30 // =0x1e96; CHECK-NEXT: ret97 %res = sub <vscale x 16 x i8> splat(i8 30), %a98 ret <vscale x 16 x i8> %res99}100 101define <vscale x 8 x i16> @subr_i16_low(<vscale x 8 x i16> %a) {102; CHECK-LABEL: subr_i16_low:103; CHECK: // %bb.0:104; CHECK-NEXT: subr z0.h, z0.h, #30 // =0x1e105; CHECK-NEXT: ret106 %res = sub <vscale x 8 x i16> splat(i16 30), %a107 ret <vscale x 8 x i16> %res108}109 110define <vscale x 8 x i16> @subr_i16_high(<vscale x 8 x i16> %a) {111; CHECK-LABEL: subr_i16_high:112; CHECK: // %bb.0:113; CHECK-NEXT: subr z0.h, z0.h, #1024 // =0x400114; CHECK-NEXT: ret115 %res = sub <vscale x 8 x i16> splat(i16 1024), %a116 ret <vscale x 8 x i16> %res117}118 119define <vscale x 4 x i32> @subr_i32_low(<vscale x 4 x i32> %a) {120; CHECK-LABEL: subr_i32_low:121; CHECK: // %bb.0:122; CHECK-NEXT: subr z0.s, z0.s, #30 // =0x1e123; CHECK-NEXT: ret124 %res = sub <vscale x 4 x i32> splat(i32 30), %a125 ret <vscale x 4 x i32> %res126}127 128define <vscale x 4 x i32> @subr_i32_high(<vscale x 4 x i32> %a) {129; CHECK-LABEL: subr_i32_high:130; CHECK: // %bb.0:131; CHECK-NEXT: subr z0.s, z0.s, #1024 // =0x400132; CHECK-NEXT: ret133 %res = sub <vscale x 4 x i32> splat(i32 1024), %a134 ret <vscale x 4 x i32> %res135}136 137define <vscale x 2 x i64> @subr_i64_low(<vscale x 2 x i64> %a) {138; CHECK-LABEL: subr_i64_low:139; CHECK: // %bb.0:140; CHECK-NEXT: subr z0.d, z0.d, #30 // =0x1e141; CHECK-NEXT: ret142 %res = sub <vscale x 2 x i64> splat(i64 30), %a143 ret <vscale x 2 x i64> %res144}145 146define <vscale x 2 x i64> @subr_i64_high(<vscale x 2 x i64> %a) {147; CHECK-LABEL: subr_i64_high:148; CHECK: // %bb.0:149; CHECK-NEXT: subr z0.d, z0.d, #1024 // =0x400150; CHECK-NEXT: ret151 %res = sub <vscale x 2 x i64> splat(i64 1024), %a152 ret <vscale x 2 x i64> %res153}154 155; SUB156define <vscale x 16 x i8> @sub_i8_low(<vscale x 16 x i8> %a) {157; CHECK-LABEL: sub_i8_low:158; CHECK: // %bb.0:159; CHECK-NEXT: sub z0.b, z0.b, #30 // =0x1e160; CHECK-NEXT: ret161 %res = sub <vscale x 16 x i8> %a, splat(i8 30)162 ret <vscale x 16 x i8> %res163}164 165define <vscale x 8 x i16> @sub_i16_low(<vscale x 8 x i16> %a) {166; CHECK-LABEL: sub_i16_low:167; CHECK: // %bb.0:168; CHECK-NEXT: sub z0.h, z0.h, #30 // =0x1e169; CHECK-NEXT: ret170 %res = sub <vscale x 8 x i16> %a, splat(i16 30)171 ret <vscale x 8 x i16> %res172}173 174define <vscale x 8 x i16> @sub_i16_high(<vscale x 8 x i16> %a) {175; CHECK-LABEL: sub_i16_high:176; CHECK: // %bb.0:177; CHECK-NEXT: sub z0.h, z0.h, #1024 // =0x400178; CHECK-NEXT: ret179 %res = sub <vscale x 8 x i16> %a, splat(i16 1024)180 ret <vscale x 8 x i16> %res181}182 183define <vscale x 4 x i32> @sub_i32_low(<vscale x 4 x i32> %a) {184; CHECK-LABEL: sub_i32_low:185; CHECK: // %bb.0:186; CHECK-NEXT: sub z0.s, z0.s, #30 // =0x1e187; CHECK-NEXT: ret188 %res = sub <vscale x 4 x i32> %a, splat(i32 30)189 ret <vscale x 4 x i32> %res190}191 192define <vscale x 4 x i32> @sub_i32_high(<vscale x 4 x i32> %a) {193; CHECK-LABEL: sub_i32_high:194; CHECK: // %bb.0:195; CHECK-NEXT: sub z0.s, z0.s, #1024 // =0x400196; CHECK-NEXT: ret197 %res = sub <vscale x 4 x i32> %a, splat(i32 1024)198 ret <vscale x 4 x i32> %res199}200 201define <vscale x 2 x i64> @sub_i64_low(<vscale x 2 x i64> %a) {202; CHECK-LABEL: sub_i64_low:203; CHECK: // %bb.0:204; CHECK-NEXT: sub z0.d, z0.d, #30 // =0x1e205; CHECK-NEXT: ret206 %res = sub <vscale x 2 x i64> %a, splat(i64 30)207 ret <vscale x 2 x i64> %res208}209 210define <vscale x 2 x i64> @sub_i64_high(<vscale x 2 x i64> %a) {211; CHECK-LABEL: sub_i64_high:212; CHECK: // %bb.0:213; CHECK-NEXT: sub z0.d, z0.d, #1024 // =0x400214; CHECK-NEXT: ret215 %res = sub <vscale x 2 x i64> %a, splat(i64 1024)216 ret <vscale x 2 x i64> %res217}218 219; SUB via -ve add220define <vscale x 16 x i8> @addnve_i8_low(<vscale x 16 x i8> %a) {221; CHECK-LABEL: addnve_i8_low:222; CHECK: // %bb.0:223; CHECK-NEXT: add z0.b, z0.b, #226 // =0xe2224; CHECK-NEXT: ret225 %res = add <vscale x 16 x i8> %a, splat(i8 -30)226 ret <vscale x 16 x i8> %res227}228 229define <vscale x 8 x i16> @addnve_i16_low(<vscale x 8 x i16> %a) {230; CHECK-LABEL: addnve_i16_low:231; CHECK: // %bb.0:232; CHECK-NEXT: sub z0.h, z0.h, #30 // =0x1e233; CHECK-NEXT: ret234 %res = add <vscale x 8 x i16> %a, splat(i16 -30)235 ret <vscale x 8 x i16> %res236}237 238define <vscale x 8 x i16> @addnve_i16_high(<vscale x 8 x i16> %a) {239; CHECK-LABEL: addnve_i16_high:240; CHECK: // %bb.0:241; CHECK-NEXT: add z0.h, z0.h, #64512 // =0xfc00242; CHECK-NEXT: ret243 %res = add <vscale x 8 x i16> %a, splat(i16 -1024)244 ret <vscale x 8 x i16> %res245}246 247define <vscale x 4 x i32> @addnve_i32_low(<vscale x 4 x i32> %a) {248; CHECK-LABEL: addnve_i32_low:249; CHECK: // %bb.0:250; CHECK-NEXT: sub z0.s, z0.s, #30 // =0x1e251; CHECK-NEXT: ret252 %res = add <vscale x 4 x i32> %a, splat(i32 -30)253 ret <vscale x 4 x i32> %res254}255 256define <vscale x 4 x i32> @addnve_i32_high(<vscale x 4 x i32> %a) {257; CHECK-LABEL: addnve_i32_high:258; CHECK: // %bb.0:259; CHECK-NEXT: sub z0.s, z0.s, #1024 // =0x400260; CHECK-NEXT: ret261 %res = add <vscale x 4 x i32> %a, splat(i32 -1024)262 ret <vscale x 4 x i32> %res263}264 265define <vscale x 2 x i64> @addnve_i64_low(<vscale x 2 x i64> %a) {266; CHECK-LABEL: addnve_i64_low:267; CHECK: // %bb.0:268; CHECK-NEXT: sub z0.d, z0.d, #30 // =0x1e269; CHECK-NEXT: ret270 %res = add <vscale x 2 x i64> %a, splat(i64 -30)271 ret <vscale x 2 x i64> %res272}273 274define <vscale x 2 x i64> @addnve_i64_high(<vscale x 2 x i64> %a) {275; CHECK-LABEL: addnve_i64_high:276; CHECK: // %bb.0:277; CHECK-NEXT: sub z0.d, z0.d, #1024 // =0x400278; CHECK-NEXT: ret279 %res = add <vscale x 2 x i64> %a, splat(i64 -1024)280 ret <vscale x 2 x i64> %res281}282 283; SQADD284define <vscale x 16 x i8> @sqadd_i8_low(<vscale x 16 x i8> %a) {285; CHECK-LABEL: sqadd_i8_low:286; CHECK: // %bb.0:287; CHECK-NEXT: sqadd z0.b, z0.b, #30 // =0x1e288; CHECK-NEXT: ret289 %res = call <vscale x 16 x i8> @llvm.sadd.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 30))290 ret <vscale x 16 x i8> %res291}292 293define <vscale x 8 x i16> @sqadd_i16_low(<vscale x 8 x i16> %a) {294; CHECK-LABEL: sqadd_i16_low:295; CHECK: // %bb.0:296; CHECK-NEXT: sqadd z0.h, z0.h, #30 // =0x1e297; CHECK-NEXT: ret298 %res = call <vscale x 8 x i16> @llvm.sadd.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 30))299 ret <vscale x 8 x i16> %res300}301 302define <vscale x 8 x i16> @sqadd_i16_high(<vscale x 8 x i16> %a) {303; CHECK-LABEL: sqadd_i16_high:304; CHECK: // %bb.0:305; CHECK-NEXT: sqadd z0.h, z0.h, #1024 // =0x400306; CHECK-NEXT: ret307 %res = call <vscale x 8 x i16> @llvm.sadd.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 1024))308 ret <vscale x 8 x i16> %res309}310 311define <vscale x 4 x i32> @sqadd_i32_low(<vscale x 4 x i32> %a) {312; CHECK-LABEL: sqadd_i32_low:313; CHECK: // %bb.0:314; CHECK-NEXT: sqadd z0.s, z0.s, #30 // =0x1e315; CHECK-NEXT: ret316 %res = call <vscale x 4 x i32> @llvm.sadd.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 30))317 ret <vscale x 4 x i32> %res318}319 320define <vscale x 4 x i32> @sqadd_i32_high(<vscale x 4 x i32> %a) {321; CHECK-LABEL: sqadd_i32_high:322; CHECK: // %bb.0:323; CHECK-NEXT: sqadd z0.s, z0.s, #1024 // =0x400324; CHECK-NEXT: ret325 %res = call <vscale x 4 x i32> @llvm.sadd.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 1024))326 ret <vscale x 4 x i32> %res327}328 329define <vscale x 2 x i64> @sqadd_i64_low(<vscale x 2 x i64> %a) {330; CHECK-LABEL: sqadd_i64_low:331; CHECK: // %bb.0:332; CHECK-NEXT: sqadd z0.d, z0.d, #30 // =0x1e333; CHECK-NEXT: ret334 %res = call <vscale x 2 x i64> @llvm.sadd.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 30))335 ret <vscale x 2 x i64> %res336}337 338define <vscale x 2 x i64> @sqadd_i64_high(<vscale x 2 x i64> %a) {339; CHECK-LABEL: sqadd_i64_high:340; CHECK: // %bb.0:341; CHECK-NEXT: sqadd z0.d, z0.d, #1024 // =0x400342; CHECK-NEXT: ret343 %res = call <vscale x 2 x i64> @llvm.sadd.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 1024))344 ret <vscale x 2 x i64> %res345}346 347; UQADD348define <vscale x 16 x i8> @uqadd_i8_low(<vscale x 16 x i8> %a) {349; CHECK-LABEL: uqadd_i8_low:350; CHECK: // %bb.0:351; CHECK-NEXT: uqadd z0.b, z0.b, #30 // =0x1e352; CHECK-NEXT: ret353 %res = call <vscale x 16 x i8> @llvm.uadd.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 30))354 ret <vscale x 16 x i8> %res355}356 357define <vscale x 8 x i16> @uqadd_i16_low(<vscale x 8 x i16> %a) {358; CHECK-LABEL: uqadd_i16_low:359; CHECK: // %bb.0:360; CHECK-NEXT: uqadd z0.h, z0.h, #30 // =0x1e361; CHECK-NEXT: ret362 %res = call <vscale x 8 x i16> @llvm.uadd.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 30))363 ret <vscale x 8 x i16> %res364}365 366define <vscale x 8 x i16> @uqadd_i16_high(<vscale x 8 x i16> %a) {367; CHECK-LABEL: uqadd_i16_high:368; CHECK: // %bb.0:369; CHECK-NEXT: uqadd z0.h, z0.h, #1024 // =0x400370; CHECK-NEXT: ret371 %res = call <vscale x 8 x i16> @llvm.uadd.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 1024))372 ret <vscale x 8 x i16> %res373}374 375define <vscale x 4 x i32> @uqadd_i32_low(<vscale x 4 x i32> %a) {376; CHECK-LABEL: uqadd_i32_low:377; CHECK: // %bb.0:378; CHECK-NEXT: uqadd z0.s, z0.s, #30 // =0x1e379; CHECK-NEXT: ret380 %res = call <vscale x 4 x i32> @llvm.uadd.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 30))381 ret <vscale x 4 x i32> %res382}383 384define <vscale x 4 x i32> @uqadd_i32_high(<vscale x 4 x i32> %a) {385; CHECK-LABEL: uqadd_i32_high:386; CHECK: // %bb.0:387; CHECK-NEXT: uqadd z0.s, z0.s, #1024 // =0x400388; CHECK-NEXT: ret389 %res = call <vscale x 4 x i32> @llvm.uadd.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 1024))390 ret <vscale x 4 x i32> %res391}392 393define <vscale x 2 x i64> @uqadd_i64_low(<vscale x 2 x i64> %a) {394; CHECK-LABEL: uqadd_i64_low:395; CHECK: // %bb.0:396; CHECK-NEXT: uqadd z0.d, z0.d, #30 // =0x1e397; CHECK-NEXT: ret398 %res = call <vscale x 2 x i64> @llvm.uadd.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 30))399 ret <vscale x 2 x i64> %res400}401 402define <vscale x 2 x i64> @uqadd_i64_high(<vscale x 2 x i64> %a) {403; CHECK-LABEL: uqadd_i64_high:404; CHECK: // %bb.0:405; CHECK-NEXT: uqadd z0.d, z0.d, #1024 // =0x400406; CHECK-NEXT: ret407 %res = call <vscale x 2 x i64> @llvm.uadd.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 1024))408 ret <vscale x 2 x i64> %res409}410 411; SQSUB412define <vscale x 16 x i8> @sqsub_i8_low(<vscale x 16 x i8> %a) {413; CHECK-LABEL: sqsub_i8_low:414; CHECK: // %bb.0:415; CHECK-NEXT: sqsub z0.b, z0.b, #30 // =0x1e416; CHECK-NEXT: ret417 %res = call <vscale x 16 x i8> @llvm.ssub.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 30))418 ret <vscale x 16 x i8> %res419}420 421define <vscale x 8 x i16> @sqsub_i16_low(<vscale x 8 x i16> %a) {422; CHECK-LABEL: sqsub_i16_low:423; CHECK: // %bb.0:424; CHECK-NEXT: sqsub z0.h, z0.h, #30 // =0x1e425; CHECK-NEXT: ret426 %res = call <vscale x 8 x i16> @llvm.ssub.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 30))427 ret <vscale x 8 x i16> %res428}429 430define <vscale x 8 x i16> @sqsub_i16_high(<vscale x 8 x i16> %a) {431; CHECK-LABEL: sqsub_i16_high:432; CHECK: // %bb.0:433; CHECK-NEXT: sqsub z0.h, z0.h, #1024 // =0x400434; CHECK-NEXT: ret435 %res = call <vscale x 8 x i16> @llvm.ssub.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 1024))436 ret <vscale x 8 x i16> %res437}438 439define <vscale x 4 x i32> @sqsub_i32_low(<vscale x 4 x i32> %a) {440; CHECK-LABEL: sqsub_i32_low:441; CHECK: // %bb.0:442; CHECK-NEXT: sqsub z0.s, z0.s, #30 // =0x1e443; CHECK-NEXT: ret444 %res = call <vscale x 4 x i32> @llvm.ssub.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 30))445 ret <vscale x 4 x i32> %res446}447 448define <vscale x 4 x i32> @sqsub_i32_high(<vscale x 4 x i32> %a) {449; CHECK-LABEL: sqsub_i32_high:450; CHECK: // %bb.0:451; CHECK-NEXT: sqsub z0.s, z0.s, #1024 // =0x400452; CHECK-NEXT: ret453 %res = call <vscale x 4 x i32> @llvm.ssub.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 1024))454 ret <vscale x 4 x i32> %res455}456 457define <vscale x 2 x i64> @sqsub_i64_low(<vscale x 2 x i64> %a) {458; CHECK-LABEL: sqsub_i64_low:459; CHECK: // %bb.0:460; CHECK-NEXT: sqsub z0.d, z0.d, #30 // =0x1e461; CHECK-NEXT: ret462 %res = call <vscale x 2 x i64> @llvm.ssub.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 30))463 ret <vscale x 2 x i64> %res464}465 466define <vscale x 2 x i64> @sqsub_i64_high(<vscale x 2 x i64> %a) {467; CHECK-LABEL: sqsub_i64_high:468; CHECK: // %bb.0:469; CHECK-NEXT: sqsub z0.d, z0.d, #1024 // =0x400470; CHECK-NEXT: ret471 %res = call <vscale x 2 x i64> @llvm.ssub.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 1024))472 ret <vscale x 2 x i64> %res473}474 475; UQSUB476define <vscale x 16 x i8> @uqsub_i8_low(<vscale x 16 x i8> %a) {477; CHECK-LABEL: uqsub_i8_low:478; CHECK: // %bb.0:479; CHECK-NEXT: uqsub z0.b, z0.b, #30 // =0x1e480; CHECK-NEXT: ret481 %res = call <vscale x 16 x i8> @llvm.usub.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 30))482 ret <vscale x 16 x i8> %res483}484 485define <vscale x 8 x i16> @uqsub_i16_low(<vscale x 8 x i16> %a) {486; CHECK-LABEL: uqsub_i16_low:487; CHECK: // %bb.0:488; CHECK-NEXT: uqsub z0.h, z0.h, #30 // =0x1e489; CHECK-NEXT: ret490 %res = call <vscale x 8 x i16> @llvm.usub.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 30))491 ret <vscale x 8 x i16> %res492}493 494define <vscale x 8 x i16> @uqsub_i16_high(<vscale x 8 x i16> %a) {495; CHECK-LABEL: uqsub_i16_high:496; CHECK: // %bb.0:497; CHECK-NEXT: uqsub z0.h, z0.h, #1024 // =0x400498; CHECK-NEXT: ret499 %res = call <vscale x 8 x i16> @llvm.usub.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 1024))500 ret <vscale x 8 x i16> %res501}502 503define <vscale x 4 x i32> @uqsub_i32_low(<vscale x 4 x i32> %a) {504; CHECK-LABEL: uqsub_i32_low:505; CHECK: // %bb.0:506; CHECK-NEXT: uqsub z0.s, z0.s, #30 // =0x1e507; CHECK-NEXT: ret508 %res = call <vscale x 4 x i32> @llvm.usub.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 30))509 ret <vscale x 4 x i32> %res510}511 512define <vscale x 4 x i32> @uqsub_i32_high(<vscale x 4 x i32> %a) {513; CHECK-LABEL: uqsub_i32_high:514; CHECK: // %bb.0:515; CHECK-NEXT: uqsub z0.s, z0.s, #1024 // =0x400516; CHECK-NEXT: ret517 %res = call <vscale x 4 x i32> @llvm.usub.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 1024))518 ret <vscale x 4 x i32> %res519}520 521define <vscale x 2 x i64> @uqsub_i64_low(<vscale x 2 x i64> %a) {522; CHECK-LABEL: uqsub_i64_low:523; CHECK: // %bb.0:524; CHECK-NEXT: uqsub z0.d, z0.d, #30 // =0x1e525; CHECK-NEXT: ret526 %res = call <vscale x 2 x i64> @llvm.usub.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 30))527 ret <vscale x 2 x i64> %res528}529 530define <vscale x 2 x i64> @uqsub_i64_high(<vscale x 2 x i64> %a) {531; CHECK-LABEL: uqsub_i64_high:532; CHECK: // %bb.0:533; CHECK-NEXT: uqsub z0.d, z0.d, #1024 // =0x400534; CHECK-NEXT: ret535 %res = call <vscale x 2 x i64> @llvm.usub.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 1024))536 ret <vscale x 2 x i64> %res537}538 539declare <vscale x 16 x i8> @llvm.sadd.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)540declare <vscale x 8 x i16> @llvm.sadd.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)541declare <vscale x 4 x i32> @llvm.sadd.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)542declare <vscale x 2 x i64> @llvm.sadd.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)543declare <vscale x 16 x i8> @llvm.uadd.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)544declare <vscale x 8 x i16> @llvm.uadd.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)545declare <vscale x 4 x i32> @llvm.uadd.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)546declare <vscale x 2 x i64> @llvm.uadd.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)547declare <vscale x 16 x i8> @llvm.ssub.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)548declare <vscale x 8 x i16> @llvm.ssub.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)549declare <vscale x 4 x i32> @llvm.ssub.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)550declare <vscale x 2 x i64> @llvm.ssub.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)551declare <vscale x 16 x i8> @llvm.usub.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)552declare <vscale x 8 x i16> @llvm.usub.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)553declare <vscale x 4 x i32> @llvm.usub.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)554declare <vscale x 2 x i64> @llvm.usub.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)555