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1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s2 3;4; SVE Logical Vector Immediate Unpredicated CodeGen5;6 7; ORR8define <vscale x 16 x i8> @orr_i8(<vscale x 16 x i8> %a) {9; CHECK-LABEL: orr_i8:10; CHECK: orr z0.b, z0.b, #0xf11; CHECK-NEXT: ret12 %res = or <vscale x 16 x i8> %a, splat(i8 15)13 ret <vscale x 16 x i8> %res14}15 16define <vscale x 8 x i16> @orr_i16(<vscale x 8 x i16> %a) {17; CHECK-LABEL: orr_i16:18; CHECK: orr z0.h, z0.h, #0xfc0719; CHECK-NEXT: ret20 %res = or <vscale x 8 x i16> %a, splat(i16 64519)21 ret <vscale x 8 x i16> %res22}23 24define <vscale x 4 x i32> @orr_i32(<vscale x 4 x i32> %a) {25; CHECK-LABEL: orr_i32:26; CHECK: orr z0.s, z0.s, #0xffff0027; CHECK-NEXT: ret28 %res = or <vscale x 4 x i32> %a, splat(i32 16776960)29 ret <vscale x 4 x i32> %res30}31 32define <vscale x 2 x i64> @orr_i64(<vscale x 2 x i64> %a) {33; CHECK-LABEL: orr_i64:34; CHECK: orr z0.d, z0.d, #0xfffc00000000000035; CHECK-NEXT: ret36 %res = or <vscale x 2 x i64> %a, splat(i64 18445618173802708992)37 ret <vscale x 2 x i64> %res38}39 40; EOR41define <vscale x 16 x i8> @eor_i8(<vscale x 16 x i8> %a) {42; CHECK-LABEL: eor_i8:43; CHECK: eor z0.b, z0.b, #0xf44; CHECK-NEXT: ret45 %res = xor <vscale x 16 x i8> %a, splat(i8 15)46 ret <vscale x 16 x i8> %res47}48 49define <vscale x 8 x i16> @eor_i16(<vscale x 8 x i16> %a) {50; CHECK-LABEL: eor_i16:51; CHECK: eor z0.h, z0.h, #0xfc0752; CHECK-NEXT: ret53 %res = xor <vscale x 8 x i16> %a, splat(i16 64519)54 ret <vscale x 8 x i16> %res55}56 57define <vscale x 4 x i32> @eor_i32(<vscale x 4 x i32> %a) {58; CHECK-LABEL: eor_i32:59; CHECK: eor z0.s, z0.s, #0xffff0060; CHECK-NEXT: ret61 %res = xor <vscale x 4 x i32> %a, splat(i32 16776960)62 ret <vscale x 4 x i32> %res63}64 65define <vscale x 2 x i64> @eor_i64(<vscale x 2 x i64> %a) {66; CHECK-LABEL: eor_i64:67; CHECK: eor z0.d, z0.d, #0xfffc00000000000068; CHECK-NEXT: ret69 %res = xor <vscale x 2 x i64> %a, splat(i64 18445618173802708992)70 ret <vscale x 2 x i64> %res71}72 73; AND74define <vscale x 16 x i8> @and_i8(<vscale x 16 x i8> %a) {75; CHECK-LABEL: and_i8:76; CHECK: and z0.b, z0.b, #0xf77; CHECK-NEXT: ret78 %res = and <vscale x 16 x i8> %a, splat(i8 15)79 ret <vscale x 16 x i8> %res80}81 82define <vscale x 8 x i16> @and_i16(<vscale x 8 x i16> %a) {83; CHECK-LABEL: and_i16:84; CHECK: and z0.h, z0.h, #0xfc0785; CHECK-NEXT: ret86 %res = and <vscale x 8 x i16> %a, splat(i16 64519)87 ret <vscale x 8 x i16> %res88}89 90define <vscale x 4 x i32> @and_i32(<vscale x 4 x i32> %a) {91; CHECK-LABEL: and_i32:92; CHECK: and z0.s, z0.s, #0xffff0093; CHECK-NEXT: ret94 %res = and <vscale x 4 x i32> %a, splat(i32 16776960)95 ret <vscale x 4 x i32> %res96}97 98define <vscale x 2 x i64> @and_i64(<vscale x 2 x i64> %a) {99; CHECK-LABEL: and_i64:100; CHECK: and z0.d, z0.d, #0xfffc000000000000101; CHECK-NEXT: ret102 %res = and <vscale x 2 x i64> %a, splat(i64 18445618173802708992)103 ret <vscale x 2 x i64> %res104}105