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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4define <vscale x 2 x i64> @and_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {5; CHECK-LABEL: and_d:6; CHECK: // %bb.0:7; CHECK-NEXT: and z0.d, z0.d, z1.d8; CHECK-NEXT: ret9 %res = and <vscale x 2 x i64> %a, %b10 ret <vscale x 2 x i64> %res11}12 13define <vscale x 4 x i32> @and_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {14; CHECK-LABEL: and_s:15; CHECK: // %bb.0:16; CHECK-NEXT: and z0.d, z0.d, z1.d17; CHECK-NEXT: ret18 %res = and <vscale x 4 x i32> %a, %b19 ret <vscale x 4 x i32> %res20}21 22define <vscale x 8 x i16> @and_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {23; CHECK-LABEL: and_h:24; CHECK: // %bb.0:25; CHECK-NEXT: and z0.d, z0.d, z1.d26; CHECK-NEXT: ret27 %res = and <vscale x 8 x i16> %a, %b28 ret <vscale x 8 x i16> %res29}30 31define <vscale x 16 x i8> @and_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {32; CHECK-LABEL: and_b:33; CHECK: // %bb.0:34; CHECK-NEXT: and z0.d, z0.d, z1.d35; CHECK-NEXT: ret36 %res = and <vscale x 16 x i8> %a, %b37 ret <vscale x 16 x i8> %res38}39 40define <vscale x 16 x i8> @and_b_zero(<vscale x 16 x i8> %a) {41; CHECK-LABEL: and_b_zero:42; CHECK: // %bb.0:43; CHECK-NEXT: movi v0.2d, #000000000000000044; CHECK-NEXT: ret45 %res = and <vscale x 16 x i8> %a, zeroinitializer46 ret <vscale x 16 x i8> %res47}48 49define <vscale x 1 x i1> @and_pred_q(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {50; CHECK-LABEL: and_pred_q:51; CHECK: // %bb.0:52; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b53; CHECK-NEXT: ret54 %res = and <vscale x 1 x i1> %a, %b55 ret <vscale x 1 x i1> %res56}57 58define <vscale x 2 x i1> @and_pred_d(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {59; CHECK-LABEL: and_pred_d:60; CHECK: // %bb.0:61; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b62; CHECK-NEXT: ret63 %res = and <vscale x 2 x i1> %a, %b64 ret <vscale x 2 x i1> %res65}66 67define <vscale x 4 x i1> @and_pred_s(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {68; CHECK-LABEL: and_pred_s:69; CHECK: // %bb.0:70; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b71; CHECK-NEXT: ret72 %res = and <vscale x 4 x i1> %a, %b73 ret <vscale x 4 x i1> %res74}75 76define <vscale x 8 x i1> @and_pred_h(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {77; CHECK-LABEL: and_pred_h:78; CHECK: // %bb.0:79; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b80; CHECK-NEXT: ret81 %res = and <vscale x 8 x i1> %a, %b82 ret <vscale x 8 x i1> %res83}84 85define <vscale x 16 x i1> @and_pred_b(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {86; CHECK-LABEL: and_pred_b:87; CHECK: // %bb.0:88; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b89; CHECK-NEXT: ret90 %res = and <vscale x 16 x i1> %a, %b91 ret <vscale x 16 x i1> %res92}93 94define <vscale x 2 x i64> @bic_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {95; CHECK-LABEL: bic_d:96; CHECK: // %bb.0:97; CHECK-NEXT: bic z0.d, z0.d, z1.d98; CHECK-NEXT: ret99 %not_b = xor <vscale x 2 x i64> %b, splat (i64 -1)100 %res = and <vscale x 2 x i64> %a, %not_b101 ret <vscale x 2 x i64> %res102}103 104define <vscale x 4 x i32> @bic_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {105; CHECK-LABEL: bic_s:106; CHECK: // %bb.0:107; CHECK-NEXT: bic z0.d, z0.d, z1.d108; CHECK-NEXT: ret109 %not_b = xor <vscale x 4 x i32> %b, splat (i32 -1)110 %res = and <vscale x 4 x i32> %a, %not_b111 ret <vscale x 4 x i32> %res112}113 114define <vscale x 8 x i16> @bic_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {115; CHECK-LABEL: bic_h:116; CHECK: // %bb.0:117; CHECK-NEXT: bic z0.d, z0.d, z1.d118; CHECK-NEXT: ret119 %not_b = xor <vscale x 8 x i16> %b, splat (i16 -1)120 %res = and <vscale x 8 x i16> %a, %not_b121 ret <vscale x 8 x i16> %res122}123 124define <vscale x 16 x i8> @bic_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {125; CHECK-LABEL: bic_b:126; CHECK: // %bb.0:127; CHECK-NEXT: bic z0.d, z0.d, z1.d128; CHECK-NEXT: ret129 %not_b = xor <vscale x 16 x i8> %b, splat (i8 -1)130 %res = and <vscale x 16 x i8> %a, %not_b131 ret <vscale x 16 x i8> %res132}133 134define <vscale x 1 x i1> @bic_pred_q(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {135; CHECK-LABEL: bic_pred_q:136; CHECK: // %bb.0:137; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b138; CHECK-NEXT: ret139 %not_b = xor <vscale x 1 x i1> %b, splat (i1 true)140 %res = and <vscale x 1 x i1> %a, %not_b141 ret <vscale x 1 x i1> %res142}143 144define <vscale x 2 x i1> @bic_pred_d(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {145; CHECK-LABEL: bic_pred_d:146; CHECK: // %bb.0:147; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b148; CHECK-NEXT: ret149 %not_b = xor <vscale x 2 x i1> %b, splat (i1 true)150 %res = and <vscale x 2 x i1> %a, %not_b151 ret <vscale x 2 x i1> %res152}153 154define <vscale x 4 x i1> @bic_pred_s(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {155; CHECK-LABEL: bic_pred_s:156; CHECK: // %bb.0:157; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b158; CHECK-NEXT: ret159 %not_b = xor <vscale x 4 x i1> %b, splat (i1 true)160 %res = and <vscale x 4 x i1> %a, %not_b161 ret <vscale x 4 x i1> %res162}163 164define <vscale x 8 x i1> @bic_pred_h(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {165; CHECK-LABEL: bic_pred_h:166; CHECK: // %bb.0:167; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b168; CHECK-NEXT: ret169 %not_b = xor <vscale x 8 x i1> %b, splat (i1 true)170 %res = and <vscale x 8 x i1> %a, %not_b171 ret <vscale x 8 x i1> %res172}173 174define <vscale x 16 x i1> @bic_pred_b(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {175; CHECK-LABEL: bic_pred_b:176; CHECK: // %bb.0:177; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b178; CHECK-NEXT: ret179 %not_b = xor <vscale x 16 x i1> %b, splat (i1 true)180 %res = and <vscale x 16 x i1> %a, %not_b181 ret <vscale x 16 x i1> %res182}183 184define <vscale x 2 x i64> @or_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {185; CHECK-LABEL: or_d:186; CHECK: // %bb.0:187; CHECK-NEXT: orr z0.d, z0.d, z1.d188; CHECK-NEXT: ret189 %res = or <vscale x 2 x i64> %a, %b190 ret <vscale x 2 x i64> %res191}192 193define <vscale x 4 x i32> @or_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {194; CHECK-LABEL: or_s:195; CHECK: // %bb.0:196; CHECK-NEXT: orr z0.d, z0.d, z1.d197; CHECK-NEXT: ret198 %res = or <vscale x 4 x i32> %a, %b199 ret <vscale x 4 x i32> %res200}201 202define <vscale x 8 x i16> @or_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {203; CHECK-LABEL: or_h:204; CHECK: // %bb.0:205; CHECK-NEXT: orr z0.d, z0.d, z1.d206; CHECK-NEXT: ret207 %res = or <vscale x 8 x i16> %a, %b208 ret <vscale x 8 x i16> %res209}210 211define <vscale x 16 x i8> @or_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {212; CHECK-LABEL: or_b:213; CHECK: // %bb.0:214; CHECK-NEXT: orr z0.d, z0.d, z1.d215; CHECK-NEXT: ret216 %res = or <vscale x 16 x i8> %a, %b217 ret <vscale x 16 x i8> %res218}219 220define <vscale x 16 x i8> @or_b_zero(<vscale x 16 x i8> %a) {221; CHECK-LABEL: or_b_zero:222; CHECK: // %bb.0:223; CHECK-NEXT: ret224 %res = or <vscale x 16 x i8> %a, zeroinitializer225 ret <vscale x 16 x i8> %res226}227 228define <vscale x 1 x i1> @or_pred_q(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {229; CHECK-LABEL: or_pred_q:230; CHECK: // %bb.0:231; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b232; CHECK-NEXT: ret233 %res = or <vscale x 1 x i1> %a, %b234 ret <vscale x 1 x i1> %res235}236 237define <vscale x 2 x i1> @or_pred_d(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {238; CHECK-LABEL: or_pred_d:239; CHECK: // %bb.0:240; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b241; CHECK-NEXT: ret242 %res = or <vscale x 2 x i1> %a, %b243 ret <vscale x 2 x i1> %res244}245 246define <vscale x 4 x i1> @or_pred_s(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {247; CHECK-LABEL: or_pred_s:248; CHECK: // %bb.0:249; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b250; CHECK-NEXT: ret251 %res = or <vscale x 4 x i1> %a, %b252 ret <vscale x 4 x i1> %res253}254 255define <vscale x 8 x i1> @or_pred_h(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {256; CHECK-LABEL: or_pred_h:257; CHECK: // %bb.0:258; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b259; CHECK-NEXT: ret260 %res = or <vscale x 8 x i1> %a, %b261 ret <vscale x 8 x i1> %res262}263 264define <vscale x 16 x i1> @or_pred_b(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {265; CHECK-LABEL: or_pred_b:266; CHECK: // %bb.0:267; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b268; CHECK-NEXT: ret269 %res = or <vscale x 16 x i1> %a, %b270 ret <vscale x 16 x i1> %res271}272 273define <vscale x 2 x i64> @xor_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {274; CHECK-LABEL: xor_d:275; CHECK: // %bb.0:276; CHECK-NEXT: eor z0.d, z0.d, z1.d277; CHECK-NEXT: ret278 %res = xor <vscale x 2 x i64> %a, %b279 ret <vscale x 2 x i64> %res280}281 282define <vscale x 4 x i32> @xor_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {283; CHECK-LABEL: xor_s:284; CHECK: // %bb.0:285; CHECK-NEXT: eor z0.d, z0.d, z1.d286; CHECK-NEXT: ret287 %res = xor <vscale x 4 x i32> %a, %b288 ret <vscale x 4 x i32> %res289}290 291define <vscale x 8 x i16> @xor_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {292; CHECK-LABEL: xor_h:293; CHECK: // %bb.0:294; CHECK-NEXT: eor z0.d, z0.d, z1.d295; CHECK-NEXT: ret296 %res = xor <vscale x 8 x i16> %a, %b297 ret <vscale x 8 x i16> %res298}299 300define <vscale x 16 x i8> @xor_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {301; CHECK-LABEL: xor_b:302; CHECK: // %bb.0:303; CHECK-NEXT: eor z0.d, z0.d, z1.d304; CHECK-NEXT: ret305 %res = xor <vscale x 16 x i8> %a, %b306 ret <vscale x 16 x i8> %res307}308 309define <vscale x 16 x i8> @xor_b_zero(<vscale x 16 x i8> %a) {310; CHECK-LABEL: xor_b_zero:311; CHECK: // %bb.0:312; CHECK-NEXT: ret313 %res = xor <vscale x 16 x i8> %a, zeroinitializer314 ret <vscale x 16 x i8> %res315}316 317define <vscale x 1 x i1> @xor_pred_q(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {318; CHECK-LABEL: xor_pred_q:319; CHECK: // %bb.0:320; CHECK-NEXT: ptrue p2.d321; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b322; CHECK-NEXT: ret323 %res = xor <vscale x 1 x i1> %a, %b324 ret <vscale x 1 x i1> %res325}326 327define <vscale x 2 x i1> @xor_pred_d(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {328; CHECK-LABEL: xor_pred_d:329; CHECK: // %bb.0:330; CHECK-NEXT: ptrue p2.d331; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b332; CHECK-NEXT: ret333 %res = xor <vscale x 2 x i1> %a, %b334 ret <vscale x 2 x i1> %res335}336 337define <vscale x 4 x i1> @xor_pred_s(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {338; CHECK-LABEL: xor_pred_s:339; CHECK: // %bb.0:340; CHECK-NEXT: ptrue p2.s341; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b342; CHECK-NEXT: ret343 %res = xor <vscale x 4 x i1> %a, %b344 ret <vscale x 4 x i1> %res345}346 347define <vscale x 8 x i1> @xor_pred_h(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {348; CHECK-LABEL: xor_pred_h:349; CHECK: // %bb.0:350; CHECK-NEXT: ptrue p2.h351; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b352; CHECK-NEXT: ret353 %res = xor <vscale x 8 x i1> %a, %b354 ret <vscale x 8 x i1> %res355}356 357define <vscale x 16 x i1> @xor_pred_b(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {358; CHECK-LABEL: xor_pred_b:359; CHECK: // %bb.0:360; CHECK-NEXT: ptrue p2.b361; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b362; CHECK-NEXT: ret363 %res = xor <vscale x 16 x i1> %a, %b364 ret <vscale x 16 x i1> %res365}366