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1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s2 3define <vscale x 16 x i8> @mad_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {4; CHECK-LABEL: mad_i8:5; CHECK: mad z0.b, p0/m, z1.b, z2.b 6; CHECK-NEXT: ret7 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> %pg,8 <vscale x 16 x i8> %a,9 <vscale x 16 x i8> %b,10 <vscale x 16 x i8> %c)11 ret <vscale x 16 x i8> %out12}13 14define <vscale x 8 x i16> @mad_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {15; CHECK-LABEL: mad_i16:16; CHECK: mad z0.h, p0/m, z1.h, z2.h 17; CHECK-NEXT: ret18 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1> %pg,19 <vscale x 8 x i16> %a,20 <vscale x 8 x i16> %b,21 <vscale x 8 x i16> %c)22 ret <vscale x 8 x i16> %out23}24 25define <vscale x 4 x i32> @mad_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {26; CHECK-LABEL: mad_i32:27; CHECK: mad z0.s, p0/m, z1.s, z2.s 28; CHECK-NEXT: ret29 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> %pg,30 <vscale x 4 x i32> %a,31 <vscale x 4 x i32> %b,32 <vscale x 4 x i32> %c)33 ret <vscale x 4 x i32> %out34}35 36define <vscale x 2 x i64> @mad_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {37; CHECK-LABEL: mad_i64:38; CHECK: mad z0.d, p0/m, z1.d, z2.d 39; CHECK-NEXT: ret40 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1> %pg,41 <vscale x 2 x i64> %a,42 <vscale x 2 x i64> %b,43 <vscale x 2 x i64> %c)44 ret <vscale x 2 x i64> %out45}46 47define <vscale x 16 x i8> @msb_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {48; CHECK-LABEL: msb_i8:49; CHECK: msb z0.b, p0/m, z1.b, z2.b 50; CHECK-NEXT: ret51 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.msb.nxv16i8(<vscale x 16 x i1> %pg,52 <vscale x 16 x i8> %a,53 <vscale x 16 x i8> %b,54 <vscale x 16 x i8> %c)55 ret <vscale x 16 x i8> %out56}57 58define <vscale x 8 x i16> @msb_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {59; CHECK-LABEL: msb_i16:60; CHECK: msb z0.h, p0/m, z1.h, z2.h 61; CHECK-NEXT: ret62 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.msb.nxv8i16(<vscale x 8 x i1> %pg,63 <vscale x 8 x i16> %a,64 <vscale x 8 x i16> %b,65 <vscale x 8 x i16> %c)66 ret <vscale x 8 x i16> %out67}68 69define <vscale x 4 x i32> @msb_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {70; CHECK-LABEL: msb_i32:71; CHECK: msb z0.s, p0/m, z1.s, z2.s 72; CHECK-NEXT: ret73 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.msb.nxv4i32(<vscale x 4 x i1> %pg,74 <vscale x 4 x i32> %a,75 <vscale x 4 x i32> %b,76 <vscale x 4 x i32> %c)77 ret <vscale x 4 x i32> %out78}79 80define <vscale x 2 x i64> @msb_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {81; CHECK-LABEL: msb_i64:82; CHECK: msb z0.d, p0/m, z1.d, z2.d 83; CHECK-NEXT: ret84 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.msb.nxv2i64(<vscale x 2 x i1> %pg,85 <vscale x 2 x i64> %a,86 <vscale x 2 x i64> %b,87 <vscale x 2 x i64> %c)88 ret <vscale x 2 x i64> %out89}90 91 92define <vscale x 16 x i8> @mla_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {93; CHECK-LABEL: mla_i8:94; CHECK: mla z0.b, p0/m, z1.b, z2.b 95; CHECK-NEXT: ret96 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.mla.nxv16i8(<vscale x 16 x i1> %pg,97 <vscale x 16 x i8> %a,98 <vscale x 16 x i8> %b,99 <vscale x 16 x i8> %c)100 ret <vscale x 16 x i8> %out101}102 103define <vscale x 8 x i16> @mla_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {104; CHECK-LABEL: mla_i16:105; CHECK: mla z0.h, p0/m, z1.h, z2.h 106; CHECK-NEXT: ret107 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.mla.nxv8i16(<vscale x 8 x i1> %pg,108 <vscale x 8 x i16> %a,109 <vscale x 8 x i16> %b,110 <vscale x 8 x i16> %c)111 ret <vscale x 8 x i16> %out112}113 114define <vscale x 4 x i32> @mla_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {115; CHECK-LABEL: mla_i32:116; CHECK: mla z0.s, p0/m, z1.s, z2.s 117; CHECK-NEXT: ret118 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.nxv4i32(<vscale x 4 x i1> %pg,119 <vscale x 4 x i32> %a,120 <vscale x 4 x i32> %b,121 <vscale x 4 x i32> %c)122 ret <vscale x 4 x i32> %out123}124 125define <vscale x 2 x i64> @mla_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {126; CHECK-LABEL: mla_i64:127; CHECK: mla z0.d, p0/m, z1.d, z2.d 128; CHECK-NEXT: ret129 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.mla.nxv2i64(<vscale x 2 x i1> %pg,130 <vscale x 2 x i64> %a,131 <vscale x 2 x i64> %b,132 <vscale x 2 x i64> %c)133 ret <vscale x 2 x i64> %out134}135 136 137define <vscale x 16 x i8> @mls_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {138; CHECK-LABEL: mls_i8:139; CHECK: mls z0.b, p0/m, z1.b, z2.b 140; CHECK-NEXT: ret141 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.mls.nxv16i8(<vscale x 16 x i1> %pg,142 <vscale x 16 x i8> %a,143 <vscale x 16 x i8> %b,144 <vscale x 16 x i8> %c)145 ret <vscale x 16 x i8> %out146}147 148define <vscale x 8 x i16> @mls_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {149; CHECK-LABEL: mls_i16:150; CHECK: mls z0.h, p0/m, z1.h, z2.h 151; CHECK-NEXT: ret152 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.mls.nxv8i16(<vscale x 8 x i1> %pg,153 <vscale x 8 x i16> %a,154 <vscale x 8 x i16> %b,155 <vscale x 8 x i16> %c)156 ret <vscale x 8 x i16> %out157}158 159define <vscale x 4 x i32> @mls_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {160; CHECK-LABEL: mls_i32:161; CHECK: mls z0.s, p0/m, z1.s, z2.s 162; CHECK-NEXT: ret163 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mls.nxv4i32(<vscale x 4 x i1> %pg,164 <vscale x 4 x i32> %a,165 <vscale x 4 x i32> %b,166 <vscale x 4 x i32> %c)167 ret <vscale x 4 x i32> %out168}169 170define <vscale x 2 x i64> @mls_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {171; CHECK-LABEL: mls_i64:172; CHECK: mls z0.d, p0/m, z1.d, z2.d 173; CHECK-NEXT: ret174 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.mls.nxv2i64(<vscale x 2 x i1> %pg,175 <vscale x 2 x i64> %a,176 <vscale x 2 x i64> %b,177 <vscale x 2 x i64> %c)178 ret <vscale x 2 x i64> %out179}180 181declare <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>)182declare <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>)183declare <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>)184declare <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>)185 186declare <vscale x 16 x i8> @llvm.aarch64.sve.msb.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>)187declare <vscale x 8 x i16> @llvm.aarch64.sve.msb.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>)188declare <vscale x 4 x i32> @llvm.aarch64.sve.msb.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>)189declare <vscale x 2 x i64> @llvm.aarch64.sve.msb.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>)190 191declare <vscale x 16 x i8> @llvm.aarch64.sve.mla.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>)192declare <vscale x 8 x i16> @llvm.aarch64.sve.mla.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>)193declare <vscale x 4 x i32> @llvm.aarch64.sve.mla.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>)194declare <vscale x 2 x i64> @llvm.aarch64.sve.mla.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>)195 196declare <vscale x 16 x i8> @llvm.aarch64.sve.mls.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>)197declare <vscale x 8 x i16> @llvm.aarch64.sve.mls.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>)198declare <vscale x 4 x i32> @llvm.aarch64.sve.mls.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>)199declare <vscale x 2 x i64> @llvm.aarch64.sve.mls.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>)200