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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -verify-machineinstrs -mattr=+sve < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6; Muls with (-1) as operand should fold to neg.7define <vscale x 16 x i8> @mul_neg_fold_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {8; CHECK-LABEL: mul_neg_fold_i8:9; CHECK: // %bb.0:10; CHECK-NEXT: neg z0.b, p0/m, z0.b11; CHECK-NEXT: ret12 %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 -1))13 ret <vscale x 16 x i8> %114}15 16define <vscale x 8 x i16> @mul_neg_fold_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {17; CHECK-LABEL: mul_neg_fold_i16:18; CHECK: // %bb.0:19; CHECK-NEXT: neg z0.h, p0/m, z0.h20; CHECK-NEXT: ret21 %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.mul.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 -1))22 ret <vscale x 8 x i16> %123}24 25define <vscale x 4 x i32> @mul_neg_fold_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {26; CHECK-LABEL: mul_neg_fold_i32:27; CHECK: // %bb.0:28; CHECK-NEXT: neg z0.s, p0/m, z0.s29; CHECK-NEXT: ret30 %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 -1))31 ret <vscale x 4 x i32> %132}33 34define <vscale x 2 x i64> @mul_neg_fold_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {35; CHECK-LABEL: mul_neg_fold_i64:36; CHECK: // %bb.0:37; CHECK-NEXT: neg z0.d, p0/m, z0.d38; CHECK-NEXT: ret39 %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.mul.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 -1))40 ret <vscale x 2 x i64> %141}42 43define <vscale x 16 x i8> @mul_neg_fold_u_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {44; CHECK-LABEL: mul_neg_fold_u_i8:45; CHECK: // %bb.0:46; CHECK-NEXT: neg z0.b, p0/m, z0.b47; CHECK-NEXT: ret48 %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 -1))49 ret <vscale x 16 x i8> %150}51 52define <vscale x 8 x i16> @mul_neg_fold_u_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {53; CHECK-LABEL: mul_neg_fold_u_i16:54; CHECK: // %bb.0:55; CHECK-NEXT: neg z0.h, p0/m, z0.h56; CHECK-NEXT: ret57 %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.mul.u.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 -1))58 ret <vscale x 8 x i16> %159}60 61define <vscale x 4 x i32> @mul_neg_fold_u_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {62; CHECK-LABEL: mul_neg_fold_u_i32:63; CHECK: // %bb.0:64; CHECK-NEXT: neg z0.s, p0/m, z0.s65; CHECK-NEXT: ret66 %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 -1))67 ret <vscale x 4 x i32> %168}69 70define <vscale x 2 x i64> @mul_neg_fold_u_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {71; CHECK-LABEL: mul_neg_fold_u_i64:72; CHECK: // %bb.0:73; CHECK-NEXT: neg z0.d, p0/m, z0.d74; CHECK-NEXT: ret75 %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.mul.u.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 -1))76 ret <vscale x 2 x i64> %177}78 79define <vscale x 16 x i8> @mul_neg_fold_different_argument_order_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {80; CHECK-LABEL: mul_neg_fold_different_argument_order_i8:81; CHECK: // %bb.0:82; CHECK-NEXT: mov z1.b, #-1 // =0xffffffffffffffff83; CHECK-NEXT: neg z1.b, p0/m, z0.b84; CHECK-NEXT: mov z0.d, z1.d85; CHECK-NEXT: ret86 %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat(i8 -1), <vscale x 16 x i8> %a)87 ret <vscale x 16 x i8> %188}89 90define <vscale x 8 x i16> @mul_neg_fold_different_argument_order_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {91; CHECK-LABEL: mul_neg_fold_different_argument_order_i16:92; CHECK: // %bb.0:93; CHECK-NEXT: mov z1.h, #-1 // =0xffffffffffffffff94; CHECK-NEXT: neg z1.h, p0/m, z0.h95; CHECK-NEXT: mov z0.d, z1.d96; CHECK-NEXT: ret97 %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.mul.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> splat(i16 -1), <vscale x 8 x i16> %a)98 ret <vscale x 8 x i16> %199}100 101define <vscale x 4 x i32> @mul_neg_fold_different_argument_order_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {102; CHECK-LABEL: mul_neg_fold_different_argument_order_i32:103; CHECK: // %bb.0:104; CHECK-NEXT: mov z1.s, #-1 // =0xffffffffffffffff105; CHECK-NEXT: neg z1.s, p0/m, z0.s106; CHECK-NEXT: mov z0.d, z1.d107; CHECK-NEXT: ret108 %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat(i32 -1), <vscale x 4 x i32> %a)109 ret <vscale x 4 x i32> %1110}111 112define <vscale x 2 x i64> @mul_neg_fold_different_argument_order_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {113; CHECK-LABEL: mul_neg_fold_different_argument_order_i64:114; CHECK: // %bb.0:115; CHECK-NEXT: mov z1.d, #-1 // =0xffffffffffffffff116; CHECK-NEXT: neg z1.d, p0/m, z0.d117; CHECK-NEXT: mov z0.d, z1.d118; CHECK-NEXT: ret119 %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.mul.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> splat(i64 -1), <vscale x 2 x i64> %a)120 ret <vscale x 2 x i64> %1121}122 123declare <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)124declare <vscale x 8 x i16> @llvm.aarch64.sve.mul.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)125declare <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)126declare <vscale x 2 x i64> @llvm.aarch64.sve.mul.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)127 128declare <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)129declare <vscale x 8 x i16> @llvm.aarch64.sve.mul.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)130declare <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)131declare <vscale x 2 x i64> @llvm.aarch64.sve.mul.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)132