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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s3 4;5; SMULH6;7 8define <vscale x 16 x i8> @smulh_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {9; CHECK-LABEL: smulh_i8:10; CHECK: // %bb.0:11; CHECK-NEXT: ptrue p0.b12; CHECK-NEXT: smulh z0.b, p0/m, z0.b, z1.b13; CHECK-NEXT: ret14 %1 = sext <vscale x 16 x i8> %a to <vscale x 16 x i16>15 %2 = sext <vscale x 16 x i8> %b to <vscale x 16 x i16>16 %mul = mul <vscale x 16 x i16> %1, %217 %shr = lshr <vscale x 16 x i16> %mul, splat(i16 8)18 %tr = trunc <vscale x 16 x i16> %shr to <vscale x 16 x i8>19 ret <vscale x 16 x i8> %tr20}21 22define <vscale x 8 x i16> @smulh_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {23; CHECK-LABEL: smulh_i16:24; CHECK: // %bb.0:25; CHECK-NEXT: ptrue p0.h26; CHECK-NEXT: smulh z0.h, p0/m, z0.h, z1.h27; CHECK-NEXT: ret28 %1 = sext <vscale x 8 x i16> %a to <vscale x 8 x i32>29 %2 = sext <vscale x 8 x i16> %b to <vscale x 8 x i32>30 %mul = mul <vscale x 8 x i32> %1, %231 %shr = lshr <vscale x 8 x i32> %mul, splat(i32 16)32 %tr = trunc <vscale x 8 x i32> %shr to <vscale x 8 x i16>33 ret <vscale x 8 x i16> %tr34}35 36define <vscale x 4 x i32> @smulh_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {37; CHECK-LABEL: smulh_i32:38; CHECK: // %bb.0:39; CHECK-NEXT: ptrue p0.s40; CHECK-NEXT: smulh z0.s, p0/m, z0.s, z1.s41; CHECK-NEXT: ret42 %1 = sext <vscale x 4 x i32> %a to <vscale x 4 x i64>43 %2 = sext <vscale x 4 x i32> %b to <vscale x 4 x i64>44 %mul = mul <vscale x 4 x i64> %1, %245 %shr = lshr <vscale x 4 x i64> %mul, splat(i64 32)46 %tr = trunc <vscale x 4 x i64> %shr to <vscale x 4 x i32>47 ret <vscale x 4 x i32> %tr48}49 50define <vscale x 2 x i64> @smulh_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {51; CHECK-LABEL: smulh_i64:52; CHECK: // %bb.0:53; CHECK-NEXT: ptrue p0.d54; CHECK-NEXT: smulh z0.d, p0/m, z0.d, z1.d55; CHECK-NEXT: ret56 %1 = sext <vscale x 2 x i64> %a to <vscale x 2 x i128>57 %2 = sext <vscale x 2 x i64> %b to <vscale x 2 x i128>58 %mul = mul <vscale x 2 x i128> %1, %259 %shr = lshr <vscale x 2 x i128> %mul, splat(i128 64)60 %tr = trunc <vscale x 2 x i128> %shr to <vscale x 2 x i64>61 ret <vscale x 2 x i64> %tr62}63 64;65; UMULH66;67 68define <vscale x 16 x i8> @umulh_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {69; CHECK-LABEL: umulh_i8:70; CHECK: // %bb.0:71; CHECK-NEXT: ptrue p0.b72; CHECK-NEXT: umulh z0.b, p0/m, z0.b, z1.b73; CHECK-NEXT: ret74 %1 = zext <vscale x 16 x i8> %a to <vscale x 16 x i16>75 %2 = zext <vscale x 16 x i8> %b to <vscale x 16 x i16>76 %mul = mul <vscale x 16 x i16> %1, %277 %shr = lshr <vscale x 16 x i16> %mul, splat(i16 8)78 %tr = trunc <vscale x 16 x i16> %shr to <vscale x 16 x i8>79 ret <vscale x 16 x i8> %tr80}81 82define <vscale x 8 x i16> @umulh_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {83; CHECK-LABEL: umulh_i16:84; CHECK: // %bb.0:85; CHECK-NEXT: ptrue p0.h86; CHECK-NEXT: umulh z0.h, p0/m, z0.h, z1.h87; CHECK-NEXT: ret88 %1 = zext <vscale x 8 x i16> %a to <vscale x 8 x i32>89 %2 = zext <vscale x 8 x i16> %b to <vscale x 8 x i32>90 %mul = mul <vscale x 8 x i32> %1, %291 %shr = lshr <vscale x 8 x i32> %mul, splat(i32 16)92 %tr = trunc <vscale x 8 x i32> %shr to <vscale x 8 x i16>93 ret <vscale x 8 x i16> %tr94}95 96define <vscale x 4 x i32> @umulh_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {97; CHECK-LABEL: umulh_i32:98; CHECK: // %bb.0:99; CHECK-NEXT: ptrue p0.s100; CHECK-NEXT: umulh z0.s, p0/m, z0.s, z1.s101; CHECK-NEXT: ret102 %1 = zext <vscale x 4 x i32> %a to <vscale x 4 x i64>103 %2 = zext <vscale x 4 x i32> %b to <vscale x 4 x i64>104 %mul = mul <vscale x 4 x i64> %1, %2105 %shr = lshr <vscale x 4 x i64> %mul, splat(i64 32)106 %tr = trunc <vscale x 4 x i64> %shr to <vscale x 4 x i32>107 ret <vscale x 4 x i32> %tr108}109 110define <vscale x 2 x i64> @umulh_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {111; CHECK-LABEL: umulh_i64:112; CHECK: // %bb.0:113; CHECK-NEXT: ptrue p0.d114; CHECK-NEXT: umulh z0.d, p0/m, z0.d, z1.d115; CHECK-NEXT: ret116 %1 = zext <vscale x 2 x i64> %a to <vscale x 2 x i128>117 %2 = zext <vscale x 2 x i64> %b to <vscale x 2 x i128>118 %mul = mul <vscale x 2 x i128> %1, %2119 %shr = lshr <vscale x 2 x i128> %mul, splat(i128 64)120 %tr = trunc <vscale x 2 x i128> %shr to <vscale x 2 x i64>121 ret <vscale x 2 x i64> %tr122}123 124attributes #0 = { "target-features"="+sve" }125