451 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4; ANDV5 6define i1 @reduce_and_nxv16i1(<vscale x 16 x i1> %vec) {7; CHECK-LABEL: reduce_and_nxv16i1:8; CHECK: // %bb.0:9; CHECK-NEXT: ptrue p1.b10; CHECK-NEXT: nots p0.b, p1/z, p0.b11; CHECK-NEXT: cset w0, eq12; CHECK-NEXT: ret13 %res = call i1 @llvm.vector.reduce.and.i1.nxv16i1(<vscale x 16 x i1> %vec)14 ret i1 %res15}16 17define i1 @reduce_and_nxv8i1(<vscale x 8 x i1> %vec) {18; CHECK-LABEL: reduce_and_nxv8i1:19; CHECK: // %bb.0:20; CHECK-NEXT: ptrue p1.h21; CHECK-NEXT: nots p0.b, p1/z, p0.b22; CHECK-NEXT: cset w0, eq23; CHECK-NEXT: ret24 %res = call i1 @llvm.vector.reduce.and.i1.nxv8i1(<vscale x 8 x i1> %vec)25 ret i1 %res26}27 28define i1 @reduce_and_nxv4i1(<vscale x 4 x i1> %vec) {29; CHECK-LABEL: reduce_and_nxv4i1:30; CHECK: // %bb.0:31; CHECK-NEXT: ptrue p1.s32; CHECK-NEXT: nots p0.b, p1/z, p0.b33; CHECK-NEXT: cset w0, eq34; CHECK-NEXT: ret35 %res = call i1 @llvm.vector.reduce.and.i1.nxv4i1(<vscale x 4 x i1> %vec)36 ret i1 %res37}38 39define i1 @reduce_and_nxv2i1(<vscale x 2 x i1> %vec) {40; CHECK-LABEL: reduce_and_nxv2i1:41; CHECK: // %bb.0:42; CHECK-NEXT: ptrue p1.d43; CHECK-NEXT: nots p0.b, p1/z, p0.b44; CHECK-NEXT: cset w0, eq45; CHECK-NEXT: ret46 %res = call i1 @llvm.vector.reduce.and.i1.nxv2i1(<vscale x 2 x i1> %vec)47 ret i1 %res48}49 50define i1 @reduce_and_nxv1i1(<vscale x 1 x i1> %vec) {51; CHECK-LABEL: reduce_and_nxv1i1:52; CHECK: // %bb.0:53; CHECK-NEXT: ptrue p1.d54; CHECK-NEXT: punpklo p2.h, p1.b55; CHECK-NEXT: eor p0.b, p1/z, p0.b, p2.b56; CHECK-NEXT: ptest p2, p0.b57; CHECK-NEXT: cset w0, eq58; CHECK-NEXT: ret59 %res = call i1 @llvm.vector.reduce.and.i1.nxv1i1(<vscale x 1 x i1> %vec)60 ret i1 %res61}62 63; ORV64 65define i1 @reduce_or_nxv16i1(<vscale x 16 x i1> %vec) {66; CHECK-LABEL: reduce_or_nxv16i1:67; CHECK: // %bb.0:68; CHECK-NEXT: ptest p0, p0.b69; CHECK-NEXT: cset w0, ne70; CHECK-NEXT: ret71 %res = call i1 @llvm.vector.reduce.or.i1.nxv16i1(<vscale x 16 x i1> %vec)72 ret i1 %res73}74 75define i1 @reduce_or_nxv8i1(<vscale x 8 x i1> %vec) {76; CHECK-LABEL: reduce_or_nxv8i1:77; CHECK: // %bb.0:78; CHECK-NEXT: ptrue p1.h79; CHECK-NEXT: ptest p1, p0.b80; CHECK-NEXT: cset w0, ne81; CHECK-NEXT: ret82 %res = call i1 @llvm.vector.reduce.or.i1.nxv8i1(<vscale x 8 x i1> %vec)83 ret i1 %res84}85 86define i1 @reduce_or_nxv4i1(<vscale x 4 x i1> %vec) {87; CHECK-LABEL: reduce_or_nxv4i1:88; CHECK: // %bb.0:89; CHECK-NEXT: ptrue p1.s90; CHECK-NEXT: ptest p1, p0.b91; CHECK-NEXT: cset w0, ne92; CHECK-NEXT: ret93 %res = call i1 @llvm.vector.reduce.or.i1.nxv4i1(<vscale x 4 x i1> %vec)94 ret i1 %res95}96 97define i1 @reduce_or_nxv2i1(<vscale x 2 x i1> %vec) {98; CHECK-LABEL: reduce_or_nxv2i1:99; CHECK: // %bb.0:100; CHECK-NEXT: ptrue p1.d101; CHECK-NEXT: ptest p1, p0.b102; CHECK-NEXT: cset w0, ne103; CHECK-NEXT: ret104 %res = call i1 @llvm.vector.reduce.or.i1.nxv2i1(<vscale x 2 x i1> %vec)105 ret i1 %res106}107 108define i1 @reduce_or_nxv1i1(<vscale x 1 x i1> %vec) {109; CHECK-LABEL: reduce_or_nxv1i1:110; CHECK: // %bb.0:111; CHECK-NEXT: ptrue p1.d112; CHECK-NEXT: punpklo p1.h, p1.b113; CHECK-NEXT: ptest p1, p0.b114; CHECK-NEXT: cset w0, ne115; CHECK-NEXT: ret116 %res = call i1 @llvm.vector.reduce.or.i1.nxv1i1(<vscale x 1 x i1> %vec)117 ret i1 %res118}119 120; XORV121 122define i1 @reduce_xor_nxv16i1(<vscale x 16 x i1> %vec) {123; CHECK-LABEL: reduce_xor_nxv16i1:124; CHECK: // %bb.0:125; CHECK-NEXT: ptrue p1.b126; CHECK-NEXT: cntp x8, p1, p0.b127; CHECK-NEXT: and w0, w8, #0x1128; CHECK-NEXT: ret129 %res = call i1 @llvm.vector.reduce.xor.i1.nxv16i1(<vscale x 16 x i1> %vec)130 ret i1 %res131}132 133define i1 @reduce_xor_nxv8i1(<vscale x 8 x i1> %vec) {134; CHECK-LABEL: reduce_xor_nxv8i1:135; CHECK: // %bb.0:136; CHECK-NEXT: ptrue p1.h137; CHECK-NEXT: cntp x8, p1, p0.h138; CHECK-NEXT: and w0, w8, #0x1139; CHECK-NEXT: ret140 %res = call i1 @llvm.vector.reduce.xor.i1.nxv8i1(<vscale x 8 x i1> %vec)141 ret i1 %res142}143 144define i1 @reduce_xor_nxv4i1(<vscale x 4 x i1> %vec) {145; CHECK-LABEL: reduce_xor_nxv4i1:146; CHECK: // %bb.0:147; CHECK-NEXT: ptrue p1.s148; CHECK-NEXT: cntp x8, p1, p0.s149; CHECK-NEXT: and w0, w8, #0x1150; CHECK-NEXT: ret151 %res = call i1 @llvm.vector.reduce.xor.i1.nxv4i1(<vscale x 4 x i1> %vec)152 ret i1 %res153}154 155define i1 @reduce_xor_nxv2i1(<vscale x 2 x i1> %vec) {156; CHECK-LABEL: reduce_xor_nxv2i1:157; CHECK: // %bb.0:158; CHECK-NEXT: ptrue p1.d159; CHECK-NEXT: cntp x8, p1, p0.d160; CHECK-NEXT: and w0, w8, #0x1161; CHECK-NEXT: ret162 %res = call i1 @llvm.vector.reduce.xor.i1.nxv2i1(<vscale x 2 x i1> %vec)163 ret i1 %res164}165 166define i1 @reduce_xor_nxv1i1(<vscale x 1 x i1> %vec) {167; CHECK-LABEL: reduce_xor_nxv1i1:168; CHECK: // %bb.0:169; CHECK-NEXT: ptrue p1.d170; CHECK-NEXT: punpklo p1.h, p1.b171; CHECK-NEXT: cntp x8, p1, p0.d172; CHECK-NEXT: and w0, w8, #0x1173; CHECK-NEXT: ret174 %res = call i1 @llvm.vector.reduce.xor.i1.nxv1i1(<vscale x 1 x i1> %vec)175 ret i1 %res176}177 178; SMAXV179 180define i1 @reduce_smax_nxv16i1(<vscale x 16 x i1> %vec) {181; CHECK-LABEL: reduce_smax_nxv16i1:182; CHECK: // %bb.0:183; CHECK-NEXT: ptrue p1.b184; CHECK-NEXT: nots p0.b, p1/z, p0.b185; CHECK-NEXT: cset w0, eq186; CHECK-NEXT: ret187 %res = call i1 @llvm.vector.reduce.smax.i1.nxv16i1(<vscale x 16 x i1> %vec)188 ret i1 %res189}190 191define i1 @reduce_smax_nxv8i1(<vscale x 8 x i1> %vec) {192; CHECK-LABEL: reduce_smax_nxv8i1:193; CHECK: // %bb.0:194; CHECK-NEXT: ptrue p1.h195; CHECK-NEXT: nots p0.b, p1/z, p0.b196; CHECK-NEXT: cset w0, eq197; CHECK-NEXT: ret198 %res = call i1 @llvm.vector.reduce.smax.i1.nxv8i1(<vscale x 8 x i1> %vec)199 ret i1 %res200}201 202define i1 @reduce_smax_nxv4i1(<vscale x 4 x i1> %vec) {203; CHECK-LABEL: reduce_smax_nxv4i1:204; CHECK: // %bb.0:205; CHECK-NEXT: ptrue p1.s206; CHECK-NEXT: nots p0.b, p1/z, p0.b207; CHECK-NEXT: cset w0, eq208; CHECK-NEXT: ret209 %res = call i1 @llvm.vector.reduce.smax.i1.nxv4i1(<vscale x 4 x i1> %vec)210 ret i1 %res211}212 213define i1 @reduce_smax_nxv2i1(<vscale x 2 x i1> %vec) {214; CHECK-LABEL: reduce_smax_nxv2i1:215; CHECK: // %bb.0:216; CHECK-NEXT: ptrue p1.d217; CHECK-NEXT: nots p0.b, p1/z, p0.b218; CHECK-NEXT: cset w0, eq219; CHECK-NEXT: ret220 %res = call i1 @llvm.vector.reduce.smax.i1.nxv2i1(<vscale x 2 x i1> %vec)221 ret i1 %res222}223 224define i1 @reduce_smax_nxv1i1(<vscale x 1 x i1> %vec) {225; CHECK-LABEL: reduce_smax_nxv1i1:226; CHECK: // %bb.0:227; CHECK-NEXT: ptrue p1.d228; CHECK-NEXT: punpklo p2.h, p1.b229; CHECK-NEXT: eor p0.b, p1/z, p0.b, p2.b230; CHECK-NEXT: ptest p2, p0.b231; CHECK-NEXT: cset w0, eq232; CHECK-NEXT: ret233 %res = call i1 @llvm.vector.reduce.smax.i1.nxv1i1(<vscale x 1 x i1> %vec)234 ret i1 %res235}236 237; SMINV238 239define i1 @reduce_smin_nxv16i1(<vscale x 16 x i1> %vec) {240; CHECK-LABEL: reduce_smin_nxv16i1:241; CHECK: // %bb.0:242; CHECK-NEXT: ptest p0, p0.b243; CHECK-NEXT: cset w0, ne244; CHECK-NEXT: ret245 %res = call i1 @llvm.vector.reduce.smin.i1.nxv16i1(<vscale x 16 x i1> %vec)246 ret i1 %res247}248 249define i1 @reduce_smin_nxv8i1(<vscale x 8 x i1> %vec) {250; CHECK-LABEL: reduce_smin_nxv8i1:251; CHECK: // %bb.0:252; CHECK-NEXT: ptrue p1.h253; CHECK-NEXT: ptest p1, p0.b254; CHECK-NEXT: cset w0, ne255; CHECK-NEXT: ret256 %res = call i1 @llvm.vector.reduce.smin.i1.nxv8i1(<vscale x 8 x i1> %vec)257 ret i1 %res258}259 260define i1 @reduce_smin_nxv4i1(<vscale x 4 x i1> %vec) {261; CHECK-LABEL: reduce_smin_nxv4i1:262; CHECK: // %bb.0:263; CHECK-NEXT: ptrue p1.s264; CHECK-NEXT: ptest p1, p0.b265; CHECK-NEXT: cset w0, ne266; CHECK-NEXT: ret267 %res = call i1 @llvm.vector.reduce.smin.i1.nxv4i1(<vscale x 4 x i1> %vec)268 ret i1 %res269}270 271define i1 @reduce_smin_nxv2i1(<vscale x 2 x i1> %vec) {272; CHECK-LABEL: reduce_smin_nxv2i1:273; CHECK: // %bb.0:274; CHECK-NEXT: ptrue p1.d275; CHECK-NEXT: ptest p1, p0.b276; CHECK-NEXT: cset w0, ne277; CHECK-NEXT: ret278 %res = call i1 @llvm.vector.reduce.smin.i1.nxv2i1(<vscale x 2 x i1> %vec)279 ret i1 %res280}281 282define i1 @reduce_smin_nxv1i1(<vscale x 1 x i1> %vec) {283; CHECK-LABEL: reduce_smin_nxv1i1:284; CHECK: // %bb.0:285; CHECK-NEXT: ptrue p1.d286; CHECK-NEXT: punpklo p1.h, p1.b287; CHECK-NEXT: ptest p1, p0.b288; CHECK-NEXT: cset w0, ne289; CHECK-NEXT: ret290 %res = call i1 @llvm.vector.reduce.smin.i1.nxv1i1(<vscale x 1 x i1> %vec)291 ret i1 %res292}293 294; UMAXV295 296define i1 @reduce_umax_nxv16i1(<vscale x 16 x i1> %vec) {297; CHECK-LABEL: reduce_umax_nxv16i1:298; CHECK: // %bb.0:299; CHECK-NEXT: ptest p0, p0.b300; CHECK-NEXT: cset w0, ne301; CHECK-NEXT: ret302 %res = call i1 @llvm.vector.reduce.umax.i1.nxv16i1(<vscale x 16 x i1> %vec)303 ret i1 %res304}305 306define i1 @reduce_umax_nxv8i1(<vscale x 8 x i1> %vec) {307; CHECK-LABEL: reduce_umax_nxv8i1:308; CHECK: // %bb.0:309; CHECK-NEXT: ptrue p1.h310; CHECK-NEXT: ptest p1, p0.b311; CHECK-NEXT: cset w0, ne312; CHECK-NEXT: ret313 %res = call i1 @llvm.vector.reduce.umax.i1.nxv8i1(<vscale x 8 x i1> %vec)314 ret i1 %res315}316 317define i1 @reduce_umax_nxv4i1(<vscale x 4 x i1> %vec) {318; CHECK-LABEL: reduce_umax_nxv4i1:319; CHECK: // %bb.0:320; CHECK-NEXT: ptrue p1.s321; CHECK-NEXT: ptest p1, p0.b322; CHECK-NEXT: cset w0, ne323; CHECK-NEXT: ret324 %res = call i1 @llvm.vector.reduce.umax.i1.nxv4i1(<vscale x 4 x i1> %vec)325 ret i1 %res326}327 328define i1 @reduce_umax_nxv2i1(<vscale x 2 x i1> %vec) {329; CHECK-LABEL: reduce_umax_nxv2i1:330; CHECK: // %bb.0:331; CHECK-NEXT: ptrue p1.d332; CHECK-NEXT: ptest p1, p0.b333; CHECK-NEXT: cset w0, ne334; CHECK-NEXT: ret335 %res = call i1 @llvm.vector.reduce.umax.i1.nxv2i1(<vscale x 2 x i1> %vec)336 ret i1 %res337}338 339define i1 @reduce_umax_nxv1i1(<vscale x 1 x i1> %vec) {340; CHECK-LABEL: reduce_umax_nxv1i1:341; CHECK: // %bb.0:342; CHECK-NEXT: ptrue p1.d343; CHECK-NEXT: punpklo p1.h, p1.b344; CHECK-NEXT: ptest p1, p0.b345; CHECK-NEXT: cset w0, ne346; CHECK-NEXT: ret347 %res = call i1 @llvm.vector.reduce.umax.i1.nxv1i1(<vscale x 1 x i1> %vec)348 ret i1 %res349}350 351; UMINV352 353define i1 @reduce_umin_nxv16i1(<vscale x 16 x i1> %vec) {354; CHECK-LABEL: reduce_umin_nxv16i1:355; CHECK: // %bb.0:356; CHECK-NEXT: ptrue p1.b357; CHECK-NEXT: nots p0.b, p1/z, p0.b358; CHECK-NEXT: cset w0, eq359; CHECK-NEXT: ret360 %res = call i1 @llvm.vector.reduce.umin.i1.nxv16i1(<vscale x 16 x i1> %vec)361 ret i1 %res362}363 364define i1 @reduce_umin_nxv8i1(<vscale x 8 x i1> %vec) {365; CHECK-LABEL: reduce_umin_nxv8i1:366; CHECK: // %bb.0:367; CHECK-NEXT: ptrue p1.h368; CHECK-NEXT: nots p0.b, p1/z, p0.b369; CHECK-NEXT: cset w0, eq370; CHECK-NEXT: ret371 %res = call i1 @llvm.vector.reduce.umin.i1.nxv8i1(<vscale x 8 x i1> %vec)372 ret i1 %res373}374 375define i1 @reduce_umin_nxv4i1(<vscale x 4 x i1> %vec) {376; CHECK-LABEL: reduce_umin_nxv4i1:377; CHECK: // %bb.0:378; CHECK-NEXT: ptrue p1.s379; CHECK-NEXT: nots p0.b, p1/z, p0.b380; CHECK-NEXT: cset w0, eq381; CHECK-NEXT: ret382 %res = call i1 @llvm.vector.reduce.umin.i1.nxv4i1(<vscale x 4 x i1> %vec)383 ret i1 %res384}385 386define i1 @reduce_umin_nxv1i1(<vscale x 1 x i1> %vec) {387; CHECK-LABEL: reduce_umin_nxv1i1:388; CHECK: // %bb.0:389; CHECK-NEXT: ptrue p1.d390; CHECK-NEXT: punpklo p2.h, p1.b391; CHECK-NEXT: eor p0.b, p1/z, p0.b, p2.b392; CHECK-NEXT: ptest p2, p0.b393; CHECK-NEXT: cset w0, eq394; CHECK-NEXT: ret395 %res = call i1 @llvm.vector.reduce.umin.i1.nxv1i1(<vscale x 1 x i1> %vec)396 ret i1 %res397}398 399define i1 @reduce_umin_nxv2i1(<vscale x 2 x i1> %vec) {400; CHECK-LABEL: reduce_umin_nxv2i1:401; CHECK: // %bb.0:402; CHECK-NEXT: ptrue p1.d403; CHECK-NEXT: nots p0.b, p1/z, p0.b404; CHECK-NEXT: cset w0, eq405; CHECK-NEXT: ret406 %res = call i1 @llvm.vector.reduce.umin.i1.nxv2i1(<vscale x 2 x i1> %vec)407 ret i1 %res408}409 410declare i1 @llvm.vector.reduce.and.i1.nxv16i1(<vscale x 16 x i1> %vec)411declare i1 @llvm.vector.reduce.and.i1.nxv8i1(<vscale x 8 x i1> %vec)412declare i1 @llvm.vector.reduce.and.i1.nxv4i1(<vscale x 4 x i1> %vec)413declare i1 @llvm.vector.reduce.and.i1.nxv2i1(<vscale x 2 x i1> %vec)414declare i1 @llvm.vector.reduce.and.i1.nxv1i1(<vscale x 1 x i1> %vec)415 416declare i1 @llvm.vector.reduce.or.i1.nxv16i1(<vscale x 16 x i1> %vec)417declare i1 @llvm.vector.reduce.or.i1.nxv8i1(<vscale x 8 x i1> %vec)418declare i1 @llvm.vector.reduce.or.i1.nxv4i1(<vscale x 4 x i1> %vec)419declare i1 @llvm.vector.reduce.or.i1.nxv2i1(<vscale x 2 x i1> %vec)420declare i1 @llvm.vector.reduce.or.i1.nxv1i1(<vscale x 1 x i1> %vec)421 422declare i1 @llvm.vector.reduce.xor.i1.nxv16i1(<vscale x 16 x i1> %vec)423declare i1 @llvm.vector.reduce.xor.i1.nxv8i1(<vscale x 8 x i1> %vec)424declare i1 @llvm.vector.reduce.xor.i1.nxv4i1(<vscale x 4 x i1> %vec)425declare i1 @llvm.vector.reduce.xor.i1.nxv2i1(<vscale x 2 x i1> %vec)426declare i1 @llvm.vector.reduce.xor.i1.nxv1i1(<vscale x 1 x i1> %vec)427 428declare i1 @llvm.vector.reduce.smin.i1.nxv16i1(<vscale x 16 x i1> %vec)429declare i1 @llvm.vector.reduce.smin.i1.nxv8i1(<vscale x 8 x i1> %vec)430declare i1 @llvm.vector.reduce.smin.i1.nxv4i1(<vscale x 4 x i1> %vec)431declare i1 @llvm.vector.reduce.smin.i1.nxv2i1(<vscale x 2 x i1> %vec)432declare i1 @llvm.vector.reduce.smin.i1.nxv1i1(<vscale x 1 x i1> %vec)433 434declare i1 @llvm.vector.reduce.smax.i1.nxv16i1(<vscale x 16 x i1> %vec)435declare i1 @llvm.vector.reduce.smax.i1.nxv8i1(<vscale x 8 x i1> %vec)436declare i1 @llvm.vector.reduce.smax.i1.nxv4i1(<vscale x 4 x i1> %vec)437declare i1 @llvm.vector.reduce.smax.i1.nxv2i1(<vscale x 2 x i1> %vec)438declare i1 @llvm.vector.reduce.smax.i1.nxv1i1(<vscale x 1 x i1> %vec)439 440declare i1 @llvm.vector.reduce.umin.i1.nxv16i1(<vscale x 16 x i1> %vec)441declare i1 @llvm.vector.reduce.umin.i1.nxv8i1(<vscale x 8 x i1> %vec)442declare i1 @llvm.vector.reduce.umin.i1.nxv4i1(<vscale x 4 x i1> %vec)443declare i1 @llvm.vector.reduce.umin.i1.nxv2i1(<vscale x 2 x i1> %vec)444declare i1 @llvm.vector.reduce.umin.i1.nxv1i1(<vscale x 1 x i1> %vec)445 446declare i1 @llvm.vector.reduce.umax.i1.nxv16i1(<vscale x 16 x i1> %vec)447declare i1 @llvm.vector.reduce.umax.i1.nxv8i1(<vscale x 8 x i1> %vec)448declare i1 @llvm.vector.reduce.umax.i1.nxv4i1(<vscale x 4 x i1> %vec)449declare i1 @llvm.vector.reduce.umax.i1.nxv2i1(<vscale x 2 x i1> %vec)450declare i1 @llvm.vector.reduce.umax.i1.nxv1i1(<vscale x 1 x i1> %vec)451