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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4; ANDV5 6define i8 @andv_nxv16i8(<vscale x 16 x i8> %a) {7; CHECK-LABEL: andv_nxv16i8:8; CHECK: // %bb.0:9; CHECK-NEXT: ptrue p0.b10; CHECK-NEXT: andv b0, p0, z0.b11; CHECK-NEXT: fmov w0, s012; CHECK-NEXT: ret13 %res = call i8 @llvm.vector.reduce.and.nxv16i8(<vscale x 16 x i8> %a)14 ret i8 %res15}16 17define i16 @andv_nxv8i16(<vscale x 8 x i16> %a) {18; CHECK-LABEL: andv_nxv8i16:19; CHECK: // %bb.0:20; CHECK-NEXT: ptrue p0.h21; CHECK-NEXT: andv h0, p0, z0.h22; CHECK-NEXT: fmov w0, s023; CHECK-NEXT: ret24 %res = call i16 @llvm.vector.reduce.and.nxv8i16(<vscale x 8 x i16> %a)25 ret i16 %res26}27 28define i32 @andv_nxv4i32(<vscale x 4 x i32> %a) {29; CHECK-LABEL: andv_nxv4i32:30; CHECK: // %bb.0:31; CHECK-NEXT: ptrue p0.s32; CHECK-NEXT: andv s0, p0, z0.s33; CHECK-NEXT: fmov w0, s034; CHECK-NEXT: ret35 %res = call i32 @llvm.vector.reduce.and.nxv4i32(<vscale x 4 x i32> %a)36 ret i32 %res37}38 39define i64 @andv_nxv2i64(<vscale x 2 x i64> %a) {40; CHECK-LABEL: andv_nxv2i64:41; CHECK: // %bb.0:42; CHECK-NEXT: ptrue p0.d43; CHECK-NEXT: andv d0, p0, z0.d44; CHECK-NEXT: fmov x0, d045; CHECK-NEXT: ret46 %res = call i64 @llvm.vector.reduce.and.nxv2i64(<vscale x 2 x i64> %a)47 ret i64 %res48}49 50; ORV51 52define i8 @orv_nxv16i8(<vscale x 16 x i8> %a) {53; CHECK-LABEL: orv_nxv16i8:54; CHECK: // %bb.0:55; CHECK-NEXT: ptrue p0.b56; CHECK-NEXT: orv b0, p0, z0.b57; CHECK-NEXT: fmov w0, s058; CHECK-NEXT: ret59 %res = call i8 @llvm.vector.reduce.or.nxv16i8(<vscale x 16 x i8> %a)60 ret i8 %res61}62 63define i16 @orv_nxv8i16(<vscale x 8 x i16> %a) {64; CHECK-LABEL: orv_nxv8i16:65; CHECK: // %bb.0:66; CHECK-NEXT: ptrue p0.h67; CHECK-NEXT: orv h0, p0, z0.h68; CHECK-NEXT: fmov w0, s069; CHECK-NEXT: ret70 %res = call i16 @llvm.vector.reduce.or.nxv8i16(<vscale x 8 x i16> %a)71 ret i16 %res72}73 74define i32 @orv_nxv4i32(<vscale x 4 x i32> %a) {75; CHECK-LABEL: orv_nxv4i32:76; CHECK: // %bb.0:77; CHECK-NEXT: ptrue p0.s78; CHECK-NEXT: orv s0, p0, z0.s79; CHECK-NEXT: fmov w0, s080; CHECK-NEXT: ret81 %res = call i32 @llvm.vector.reduce.or.nxv4i32(<vscale x 4 x i32> %a)82 ret i32 %res83}84 85define i64 @orv_nxv2i64(<vscale x 2 x i64> %a) {86; CHECK-LABEL: orv_nxv2i64:87; CHECK: // %bb.0:88; CHECK-NEXT: ptrue p0.d89; CHECK-NEXT: orv d0, p0, z0.d90; CHECK-NEXT: fmov x0, d091; CHECK-NEXT: ret92 %res = call i64 @llvm.vector.reduce.or.nxv2i64(<vscale x 2 x i64> %a)93 ret i64 %res94}95 96; XORV97 98define i8 @xorv_nxv16i8(<vscale x 16 x i8> %a) {99; CHECK-LABEL: xorv_nxv16i8:100; CHECK: // %bb.0:101; CHECK-NEXT: ptrue p0.b102; CHECK-NEXT: eorv b0, p0, z0.b103; CHECK-NEXT: fmov w0, s0104; CHECK-NEXT: ret105 %res = call i8 @llvm.vector.reduce.xor.nxv16i8(<vscale x 16 x i8> %a)106 ret i8 %res107}108 109define i16 @xorv_nxv8i16(<vscale x 8 x i16> %a) {110; CHECK-LABEL: xorv_nxv8i16:111; CHECK: // %bb.0:112; CHECK-NEXT: ptrue p0.h113; CHECK-NEXT: eorv h0, p0, z0.h114; CHECK-NEXT: fmov w0, s0115; CHECK-NEXT: ret116 %res = call i16 @llvm.vector.reduce.xor.nxv8i16(<vscale x 8 x i16> %a)117 ret i16 %res118}119 120define i32 @xorv_nxv4i32(<vscale x 4 x i32> %a) {121; CHECK-LABEL: xorv_nxv4i32:122; CHECK: // %bb.0:123; CHECK-NEXT: ptrue p0.s124; CHECK-NEXT: eorv s0, p0, z0.s125; CHECK-NEXT: fmov w0, s0126; CHECK-NEXT: ret127 %res = call i32 @llvm.vector.reduce.xor.nxv4i32(<vscale x 4 x i32> %a)128 ret i32 %res129}130 131define i64 @xorv_nxv2i64(<vscale x 2 x i64> %a) {132; CHECK-LABEL: xorv_nxv2i64:133; CHECK: // %bb.0:134; CHECK-NEXT: ptrue p0.d135; CHECK-NEXT: eorv d0, p0, z0.d136; CHECK-NEXT: fmov x0, d0137; CHECK-NEXT: ret138 %res = call i64 @llvm.vector.reduce.xor.nxv2i64(<vscale x 2 x i64> %a)139 ret i64 %res140}141 142; UADDV143 144define i8 @uaddv_nxv16i8(<vscale x 16 x i8> %a) {145; CHECK-LABEL: uaddv_nxv16i8:146; CHECK: // %bb.0:147; CHECK-NEXT: ptrue p0.b148; CHECK-NEXT: uaddv d0, p0, z0.b149; CHECK-NEXT: fmov w0, s0150; CHECK-NEXT: ret151 %res = call i8 @llvm.vector.reduce.add.nxv16i8(<vscale x 16 x i8> %a)152 ret i8 %res153}154 155define i16 @uaddv_nxv8i16(<vscale x 8 x i16> %a) {156; CHECK-LABEL: uaddv_nxv8i16:157; CHECK: // %bb.0:158; CHECK-NEXT: ptrue p0.h159; CHECK-NEXT: uaddv d0, p0, z0.h160; CHECK-NEXT: fmov w0, s0161; CHECK-NEXT: ret162 %res = call i16 @llvm.vector.reduce.add.nxv8i16(<vscale x 8 x i16> %a)163 ret i16 %res164}165 166define i32 @uaddv_nxv4i32(<vscale x 4 x i32> %a) {167; CHECK-LABEL: uaddv_nxv4i32:168; CHECK: // %bb.0:169; CHECK-NEXT: ptrue p0.s170; CHECK-NEXT: uaddv d0, p0, z0.s171; CHECK-NEXT: fmov w0, s0172; CHECK-NEXT: ret173 %res = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %a)174 ret i32 %res175}176 177define i64 @uaddv_nxv2i64(<vscale x 2 x i64> %a) {178; CHECK-LABEL: uaddv_nxv2i64:179; CHECK: // %bb.0:180; CHECK-NEXT: ptrue p0.d181; CHECK-NEXT: uaddv d0, p0, z0.d182; CHECK-NEXT: fmov x0, d0183; CHECK-NEXT: ret184 %res = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> %a)185 ret i64 %res186}187 188; UMINV189 190define i8 @umin_nxv16i8(<vscale x 16 x i8> %a) {191; CHECK-LABEL: umin_nxv16i8:192; CHECK: // %bb.0:193; CHECK-NEXT: ptrue p0.b194; CHECK-NEXT: uminv b0, p0, z0.b195; CHECK-NEXT: fmov w0, s0196; CHECK-NEXT: ret197 %res = call i8 @llvm.vector.reduce.umin.nxv16i8(<vscale x 16 x i8> %a)198 ret i8 %res199}200 201define i16 @umin_nxv8i16(<vscale x 8 x i16> %a) {202; CHECK-LABEL: umin_nxv8i16:203; CHECK: // %bb.0:204; CHECK-NEXT: ptrue p0.h205; CHECK-NEXT: uminv h0, p0, z0.h206; CHECK-NEXT: fmov w0, s0207; CHECK-NEXT: ret208 %res = call i16 @llvm.vector.reduce.umin.nxv8i16(<vscale x 8 x i16> %a)209 ret i16 %res210}211 212define i32 @umin_nxv4i32(<vscale x 4 x i32> %a) {213; CHECK-LABEL: umin_nxv4i32:214; CHECK: // %bb.0:215; CHECK-NEXT: ptrue p0.s216; CHECK-NEXT: uminv s0, p0, z0.s217; CHECK-NEXT: fmov w0, s0218; CHECK-NEXT: ret219 %res = call i32 @llvm.vector.reduce.umin.nxv4i32(<vscale x 4 x i32> %a)220 ret i32 %res221}222 223define i64 @umin_nxv2i64(<vscale x 2 x i64> %a) {224; CHECK-LABEL: umin_nxv2i64:225; CHECK: // %bb.0:226; CHECK-NEXT: ptrue p0.d227; CHECK-NEXT: uminv d0, p0, z0.d228; CHECK-NEXT: fmov x0, d0229; CHECK-NEXT: ret230 %res = call i64 @llvm.vector.reduce.umin.nxv2i64(<vscale x 2 x i64> %a)231 ret i64 %res232}233 234; SMINV235 236define i8 @smin_nxv16i8(<vscale x 16 x i8> %a) {237; CHECK-LABEL: smin_nxv16i8:238; CHECK: // %bb.0:239; CHECK-NEXT: ptrue p0.b240; CHECK-NEXT: sminv b0, p0, z0.b241; CHECK-NEXT: fmov w0, s0242; CHECK-NEXT: ret243 %res = call i8 @llvm.vector.reduce.smin.nxv16i8(<vscale x 16 x i8> %a)244 ret i8 %res245}246 247define i16 @smin_nxv8i16(<vscale x 8 x i16> %a) {248; CHECK-LABEL: smin_nxv8i16:249; CHECK: // %bb.0:250; CHECK-NEXT: ptrue p0.h251; CHECK-NEXT: sminv h0, p0, z0.h252; CHECK-NEXT: fmov w0, s0253; CHECK-NEXT: ret254 %res = call i16 @llvm.vector.reduce.smin.nxv8i16(<vscale x 8 x i16> %a)255 ret i16 %res256}257 258define i32 @smin_nxv4i32(<vscale x 4 x i32> %a) {259; CHECK-LABEL: smin_nxv4i32:260; CHECK: // %bb.0:261; CHECK-NEXT: ptrue p0.s262; CHECK-NEXT: sminv s0, p0, z0.s263; CHECK-NEXT: fmov w0, s0264; CHECK-NEXT: ret265 %res = call i32 @llvm.vector.reduce.smin.nxv4i32(<vscale x 4 x i32> %a)266 ret i32 %res267}268 269define i64 @smin_nxv2i64(<vscale x 2 x i64> %a) {270; CHECK-LABEL: smin_nxv2i64:271; CHECK: // %bb.0:272; CHECK-NEXT: ptrue p0.d273; CHECK-NEXT: sminv d0, p0, z0.d274; CHECK-NEXT: fmov x0, d0275; CHECK-NEXT: ret276 %res = call i64 @llvm.vector.reduce.smin.nxv2i64(<vscale x 2 x i64> %a)277 ret i64 %res278}279 280; UMAXV281 282define i8 @umax_nxv16i8(<vscale x 16 x i8> %a) {283; CHECK-LABEL: umax_nxv16i8:284; CHECK: // %bb.0:285; CHECK-NEXT: ptrue p0.b286; CHECK-NEXT: umaxv b0, p0, z0.b287; CHECK-NEXT: fmov w0, s0288; CHECK-NEXT: ret289 %res = call i8 @llvm.vector.reduce.umax.nxv16i8(<vscale x 16 x i8> %a)290 ret i8 %res291}292 293define i16 @umax_nxv8i16(<vscale x 8 x i16> %a) {294; CHECK-LABEL: umax_nxv8i16:295; CHECK: // %bb.0:296; CHECK-NEXT: ptrue p0.h297; CHECK-NEXT: umaxv h0, p0, z0.h298; CHECK-NEXT: fmov w0, s0299; CHECK-NEXT: ret300 %res = call i16 @llvm.vector.reduce.umax.nxv8i16(<vscale x 8 x i16> %a)301 ret i16 %res302}303 304define i32 @umax_nxv4i32(<vscale x 4 x i32> %a) {305; CHECK-LABEL: umax_nxv4i32:306; CHECK: // %bb.0:307; CHECK-NEXT: ptrue p0.s308; CHECK-NEXT: umaxv s0, p0, z0.s309; CHECK-NEXT: fmov w0, s0310; CHECK-NEXT: ret311 %res = call i32 @llvm.vector.reduce.umax.nxv4i32(<vscale x 4 x i32> %a)312 ret i32 %res313}314 315define i64 @umax_nxv2i64(<vscale x 2 x i64> %a) {316; CHECK-LABEL: umax_nxv2i64:317; CHECK: // %bb.0:318; CHECK-NEXT: ptrue p0.d319; CHECK-NEXT: umaxv d0, p0, z0.d320; CHECK-NEXT: fmov x0, d0321; CHECK-NEXT: ret322 %res = call i64 @llvm.vector.reduce.umax.nxv2i64(<vscale x 2 x i64> %a)323 ret i64 %res324}325 326; SMAXV327 328define i8 @smax_nxv16i8(<vscale x 16 x i8> %a) {329; CHECK-LABEL: smax_nxv16i8:330; CHECK: // %bb.0:331; CHECK-NEXT: ptrue p0.b332; CHECK-NEXT: smaxv b0, p0, z0.b333; CHECK-NEXT: fmov w0, s0334; CHECK-NEXT: ret335 %res = call i8 @llvm.vector.reduce.smax.nxv16i8(<vscale x 16 x i8> %a)336 ret i8 %res337}338 339define i16 @smax_nxv8i16(<vscale x 8 x i16> %a) {340; CHECK-LABEL: smax_nxv8i16:341; CHECK: // %bb.0:342; CHECK-NEXT: ptrue p0.h343; CHECK-NEXT: smaxv h0, p0, z0.h344; CHECK-NEXT: fmov w0, s0345; CHECK-NEXT: ret346 %res = call i16 @llvm.vector.reduce.smax.nxv8i16(<vscale x 8 x i16> %a)347 ret i16 %res348}349 350define i32 @smax_nxv4i32(<vscale x 4 x i32> %a) {351; CHECK-LABEL: smax_nxv4i32:352; CHECK: // %bb.0:353; CHECK-NEXT: ptrue p0.s354; CHECK-NEXT: smaxv s0, p0, z0.s355; CHECK-NEXT: fmov w0, s0356; CHECK-NEXT: ret357 %res = call i32 @llvm.vector.reduce.smax.nxv4i32(<vscale x 4 x i32> %a)358 ret i32 %res359}360 361define i64 @smax_nxv2i64(<vscale x 2 x i64> %a) {362; CHECK-LABEL: smax_nxv2i64:363; CHECK: // %bb.0:364; CHECK-NEXT: ptrue p0.d365; CHECK-NEXT: smaxv d0, p0, z0.d366; CHECK-NEXT: fmov x0, d0367; CHECK-NEXT: ret368 %res = call i64 @llvm.vector.reduce.smax.nxv2i64(<vscale x 2 x i64> %a)369 ret i64 %res370}371 372; No MULV instruction so use knowledge about the architectural maximum size of373; an SVE register to "scalarise" the reduction.374 375define i8 @mulv_nxv16i8(<vscale x 16 x i8> %a) {376; CHECK-LABEL: mulv_nxv16i8:377; CHECK: // %bb.0:378; CHECK-NEXT: mov z1.b, #1 // =0x1379; CHECK-NEXT: ptrue p0.b380; CHECK-NEXT: uzp2 z2.b, z0.b, z1.b381; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b382; CHECK-NEXT: mul z0.b, p0/m, z0.b, z2.b383; CHECK-NEXT: uzp2 z2.b, z0.b, z1.b384; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b385; CHECK-NEXT: mul z0.b, p0/m, z0.b, z2.b386; CHECK-NEXT: uzp2 z2.b, z0.b, z1.b387; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b388; CHECK-NEXT: mul z0.b, p0/m, z0.b, z2.b389; CHECK-NEXT: uzp2 z2.b, z0.b, z1.b390; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b391; CHECK-NEXT: mul z0.b, p0/m, z0.b, z2.b392; CHECK-NEXT: uzp2 z2.b, z0.b, z1.b393; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b394; CHECK-NEXT: mul z0.b, p0/m, z0.b, z2.b395; CHECK-NEXT: uzp2 z2.b, z0.b, z1.b396; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b397; CHECK-NEXT: mul z0.b, p0/m, z0.b, z2.b398; CHECK-NEXT: uzp2 z2.b, z0.b, z1.b399; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b400; CHECK-NEXT: mul z0.b, p0/m, z0.b, z2.b401; CHECK-NEXT: uzp2 z2.b, z0.b, z1.b402; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b403; CHECK-NEXT: mul z0.b, p0/m, z0.b, z2.b404; CHECK-NEXT: fmov w0, s0405; CHECK-NEXT: ret406 %res = call i8 @llvm.vector.reduce.mul.nxv16i8(<vscale x 16 x i8> %a)407 ret i8 %res408}409 410define i16 @mulv_nxv8i16(<vscale x 8 x i16> %a) {411; CHECK-LABEL: mulv_nxv8i16:412; CHECK: // %bb.0:413; CHECK-NEXT: mov z1.h, #1 // =0x1414; CHECK-NEXT: ptrue p0.h415; CHECK-NEXT: uzp2 z2.h, z0.h, z1.h416; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h417; CHECK-NEXT: mul z0.h, p0/m, z0.h, z2.h418; CHECK-NEXT: uzp2 z2.h, z0.h, z1.h419; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h420; CHECK-NEXT: mul z0.h, p0/m, z0.h, z2.h421; CHECK-NEXT: uzp2 z2.h, z0.h, z1.h422; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h423; CHECK-NEXT: mul z0.h, p0/m, z0.h, z2.h424; CHECK-NEXT: uzp2 z2.h, z0.h, z1.h425; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h426; CHECK-NEXT: mul z0.h, p0/m, z0.h, z2.h427; CHECK-NEXT: uzp2 z2.h, z0.h, z1.h428; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h429; CHECK-NEXT: mul z0.h, p0/m, z0.h, z2.h430; CHECK-NEXT: uzp2 z2.h, z0.h, z1.h431; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h432; CHECK-NEXT: mul z0.h, p0/m, z0.h, z2.h433; CHECK-NEXT: uzp2 z2.h, z0.h, z1.h434; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h435; CHECK-NEXT: mul z0.h, p0/m, z0.h, z2.h436; CHECK-NEXT: fmov w0, s0437; CHECK-NEXT: ret438 %res = call i16 @llvm.vector.reduce.mul.nxv8i16(<vscale x 8 x i16> %a)439 ret i16 %res440}441 442define i32 @mulv_nxv4i32(<vscale x 4 x i32> %a) {443; CHECK-LABEL: mulv_nxv4i32:444; CHECK: // %bb.0:445; CHECK-NEXT: mov z1.s, #1 // =0x1446; CHECK-NEXT: ptrue p0.s447; CHECK-NEXT: uzp2 z2.s, z0.s, z1.s448; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s449; CHECK-NEXT: mul z0.s, p0/m, z0.s, z2.s450; CHECK-NEXT: uzp2 z2.s, z0.s, z1.s451; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s452; CHECK-NEXT: mul z0.s, p0/m, z0.s, z2.s453; CHECK-NEXT: uzp2 z2.s, z0.s, z1.s454; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s455; CHECK-NEXT: mul z0.s, p0/m, z0.s, z2.s456; CHECK-NEXT: uzp2 z2.s, z0.s, z1.s457; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s458; CHECK-NEXT: mul z0.s, p0/m, z0.s, z2.s459; CHECK-NEXT: uzp2 z2.s, z0.s, z1.s460; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s461; CHECK-NEXT: mul z0.s, p0/m, z0.s, z2.s462; CHECK-NEXT: uzp2 z2.s, z0.s, z1.s463; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s464; CHECK-NEXT: mul z0.s, p0/m, z0.s, z2.s465; CHECK-NEXT: fmov w0, s0466; CHECK-NEXT: ret467 %res = call i32 @llvm.vector.reduce.mul.nxv4i32(<vscale x 4 x i32> %a)468 ret i32 %res469}470 471define i64 @mulv_nxv2i64(<vscale x 2 x i64> %a) {472; CHECK-LABEL: mulv_nxv2i64:473; CHECK: // %bb.0:474; CHECK-NEXT: mov z1.d, #1 // =0x1475; CHECK-NEXT: ptrue p0.d476; CHECK-NEXT: uzp2 z2.d, z0.d, z1.d477; CHECK-NEXT: uzp1 z0.d, z0.d, z1.d478; CHECK-NEXT: mul z0.d, p0/m, z0.d, z2.d479; CHECK-NEXT: uzp2 z2.d, z0.d, z1.d480; CHECK-NEXT: uzp1 z0.d, z0.d, z1.d481; CHECK-NEXT: mul z0.d, p0/m, z0.d, z2.d482; CHECK-NEXT: uzp2 z2.d, z0.d, z1.d483; CHECK-NEXT: uzp1 z0.d, z0.d, z1.d484; CHECK-NEXT: mul z0.d, p0/m, z0.d, z2.d485; CHECK-NEXT: uzp2 z2.d, z0.d, z1.d486; CHECK-NEXT: uzp1 z0.d, z0.d, z1.d487; CHECK-NEXT: mul z0.d, p0/m, z0.d, z2.d488; CHECK-NEXT: uzp2 z2.d, z0.d, z1.d489; CHECK-NEXT: uzp1 z0.d, z0.d, z1.d490; CHECK-NEXT: mul z0.d, p0/m, z0.d, z2.d491; CHECK-NEXT: fmov x0, d0492; CHECK-NEXT: ret493 %res = call i64 @llvm.vector.reduce.mul.nxv2i64(<vscale x 2 x i64> %a)494 ret i64 %res495}496 497; Test widen vector reduce type498declare i8 @llvm.vector.reduce.smin.nxv10i8(<vscale x 10 x i8>)499 500define i8 @smin_nxv10i8(<vscale x 10 x i8> %a) {501; CHECK-LABEL: smin_nxv10i8:502; CHECK: // %bb.0:503; CHECK-NEXT: uunpkhi z1.h, z0.b504; CHECK-NEXT: mov z3.d, #127 // =0x7f505; CHECK-NEXT: uunpklo z0.h, z0.b506; CHECK-NEXT: ptrue p0.b507; CHECK-NEXT: uunpklo z2.s, z1.h508; CHECK-NEXT: uunpkhi z1.s, z1.h509; CHECK-NEXT: uunpklo z2.d, z2.s510; CHECK-NEXT: uzp1 z2.s, z2.s, z3.s511; CHECK-NEXT: uzp1 z1.h, z2.h, z1.h512; CHECK-NEXT: uzp1 z1.b, z0.b, z1.b513; CHECK-NEXT: uunpkhi z1.h, z1.b514; CHECK-NEXT: uunpkhi z2.s, z1.h515; CHECK-NEXT: uunpklo z1.s, z1.h516; CHECK-NEXT: uunpkhi z2.d, z2.s517; CHECK-NEXT: uzp1 z2.s, z3.s, z2.s518; CHECK-NEXT: uzp1 z1.h, z1.h, z2.h519; CHECK-NEXT: uzp1 z1.b, z0.b, z1.b520; CHECK-NEXT: uunpkhi z1.h, z1.b521; CHECK-NEXT: uunpkhi z2.s, z1.h522; CHECK-NEXT: uunpklo z1.s, z1.h523; CHECK-NEXT: uunpklo z2.d, z2.s524; CHECK-NEXT: uzp1 z2.s, z2.s, z3.s525; CHECK-NEXT: uzp1 z1.h, z1.h, z2.h526; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b527; CHECK-NEXT: sminv b0, p0, z0.b528; CHECK-NEXT: fmov w0, s0529; CHECK-NEXT: ret530 %res = call i8 @llvm.vector.reduce.smin.nxv10i8(<vscale x 10 x i8> %a)531 ret i8 %res532}533 534declare i8 @llvm.vector.reduce.add.nxv12i8(<vscale x 12 x i8>)535 536define i8 @uaddv_nxv12i8(<vscale x 12 x i8> %a) {537; CHECK-LABEL: uaddv_nxv12i8:538; CHECK: // %bb.0:539; CHECK-NEXT: uunpkhi z2.h, z0.b540; CHECK-NEXT: movi v1.2d, #0000000000000000541; CHECK-NEXT: uunpklo z0.h, z0.b542; CHECK-NEXT: ptrue p0.b543; CHECK-NEXT: uunpklo z2.s, z2.h544; CHECK-NEXT: uzp1 z1.h, z2.h, z1.h545; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b546; CHECK-NEXT: uaddv d0, p0, z0.b547; CHECK-NEXT: fmov w0, s0548; CHECK-NEXT: ret549 %res = call i8 @llvm.vector.reduce.add.nxv12i8(<vscale x 12 x i8> %a)550 ret i8 %res551}552 553declare i8 @llvm.vector.reduce.umax.nxv14i8(<vscale x 14 x i8>)554 555define i8 @umax_nxv14i8(<vscale x 14 x i8> %a) {556; CHECK-LABEL: umax_nxv14i8:557; CHECK: // %bb.0:558; CHECK-NEXT: uunpkhi z2.h, z0.b559; CHECK-NEXT: movi v1.2d, #0000000000000000560; CHECK-NEXT: uunpklo z0.h, z0.b561; CHECK-NEXT: ptrue p0.b562; CHECK-NEXT: uunpkhi z3.s, z2.h563; CHECK-NEXT: uunpklo z2.s, z2.h564; CHECK-NEXT: uunpklo z3.d, z3.s565; CHECK-NEXT: uzp1 z1.s, z3.s, z1.s566; CHECK-NEXT: uzp1 z1.h, z2.h, z1.h567; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b568; CHECK-NEXT: umaxv b0, p0, z0.b569; CHECK-NEXT: fmov w0, s0570; CHECK-NEXT: ret571 %res = call i8 @llvm.vector.reduce.umax.nxv14i8(<vscale x 14 x i8> %a)572 ret i8 %res573}574 575declare i8 @llvm.vector.reduce.and.nxv16i8(<vscale x 16 x i8>)576declare i16 @llvm.vector.reduce.and.nxv8i16(<vscale x 8 x i16>)577declare i32 @llvm.vector.reduce.and.nxv4i32(<vscale x 4 x i32>)578declare i64 @llvm.vector.reduce.and.nxv2i64(<vscale x 2 x i64>)579 580declare i8 @llvm.vector.reduce.or.nxv16i8(<vscale x 16 x i8>)581declare i16 @llvm.vector.reduce.or.nxv8i16(<vscale x 8 x i16>)582declare i32 @llvm.vector.reduce.or.nxv4i32(<vscale x 4 x i32>)583declare i64 @llvm.vector.reduce.or.nxv2i64(<vscale x 2 x i64>)584 585declare i8 @llvm.vector.reduce.xor.nxv16i8(<vscale x 16 x i8>)586declare i16 @llvm.vector.reduce.xor.nxv8i16(<vscale x 8 x i16>)587declare i32 @llvm.vector.reduce.xor.nxv4i32(<vscale x 4 x i32>)588declare i64 @llvm.vector.reduce.xor.nxv2i64(<vscale x 2 x i64>)589 590declare i8 @llvm.vector.reduce.add.nxv16i8(<vscale x 16 x i8>)591declare i16 @llvm.vector.reduce.add.nxv8i16(<vscale x 8 x i16>)592declare i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32>)593declare i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64>)594 595declare i8 @llvm.vector.reduce.umin.nxv16i8(<vscale x 16 x i8>)596declare i16 @llvm.vector.reduce.umin.nxv8i16(<vscale x 8 x i16>)597declare i32 @llvm.vector.reduce.umin.nxv4i32(<vscale x 4 x i32>)598declare i64 @llvm.vector.reduce.umin.nxv2i64(<vscale x 2 x i64>)599 600declare i8 @llvm.vector.reduce.smin.nxv16i8(<vscale x 16 x i8>)601declare i16 @llvm.vector.reduce.smin.nxv8i16(<vscale x 8 x i16>)602declare i32 @llvm.vector.reduce.smin.nxv4i32(<vscale x 4 x i32>)603declare i64 @llvm.vector.reduce.smin.nxv2i64(<vscale x 2 x i64>)604 605declare i8 @llvm.vector.reduce.umax.nxv16i8(<vscale x 16 x i8>)606declare i16 @llvm.vector.reduce.umax.nxv8i16(<vscale x 8 x i16>)607declare i32 @llvm.vector.reduce.umax.nxv4i32(<vscale x 4 x i32>)608declare i64 @llvm.vector.reduce.umax.nxv2i64(<vscale x 2 x i64>)609 610declare i8 @llvm.vector.reduce.smax.nxv16i8(<vscale x 16 x i8>)611declare i16 @llvm.vector.reduce.smax.nxv8i16(<vscale x 8 x i16>)612declare i32 @llvm.vector.reduce.smax.nxv4i32(<vscale x 4 x i32>)613declare i64 @llvm.vector.reduce.smax.nxv2i64(<vscale x 2 x i64>)614