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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4;5; ADRB6;7 8define <vscale x 4 x i32> @adrb_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {9; CHECK-LABEL: adrb_i32:10; CHECK: // %bb.0:11; CHECK-NEXT: adr z0.s, [z0.s, z1.s]12; CHECK-NEXT: ret13 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.adrb.nxv4i32(<vscale x 4 x i32> %a,14 <vscale x 4 x i32> %b)15 ret <vscale x 4 x i32> %out16}17 18define <vscale x 2 x i64> @adrb_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {19; CHECK-LABEL: adrb_i64:20; CHECK: // %bb.0:21; CHECK-NEXT: adr z0.d, [z0.d, z1.d]22; CHECK-NEXT: ret23 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.adrb.nxv2i64(<vscale x 2 x i64> %a,24 <vscale x 2 x i64> %b)25 ret <vscale x 2 x i64> %out26}27 28;29; ADRH30;31 32define <vscale x 4 x i32> @adrh_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {33; CHECK-LABEL: adrh_i32:34; CHECK: // %bb.0:35; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #1]36; CHECK-NEXT: ret37 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.adrh.nxv4i32(<vscale x 4 x i32> %a,38 <vscale x 4 x i32> %b)39 ret <vscale x 4 x i32> %out40}41 42define <vscale x 2 x i64> @adrh_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {43; CHECK-LABEL: adrh_i64:44; CHECK: // %bb.0:45; CHECK-NEXT: adr z0.d, [z0.d, z1.d, lsl #1]46; CHECK-NEXT: ret47 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.adrh.nxv2i64(<vscale x 2 x i64> %a,48 <vscale x 2 x i64> %b)49 ret <vscale x 2 x i64> %out50}51 52;53; ADRW54;55 56define <vscale x 4 x i32> @adrw_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {57; CHECK-LABEL: adrw_i32:58; CHECK: // %bb.0:59; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #2]60; CHECK-NEXT: ret61 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.adrw.nxv4i32(<vscale x 4 x i32> %a,62 <vscale x 4 x i32> %b)63 ret <vscale x 4 x i32> %out64}65 66define <vscale x 2 x i64> @adrw_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {67; CHECK-LABEL: adrw_i64:68; CHECK: // %bb.0:69; CHECK-NEXT: adr z0.d, [z0.d, z1.d, lsl #2]70; CHECK-NEXT: ret71 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.adrw.nxv2i64(<vscale x 2 x i64> %a,72 <vscale x 2 x i64> %b)73 ret <vscale x 2 x i64> %out74}75 76;77; ADRD78;79 80define <vscale x 4 x i32> @adrd_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {81; CHECK-LABEL: adrd_i32:82; CHECK: // %bb.0:83; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #3]84; CHECK-NEXT: ret85 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32> %a,86 <vscale x 4 x i32> %b)87 ret <vscale x 4 x i32> %out88}89 90define <vscale x 2 x i64> @adrd_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {91; CHECK-LABEL: adrd_i64:92; CHECK: // %bb.0:93; CHECK-NEXT: adr z0.d, [z0.d, z1.d, lsl #3]94; CHECK-NEXT: ret95 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64> %a,96 <vscale x 2 x i64> %b)97 ret <vscale x 2 x i64> %out98}99 100declare <vscale x 4 x i32> @llvm.aarch64.sve.adrb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)101declare <vscale x 2 x i64> @llvm.aarch64.sve.adrb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)102 103declare <vscale x 4 x i32> @llvm.aarch64.sve.adrh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)104declare <vscale x 2 x i64> @llvm.aarch64.sve.adrh.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)105 106declare <vscale x 4 x i32> @llvm.aarch64.sve.adrw.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)107declare <vscale x 2 x i64> @llvm.aarch64.sve.adrw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)108 109declare <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)110declare <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)111