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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4;5; Unpredicated dup instruction (which is an alias for mov):6; * register + register,7; * register + immediate8;9 10define <vscale x 16 x i8> @dup_i8(i8 %b) {11; CHECK-LABEL: dup_i8:12; CHECK: // %bb.0:13; CHECK-NEXT: mov z0.b, w014; CHECK-NEXT: ret15 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %b)16 ret <vscale x 16 x i8> %out17}18 19define <vscale x 16 x i8> @dup_imm_i8() {20; CHECK-LABEL: dup_imm_i8:21; CHECK: // %bb.0:22; CHECK-NEXT: mov z0.b, #16 // =0x1023; CHECK-NEXT: ret24 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 16)25 ret <vscale x 16 x i8> %out26}27 28define <vscale x 8 x i16> @dup_i16(i16 %b) {29; CHECK-LABEL: dup_i16:30; CHECK: // %bb.0:31; CHECK-NEXT: mov z0.h, w032; CHECK-NEXT: ret33 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %b)34 ret <vscale x 8 x i16> %out35}36 37define <vscale x 8 x i16> @dup_imm_i16(i16 %b) {38; CHECK-LABEL: dup_imm_i16:39; CHECK: // %bb.0:40; CHECK-NEXT: mov z0.h, #16 // =0x1041; CHECK-NEXT: ret42 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 16)43 ret <vscale x 8 x i16> %out44}45 46define <vscale x 4 x i32> @dup_i32(i32 %b) {47; CHECK-LABEL: dup_i32:48; CHECK: // %bb.0:49; CHECK-NEXT: mov z0.s, w050; CHECK-NEXT: ret51 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %b)52 ret <vscale x 4 x i32> %out53}54 55define <vscale x 4 x i32> @dup_imm_i32(i32 %b) {56; CHECK-LABEL: dup_imm_i32:57; CHECK: // %bb.0:58; CHECK-NEXT: mov z0.s, #16 // =0x1059; CHECK-NEXT: ret60 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 16)61 ret <vscale x 4 x i32> %out62}63 64define <vscale x 2 x i64> @dup_i64(i64 %b) {65; CHECK-LABEL: dup_i64:66; CHECK: // %bb.0:67; CHECK-NEXT: mov z0.d, x068; CHECK-NEXT: ret69 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %b)70 ret <vscale x 2 x i64> %out71}72 73define <vscale x 2 x i64> @dup_imm_i64(i64 %b) {74; CHECK-LABEL: dup_imm_i64:75; CHECK: // %bb.0:76; CHECK-NEXT: mov z0.d, #16 // =0x1077; CHECK-NEXT: ret78 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 16)79 ret <vscale x 2 x i64> %out80}81 82define <vscale x 8 x half> @dup_f16(half %b) {83; CHECK-LABEL: dup_f16:84; CHECK: // %bb.0:85; CHECK-NEXT: // kill: def $h0 killed $h0 def $z086; CHECK-NEXT: mov z0.h, h087; CHECK-NEXT: ret88 %out = call <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half %b)89 ret <vscale x 8 x half> %out90}91 92define <vscale x 8 x bfloat> @dup_bf16(bfloat %b) #0 {93; CHECK-LABEL: dup_bf16:94; CHECK: // %bb.0:95; CHECK-NEXT: // kill: def $h0 killed $h0 def $z096; CHECK-NEXT: mov z0.h, h097; CHECK-NEXT: ret98 %out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat %b)99 ret <vscale x 8 x bfloat> %out100}101 102define <vscale x 8 x half> @dup_imm_f16(half %b) {103; CHECK-LABEL: dup_imm_f16:104; CHECK: // %bb.0:105; CHECK-NEXT: fmov z0.h, #16.00000000106; CHECK-NEXT: ret107 %out = call <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half 16.)108 ret <vscale x 8 x half> %out109}110 111define <vscale x 4 x float> @dup_f32(float %b) {112; CHECK-LABEL: dup_f32:113; CHECK: // %bb.0:114; CHECK-NEXT: // kill: def $s0 killed $s0 def $z0115; CHECK-NEXT: mov z0.s, s0116; CHECK-NEXT: ret117 %out = call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float %b)118 ret <vscale x 4 x float> %out119}120 121define <vscale x 4 x float> @dup_imm_f32(float %b) {122; CHECK-LABEL: dup_imm_f32:123; CHECK: // %bb.0:124; CHECK-NEXT: fmov z0.s, #16.00000000125; CHECK-NEXT: ret126 %out = call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float 16.)127 ret <vscale x 4 x float> %out128}129 130define <vscale x 2 x double> @dup_f64(double %b) {131; CHECK-LABEL: dup_f64:132; CHECK: // %bb.0:133; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0134; CHECK-NEXT: mov z0.d, d0135; CHECK-NEXT: ret136 %out = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double %b)137 ret <vscale x 2 x double> %out138}139 140define <vscale x 2 x double> @dup_imm_f64(double %b) {141; CHECK-LABEL: dup_imm_f64:142; CHECK: // %bb.0:143; CHECK-NEXT: fmov z0.d, #16.00000000144; CHECK-NEXT: ret145 %out = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double 16.)146 ret <vscale x 2 x double> %out147}148 149define <vscale x 2 x float> @dup_fmov_imm_f32_2() {150; CHECK-LABEL: dup_fmov_imm_f32_2:151; CHECK: // %bb.0:152; CHECK-NEXT: mov w8, #1109917696153; CHECK-NEXT: mov z0.s, w8154; CHECK-NEXT: ret155 %out = tail call <vscale x 2 x float> @llvm.aarch64.sve.dup.x.nxv2f32(float 4.200000e+01)156 ret <vscale x 2 x float> %out157}158 159define <vscale x 4 x float> @dup_fmov_imm_f32_4() {160; CHECK-LABEL: dup_fmov_imm_f32_4:161; CHECK: // %bb.0:162; CHECK-NEXT: mov w8, #1109917696163; CHECK-NEXT: mov z0.s, w8164; CHECK-NEXT: ret165 %out = tail call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float 4.200000e+01)166 ret <vscale x 4 x float> %out167}168 169define <vscale x 2 x double> @dup_fmov_imm_f64_2() {170; CHECK-LABEL: dup_fmov_imm_f64_2:171; CHECK: // %bb.0:172; CHECK-NEXT: mov x8, #4631107791820423168173; CHECK-NEXT: mov z0.d, x8174; CHECK-NEXT: ret175 %out = tail call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double 4.200000e+01)176 ret <vscale x 2 x double> %out177}178 179declare <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8( i8)180declare <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16)181declare <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32)182declare <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64)183declare <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half)184declare <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat)185declare <vscale x 2 x float> @llvm.aarch64.sve.dup.x.nxv2f32(float)186declare <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float)187declare <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double)188 189; +bf16 is required for the bfloat version.190attributes #0 = { "target-features"="+sve,+bf16" }191