277 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -verify-machineinstrs < %s | FileCheck %s3 4;5; LDFF1H, LDFF1W, LDFF1D: base + 32-bit scaled offset, sign (sxtw) or zero (uxtw)6; extended to 64 bits7; e.g. ldff1h z0.d, p0/z, [x0, z0.d, uxtw #1]8;9 10; LDFF1H11define <vscale x 4 x i32> @gldff1h_s_uxtw_index(<vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %b) {12; CHECK-LABEL: gldff1h_s_uxtw_index:13; CHECK: // %bb.0:14; CHECK-NEXT: ldff1h { z0.s }, p0/z, [x0, z0.s, uxtw #1]15; CHECK-NEXT: ret16 %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4i16(<vscale x 4 x i1> %pg,17 ptr %base,18 <vscale x 4 x i32> %b)19 %res = zext <vscale x 4 x i16> %load to <vscale x 4 x i32>20 ret <vscale x 4 x i32> %res21}22 23define <vscale x 4 x i32> @gldff1h_s_sxtw_index(<vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %b) {24; CHECK-LABEL: gldff1h_s_sxtw_index:25; CHECK: // %bb.0:26; CHECK-NEXT: ldff1h { z0.s }, p0/z, [x0, z0.s, sxtw #1]27; CHECK-NEXT: ret28 %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i16(<vscale x 4 x i1> %pg,29 ptr %base,30 <vscale x 4 x i32> %b)31 %res = zext <vscale x 4 x i16> %load to <vscale x 4 x i32>32 ret <vscale x 4 x i32> %res33}34 35define <vscale x 2 x i64> @gldff1h_d_uxtw_index(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {36; CHECK-LABEL: gldff1h_d_uxtw_index:37; CHECK: // %bb.0:38; CHECK-NEXT: ldff1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]39; CHECK-NEXT: ret40 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv2i16(<vscale x 2 x i1> %pg,41 ptr %base,42 <vscale x 2 x i32> %b)43 %res = zext <vscale x 2 x i16> %load to <vscale x 2 x i64>44 ret <vscale x 2 x i64> %res45}46 47define <vscale x 2 x i64> @gldff1h_d_sxtw_index(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {48; CHECK-LABEL: gldff1h_d_sxtw_index:49; CHECK: // %bb.0:50; CHECK-NEXT: ldff1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]51; CHECK-NEXT: ret52 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv2i16(<vscale x 2 x i1> %pg,53 ptr %base,54 <vscale x 2 x i32> %b)55 %res = zext <vscale x 2 x i16> %load to <vscale x 2 x i64>56 ret <vscale x 2 x i64> %res57}58 59; LDFF1W60define <vscale x 4 x i32> @gldff1w_s_uxtw_index(<vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %b) {61; CHECK-LABEL: gldff1w_s_uxtw_index:62; CHECK: // %bb.0:63; CHECK-NEXT: ldff1w { z0.s }, p0/z, [x0, z0.s, uxtw #2]64; CHECK-NEXT: ret65 %load = call <vscale x 4 x i32> @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4i32(<vscale x 4 x i1> %pg,66 ptr %base,67 <vscale x 4 x i32> %b)68 ret <vscale x 4 x i32> %load69}70 71define <vscale x 4 x i32> @gldff1w_s_sxtw_index(<vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %b) {72; CHECK-LABEL: gldff1w_s_sxtw_index:73; CHECK: // %bb.0:74; CHECK-NEXT: ldff1w { z0.s }, p0/z, [x0, z0.s, sxtw #2]75; CHECK-NEXT: ret76 %load = call <vscale x 4 x i32> @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i32(<vscale x 4 x i1> %pg,77 ptr %base,78 <vscale x 4 x i32> %b)79 ret <vscale x 4 x i32> %load80}81 82define <vscale x 2 x i64> @gldff1w_d_uxtw_index(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {83; CHECK-LABEL: gldff1w_d_uxtw_index:84; CHECK: // %bb.0:85; CHECK-NEXT: ldff1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]86; CHECK-NEXT: ret87 %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv2i32(<vscale x 2 x i1> %pg,88 ptr %base,89 <vscale x 2 x i32> %b)90 %res = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>91 ret <vscale x 2 x i64> %res92}93 94define <vscale x 2 x i64> @gldff1w_d_sxtw_index(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {95; CHECK-LABEL: gldff1w_d_sxtw_index:96; CHECK: // %bb.0:97; CHECK-NEXT: ldff1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]98; CHECK-NEXT: ret99 %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv2i32(<vscale x 2 x i1> %pg,100 ptr %base,101 <vscale x 2 x i32> %b)102 %res = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>103 ret <vscale x 2 x i64> %res104}105 106define <vscale x 4 x float> @gldff1w_s_uxtw_index_float(<vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %b) {107; CHECK-LABEL: gldff1w_s_uxtw_index_float:108; CHECK: // %bb.0:109; CHECK-NEXT: ldff1w { z0.s }, p0/z, [x0, z0.s, uxtw #2]110; CHECK-NEXT: ret111 %load = call <vscale x 4 x float> @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4f32(<vscale x 4 x i1> %pg,112 ptr %base,113 <vscale x 4 x i32> %b)114 ret <vscale x 4 x float> %load115}116 117define <vscale x 4 x float> @gldff1w_s_sxtw_index_float(<vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %b) {118; CHECK-LABEL: gldff1w_s_sxtw_index_float:119; CHECK: // %bb.0:120; CHECK-NEXT: ldff1w { z0.s }, p0/z, [x0, z0.s, sxtw #2]121; CHECK-NEXT: ret122 %load = call <vscale x 4 x float> @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4f32(<vscale x 4 x i1> %pg,123 ptr %base,124 <vscale x 4 x i32> %b)125 ret <vscale x 4 x float> %load126}127 128; LDFF1D129define <vscale x 2 x i64> @gldff1d_s_uxtw_index(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {130; CHECK-LABEL: gldff1d_s_uxtw_index:131; CHECK: // %bb.0:132; CHECK-NEXT: ldff1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]133; CHECK-NEXT: ret134 %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv2i64(<vscale x 2 x i1> %pg,135 ptr %base,136 <vscale x 2 x i32> %b)137 ret <vscale x 2 x i64> %load138}139 140define <vscale x 2 x i64> @gldff1d_sxtw_index(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {141; CHECK-LABEL: gldff1d_sxtw_index:142; CHECK: // %bb.0:143; CHECK-NEXT: ldff1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]144; CHECK-NEXT: ret145 %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv2i64(<vscale x 2 x i1> %pg,146 ptr %base,147 <vscale x 2 x i32> %b)148 ret <vscale x 2 x i64> %load149}150 151define <vscale x 2 x double> @gldff1d_uxtw_index_double(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {152; CHECK-LABEL: gldff1d_uxtw_index_double:153; CHECK: // %bb.0:154; CHECK-NEXT: ldff1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]155; CHECK-NEXT: ret156 %load = call <vscale x 2 x double> @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv2f64(<vscale x 2 x i1> %pg,157 ptr %base,158 <vscale x 2 x i32> %b)159 ret <vscale x 2 x double> %load160}161 162define <vscale x 2 x double> @gldff1d_sxtw_index_double(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {163; CHECK-LABEL: gldff1d_sxtw_index_double:164; CHECK: // %bb.0:165; CHECK-NEXT: ldff1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]166; CHECK-NEXT: ret167 %load = call <vscale x 2 x double> @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv2f64(<vscale x 2 x i1> %pg,168 ptr %base,169 <vscale x 2 x i32> %b)170 ret <vscale x 2 x double> %load171}172 173;174; LDFF1SH, LDFF1SW, LDFF1SD: base + 32-bit scaled offset, sign (sxtw) or zero (uxtw)175; extended to 64 bits176; e.g. ldff1sh z0.d, p0/z, [x0, z0.d, uxtw #1]177;178 179; LDFF1SH180define <vscale x 4 x i32> @gldff1sh_s_uxtw_index(<vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %b) {181; CHECK-LABEL: gldff1sh_s_uxtw_index:182; CHECK: // %bb.0:183; CHECK-NEXT: ldff1sh { z0.s }, p0/z, [x0, z0.s, uxtw #1]184; CHECK-NEXT: ret185 %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4i16(<vscale x 4 x i1> %pg,186 ptr %base,187 <vscale x 4 x i32> %b)188 %res = sext <vscale x 4 x i16> %load to <vscale x 4 x i32>189 ret <vscale x 4 x i32> %res190}191 192define <vscale x 4 x i32> @gldff1sh_s_sxtw_index(<vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %b) {193; CHECK-LABEL: gldff1sh_s_sxtw_index:194; CHECK: // %bb.0:195; CHECK-NEXT: ldff1sh { z0.s }, p0/z, [x0, z0.s, sxtw #1]196; CHECK-NEXT: ret197 %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i16(<vscale x 4 x i1> %pg,198 ptr %base,199 <vscale x 4 x i32> %b)200 %res = sext <vscale x 4 x i16> %load to <vscale x 4 x i32>201 ret <vscale x 4 x i32> %res202}203 204define <vscale x 2 x i64> @gldff1sh_d_uxtw_index(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {205; CHECK-LABEL: gldff1sh_d_uxtw_index:206; CHECK: // %bb.0:207; CHECK-NEXT: ldff1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]208; CHECK-NEXT: ret209 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv2i16(<vscale x 2 x i1> %pg,210 ptr %base,211 <vscale x 2 x i32> %b)212 %res = sext <vscale x 2 x i16> %load to <vscale x 2 x i64>213 ret <vscale x 2 x i64> %res214}215 216define <vscale x 2 x i64> @gldff1sh_d_sxtw_index(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {217; CHECK-LABEL: gldff1sh_d_sxtw_index:218; CHECK: // %bb.0:219; CHECK-NEXT: ldff1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]220; CHECK-NEXT: ret221 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv2i16(<vscale x 2 x i1> %pg,222 ptr %base,223 <vscale x 2 x i32> %b)224 %res = sext <vscale x 2 x i16> %load to <vscale x 2 x i64>225 ret <vscale x 2 x i64> %res226}227 228; LDFF1SW229define <vscale x 2 x i64> @gldff1sw_d_uxtw_index(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {230; CHECK-LABEL: gldff1sw_d_uxtw_index:231; CHECK: // %bb.0:232; CHECK-NEXT: ldff1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]233; CHECK-NEXT: ret234 %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv2i32(<vscale x 2 x i1> %pg,235 ptr %base,236 <vscale x 2 x i32> %b)237 %res = sext <vscale x 2 x i32> %load to <vscale x 2 x i64>238 ret <vscale x 2 x i64> %res239}240 241define <vscale x 2 x i64> @gldff1sw_d_sxtw_index(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {242; CHECK-LABEL: gldff1sw_d_sxtw_index:243; CHECK: // %bb.0:244; CHECK-NEXT: ldff1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]245; CHECK-NEXT: ret246 %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv2i32(<vscale x 2 x i1> %pg,247 ptr %base,248 <vscale x 2 x i32> %b)249 %res = sext <vscale x 2 x i32> %load to <vscale x 2 x i64>250 ret <vscale x 2 x i64> %res251}252 253 254; LDFF1H/LDFF1SH255declare <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4i16(<vscale x 4 x i1>, ptr, <vscale x 4 x i32>)256declare <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i16(<vscale x 4 x i1>, ptr, <vscale x 4 x i32>)257 258declare <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv2i16(<vscale x 2 x i1>, ptr, <vscale x 2 x i32>)259declare <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv2i16(<vscale x 2 x i1>, ptr, <vscale x 2 x i32>)260 261; LDFF1W/LDFF1SW262declare <vscale x 4 x i32> @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4i32(<vscale x 4 x i1>, ptr, <vscale x 4 x i32>)263declare <vscale x 4 x i32> @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i32(<vscale x 4 x i1>, ptr, <vscale x 4 x i32>)264 265declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv2i32(<vscale x 2 x i1>, ptr, <vscale x 2 x i32>)266declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv2i32(<vscale x 2 x i1>, ptr, <vscale x 2 x i32>)267 268declare <vscale x 4 x float> @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4f32(<vscale x 4 x i1>, ptr, <vscale x 4 x i32>)269declare <vscale x 4 x float> @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4f32(<vscale x 4 x i1>, ptr, <vscale x 4 x i32>)270 271; LDFF1D272declare <vscale x 2 x i64> @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv2i64(<vscale x 2 x i1>, ptr, <vscale x 2 x i32>)273declare <vscale x 2 x i64> @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv2i64(<vscale x 2 x i1>, ptr, <vscale x 2 x i32>)274 275declare <vscale x 2 x double> @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv2f64(<vscale x 2 x i1>, ptr, <vscale x 2 x i32>)276declare <vscale x 2 x double> @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv2f64(<vscale x 2 x i1>, ptr, <vscale x 2 x i32>)277