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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4;5; FABD6;7 8define <vscale x 8 x half> @fabd_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {9; CHECK-LABEL: fabd_h:10; CHECK: // %bb.0:11; CHECK-NEXT: fabd z0.h, p0/m, z0.h, z1.h12; CHECK-NEXT: ret13 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fabd.u.nxv8f16(<vscale x 8 x i1> %pg,14 <vscale x 8 x half> %a,15 <vscale x 8 x half> %b)16 ret <vscale x 8 x half> %out17}18 19define <vscale x 4 x float> @fabd_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {20; CHECK-LABEL: fabd_s:21; CHECK: // %bb.0:22; CHECK-NEXT: fabd z0.s, p0/m, z0.s, z1.s23; CHECK-NEXT: ret24 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fabd.u.nxv4f32(<vscale x 4 x i1> %pg,25 <vscale x 4 x float> %a,26 <vscale x 4 x float> %b)27 ret <vscale x 4 x float> %out28}29 30define <vscale x 2 x double> @fabd_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {31; CHECK-LABEL: fabd_d:32; CHECK: // %bb.0:33; CHECK-NEXT: fabd z0.d, p0/m, z0.d, z1.d34; CHECK-NEXT: ret35 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fabd.u.nxv2f64(<vscale x 2 x i1> %pg,36 <vscale x 2 x double> %a,37 <vscale x 2 x double> %b)38 ret <vscale x 2 x double> %out39}40 41;42; FADD43;44 45define <vscale x 8 x half> @fadd_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {46; CHECK-LABEL: fadd_h:47; CHECK: // %bb.0:48; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h49; CHECK-NEXT: ret50 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fadd.u.nxv8f16(<vscale x 8 x i1> %pg,51 <vscale x 8 x half> %a,52 <vscale x 8 x half> %b)53 ret <vscale x 8 x half> %out54}55 56define <vscale x 4 x float> @fadd_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {57; CHECK-LABEL: fadd_s:58; CHECK: // %bb.0:59; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s60; CHECK-NEXT: ret61 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fadd.u.nxv4f32(<vscale x 4 x i1> %pg,62 <vscale x 4 x float> %a,63 <vscale x 4 x float> %b)64 ret <vscale x 4 x float> %out65}66 67define <vscale x 2 x double> @fadd_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {68; CHECK-LABEL: fadd_d:69; CHECK: // %bb.0:70; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z1.d71; CHECK-NEXT: ret72 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fadd.u.nxv2f64(<vscale x 2 x i1> %pg,73 <vscale x 2 x double> %a,74 <vscale x 2 x double> %b)75 ret <vscale x 2 x double> %out76}77 78;79; FDIV80;81 82define <vscale x 8 x half> @fdiv_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {83; CHECK-LABEL: fdiv_h:84; CHECK: // %bb.0:85; CHECK-NEXT: fdiv z0.h, p0/m, z0.h, z1.h86; CHECK-NEXT: ret87 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fdiv.u.nxv8f16(<vscale x 8 x i1> %pg,88 <vscale x 8 x half> %a,89 <vscale x 8 x half> %b)90 ret <vscale x 8 x half> %out91}92 93define <vscale x 4 x float> @fdiv_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {94; CHECK-LABEL: fdiv_s:95; CHECK: // %bb.0:96; CHECK-NEXT: fdiv z0.s, p0/m, z0.s, z1.s97; CHECK-NEXT: ret98 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fdiv.u.nxv4f32(<vscale x 4 x i1> %pg,99 <vscale x 4 x float> %a,100 <vscale x 4 x float> %b)101 ret <vscale x 4 x float> %out102}103 104define <vscale x 2 x double> @fdiv_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {105; CHECK-LABEL: fdiv_d:106; CHECK: // %bb.0:107; CHECK-NEXT: fdiv z0.d, p0/m, z0.d, z1.d108; CHECK-NEXT: ret109 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fdiv.u.nxv2f64(<vscale x 2 x i1> %pg,110 <vscale x 2 x double> %a,111 <vscale x 2 x double> %b)112 ret <vscale x 2 x double> %out113}114 115;116; FDIVR117;118 119define <vscale x 8 x half> @fdivr_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {120; CHECK-LABEL: fdivr_h:121; CHECK: // %bb.0:122; CHECK-NEXT: fdivr z0.h, p0/m, z0.h, z1.h123; CHECK-NEXT: ret124 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fdiv.u.nxv8f16(<vscale x 8 x i1> %pg,125 <vscale x 8 x half> %b,126 <vscale x 8 x half> %a)127 ret <vscale x 8 x half> %out128}129 130define <vscale x 4 x float> @fdivr_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {131; CHECK-LABEL: fdivr_s:132; CHECK: // %bb.0:133; CHECK-NEXT: fdivr z0.s, p0/m, z0.s, z1.s134; CHECK-NEXT: ret135 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fdiv.u.nxv4f32(<vscale x 4 x i1> %pg,136 <vscale x 4 x float> %b,137 <vscale x 4 x float> %a)138 ret <vscale x 4 x float> %out139}140 141define <vscale x 2 x double> @fdivr_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {142; CHECK-LABEL: fdivr_d:143; CHECK: // %bb.0:144; CHECK-NEXT: fdivr z0.d, p0/m, z0.d, z1.d145; CHECK-NEXT: ret146 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fdiv.u.nxv2f64(<vscale x 2 x i1> %pg,147 <vscale x 2 x double> %b,148 <vscale x 2 x double> %a)149 ret <vscale x 2 x double> %out150}151 152;153; FMAD154;155 156define <vscale x 8 x half> @fmad_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {157; CHECK-LABEL: fmad_h:158; CHECK: // %bb.0:159; CHECK-NEXT: fmad z0.h, p0/m, z1.h, z2.h160; CHECK-NEXT: ret161 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmla.u.nxv8f16(<vscale x 8 x i1> %pg,162 <vscale x 8 x half> %c,163 <vscale x 8 x half> %a,164 <vscale x 8 x half> %b)165 ret <vscale x 8 x half> %out166}167 168define <vscale x 4 x float> @fmad_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c) {169; CHECK-LABEL: fmad_s:170; CHECK: // %bb.0:171; CHECK-NEXT: fmad z0.s, p0/m, z1.s, z2.s172; CHECK-NEXT: ret173 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmla.u.nxv4f32(<vscale x 4 x i1> %pg,174 <vscale x 4 x float> %c,175 <vscale x 4 x float> %a,176 <vscale x 4 x float> %b)177 ret <vscale x 4 x float> %out178}179 180define <vscale x 2 x double> @fmad_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b, <vscale x 2 x double> %c) {181; CHECK-LABEL: fmad_d:182; CHECK: // %bb.0:183; CHECK-NEXT: fmad z0.d, p0/m, z1.d, z2.d184; CHECK-NEXT: ret185 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmla.u.nxv2f64(<vscale x 2 x i1> %pg,186 <vscale x 2 x double> %c,187 <vscale x 2 x double> %a,188 <vscale x 2 x double> %b)189 ret <vscale x 2 x double> %out190}191 192;193; FMAX194;195 196define <vscale x 8 x half> @fmax_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {197; CHECK-LABEL: fmax_h:198; CHECK: // %bb.0:199; CHECK-NEXT: fmax z0.h, p0/m, z0.h, z1.h200; CHECK-NEXT: ret201 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmax.u.nxv8f16(<vscale x 8 x i1> %pg,202 <vscale x 8 x half> %a,203 <vscale x 8 x half> %b)204 ret <vscale x 8 x half> %out205}206 207define <vscale x 4 x float> @fmax_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {208; CHECK-LABEL: fmax_s:209; CHECK: // %bb.0:210; CHECK-NEXT: fmax z0.s, p0/m, z0.s, z1.s211; CHECK-NEXT: ret212 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmax.u.nxv4f32(<vscale x 4 x i1> %pg,213 <vscale x 4 x float> %a,214 <vscale x 4 x float> %b)215 ret <vscale x 4 x float> %out216}217 218define <vscale x 2 x double> @fmax_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {219; CHECK-LABEL: fmax_d:220; CHECK: // %bb.0:221; CHECK-NEXT: fmax z0.d, p0/m, z0.d, z1.d222; CHECK-NEXT: ret223 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmax.u.nxv2f64(<vscale x 2 x i1> %pg,224 <vscale x 2 x double> %a,225 <vscale x 2 x double> %b)226 ret <vscale x 2 x double> %out227}228 229;230; FMAXNM231;232 233define <vscale x 8 x half> @fmaxnm_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {234; CHECK-LABEL: fmaxnm_h:235; CHECK: // %bb.0:236; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, z1.h237; CHECK-NEXT: ret238 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.u.nxv8f16(<vscale x 8 x i1> %pg,239 <vscale x 8 x half> %a,240 <vscale x 8 x half> %b)241 ret <vscale x 8 x half> %out242}243 244define <vscale x 4 x float> @fmaxnm_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {245; CHECK-LABEL: fmaxnm_s:246; CHECK: // %bb.0:247; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, z1.s248; CHECK-NEXT: ret249 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.u.nxv4f32(<vscale x 4 x i1> %pg,250 <vscale x 4 x float> %a,251 <vscale x 4 x float> %b)252 ret <vscale x 4 x float> %out253}254 255define <vscale x 2 x double> @fmaxnm_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {256; CHECK-LABEL: fmaxnm_d:257; CHECK: // %bb.0:258; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, z1.d259; CHECK-NEXT: ret260 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.u.nxv2f64(<vscale x 2 x i1> %pg,261 <vscale x 2 x double> %a,262 <vscale x 2 x double> %b)263 ret <vscale x 2 x double> %out264}265 266;267; FMIN268;269 270define <vscale x 8 x half> @fmin_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {271; CHECK-LABEL: fmin_h:272; CHECK: // %bb.0:273; CHECK-NEXT: fmin z0.h, p0/m, z0.h, z1.h274; CHECK-NEXT: ret275 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmin.u.nxv8f16(<vscale x 8 x i1> %pg,276 <vscale x 8 x half> %a,277 <vscale x 8 x half> %b)278 ret <vscale x 8 x half> %out279}280 281define <vscale x 4 x float> @fmin_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {282; CHECK-LABEL: fmin_s:283; CHECK: // %bb.0:284; CHECK-NEXT: fmin z0.s, p0/m, z0.s, z1.s285; CHECK-NEXT: ret286 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmin.u.nxv4f32(<vscale x 4 x i1> %pg,287 <vscale x 4 x float> %a,288 <vscale x 4 x float> %b)289 ret <vscale x 4 x float> %out290}291 292define <vscale x 2 x double> @fmin_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {293; CHECK-LABEL: fmin_d:294; CHECK: // %bb.0:295; CHECK-NEXT: fmin z0.d, p0/m, z0.d, z1.d296; CHECK-NEXT: ret297 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmin.u.nxv2f64(<vscale x 2 x i1> %pg,298 <vscale x 2 x double> %a,299 <vscale x 2 x double> %b)300 ret <vscale x 2 x double> %out301}302 303;304; FMINNM305;306 307define <vscale x 8 x half> @fminnm_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {308; CHECK-LABEL: fminnm_h:309; CHECK: // %bb.0:310; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, z1.h311; CHECK-NEXT: ret312 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fminnm.u.nxv8f16(<vscale x 8 x i1> %pg,313 <vscale x 8 x half> %a,314 <vscale x 8 x half> %b)315 ret <vscale x 8 x half> %out316}317 318define <vscale x 4 x float> @fminnm_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {319; CHECK-LABEL: fminnm_s:320; CHECK: // %bb.0:321; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, z1.s322; CHECK-NEXT: ret323 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fminnm.u.nxv4f32(<vscale x 4 x i1> %pg,324 <vscale x 4 x float> %a,325 <vscale x 4 x float> %b)326 ret <vscale x 4 x float> %out327}328 329define <vscale x 2 x double> @fminnm_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {330; CHECK-LABEL: fminnm_d:331; CHECK: // %bb.0:332; CHECK-NEXT: fminnm z0.d, p0/m, z0.d, z1.d333; CHECK-NEXT: ret334 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fminnm.u.nxv2f64(<vscale x 2 x i1> %pg,335 <vscale x 2 x double> %a,336 <vscale x 2 x double> %b)337 ret <vscale x 2 x double> %out338}339 340;341; FMLA342;343 344define <vscale x 8 x half> @fmla_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {345; CHECK-LABEL: fmla_h:346; CHECK: // %bb.0:347; CHECK-NEXT: fmla z0.h, p0/m, z1.h, z2.h348; CHECK-NEXT: ret349 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmla.u.nxv8f16(<vscale x 8 x i1> %pg,350 <vscale x 8 x half> %a,351 <vscale x 8 x half> %b,352 <vscale x 8 x half> %c)353 ret <vscale x 8 x half> %out354}355 356define <vscale x 4 x float> @fmla_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c) {357; CHECK-LABEL: fmla_s:358; CHECK: // %bb.0:359; CHECK-NEXT: fmla z0.s, p0/m, z1.s, z2.s360; CHECK-NEXT: ret361 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmla.u.nxv4f32(<vscale x 4 x i1> %pg,362 <vscale x 4 x float> %a,363 <vscale x 4 x float> %b,364 <vscale x 4 x float> %c)365 ret <vscale x 4 x float> %out366}367 368define <vscale x 2 x double> @fmla_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b, <vscale x 2 x double> %c) {369; CHECK-LABEL: fmla_d:370; CHECK: // %bb.0:371; CHECK-NEXT: fmla z0.d, p0/m, z1.d, z2.d372; CHECK-NEXT: ret373 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmla.u.nxv2f64(<vscale x 2 x i1> %pg,374 <vscale x 2 x double> %a,375 <vscale x 2 x double> %b,376 <vscale x 2 x double> %c)377 ret <vscale x 2 x double> %out378}379 380;381; FMLS382;383 384define <vscale x 8 x half> @fmls_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {385; CHECK-LABEL: fmls_h:386; CHECK: // %bb.0:387; CHECK-NEXT: fmls z0.h, p0/m, z1.h, z2.h388; CHECK-NEXT: ret389 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmls.u.nxv8f16(<vscale x 8 x i1> %pg,390 <vscale x 8 x half> %a,391 <vscale x 8 x half> %b,392 <vscale x 8 x half> %c)393 ret <vscale x 8 x half> %out394}395 396define <vscale x 4 x float> @fmls_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c) {397; CHECK-LABEL: fmls_s:398; CHECK: // %bb.0:399; CHECK-NEXT: fmls z0.s, p0/m, z1.s, z2.s400; CHECK-NEXT: ret401 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmls.u.nxv4f32(<vscale x 4 x i1> %pg,402 <vscale x 4 x float> %a,403 <vscale x 4 x float> %b,404 <vscale x 4 x float> %c)405 ret <vscale x 4 x float> %out406}407 408define <vscale x 2 x double> @fmls_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b, <vscale x 2 x double> %c) {409; CHECK-LABEL: fmls_d:410; CHECK: // %bb.0:411; CHECK-NEXT: fmls z0.d, p0/m, z1.d, z2.d412; CHECK-NEXT: ret413 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmls.u.nxv2f64(<vscale x 2 x i1> %pg,414 <vscale x 2 x double> %a,415 <vscale x 2 x double> %b,416 <vscale x 2 x double> %c)417 ret <vscale x 2 x double> %out418}419 420;421; FMSB422;423 424define <vscale x 8 x half> @fmsb_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {425; CHECK-LABEL: fmsb_h:426; CHECK: // %bb.0:427; CHECK-NEXT: fmsb z0.h, p0/m, z1.h, z2.h428; CHECK-NEXT: ret429 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmls.u.nxv8f16(<vscale x 8 x i1> %pg,430 <vscale x 8 x half> %c,431 <vscale x 8 x half> %a,432 <vscale x 8 x half> %b)433 ret <vscale x 8 x half> %out434}435 436define <vscale x 4 x float> @fmsb_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c) {437; CHECK-LABEL: fmsb_s:438; CHECK: // %bb.0:439; CHECK-NEXT: fmsb z0.s, p0/m, z1.s, z2.s440; CHECK-NEXT: ret441 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmls.u.nxv4f32(<vscale x 4 x i1> %pg,442 <vscale x 4 x float> %c,443 <vscale x 4 x float> %a,444 <vscale x 4 x float> %b)445 ret <vscale x 4 x float> %out446}447 448define <vscale x 2 x double> @fmsb_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b, <vscale x 2 x double> %c) {449; CHECK-LABEL: fmsb_d:450; CHECK: // %bb.0:451; CHECK-NEXT: fmsb z0.d, p0/m, z1.d, z2.d452; CHECK-NEXT: ret453 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmls.u.nxv2f64(<vscale x 2 x i1> %pg,454 <vscale x 2 x double> %c,455 <vscale x 2 x double> %a,456 <vscale x 2 x double> %b)457 ret <vscale x 2 x double> %out458}459 460;461; FMUL462;463 464define <vscale x 8 x half> @fmul_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {465; CHECK-LABEL: fmul_h:466; CHECK: // %bb.0:467; CHECK-NEXT: fmul z0.h, p0/m, z0.h, z1.h468; CHECK-NEXT: ret469 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmul.u.nxv8f16(<vscale x 8 x i1> %pg,470 <vscale x 8 x half> %a,471 <vscale x 8 x half> %b)472 ret <vscale x 8 x half> %out473}474 475define <vscale x 4 x float> @fmul_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {476; CHECK-LABEL: fmul_s:477; CHECK: // %bb.0:478; CHECK-NEXT: fmul z0.s, p0/m, z0.s, z1.s479; CHECK-NEXT: ret480 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmul.u.nxv4f32(<vscale x 4 x i1> %pg,481 <vscale x 4 x float> %a,482 <vscale x 4 x float> %b)483 ret <vscale x 4 x float> %out484}485 486define <vscale x 2 x double> @fmul_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {487; CHECK-LABEL: fmul_d:488; CHECK: // %bb.0:489; CHECK-NEXT: fmul z0.d, p0/m, z0.d, z1.d490; CHECK-NEXT: ret491 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmul.u.nxv2f64(<vscale x 2 x i1> %pg,492 <vscale x 2 x double> %a,493 <vscale x 2 x double> %b)494 ret <vscale x 2 x double> %out495}496 497;498; FMULX499;500 501define <vscale x 8 x half> @fmulx_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {502; CHECK-LABEL: fmulx_h:503; CHECK: // %bb.0:504; CHECK-NEXT: fmulx z0.h, p0/m, z0.h, z1.h505; CHECK-NEXT: ret506 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmulx.u.nxv8f16(<vscale x 8 x i1> %pg,507 <vscale x 8 x half> %a,508 <vscale x 8 x half> %b)509 ret <vscale x 8 x half> %out510}511 512define <vscale x 4 x float> @fmulx_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {513; CHECK-LABEL: fmulx_s:514; CHECK: // %bb.0:515; CHECK-NEXT: fmulx z0.s, p0/m, z0.s, z1.s516; CHECK-NEXT: ret517 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmulx.u.nxv4f32(<vscale x 4 x i1> %pg,518 <vscale x 4 x float> %a,519 <vscale x 4 x float> %b)520 ret <vscale x 4 x float> %out521}522 523define <vscale x 2 x double> @fmulx_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {524; CHECK-LABEL: fmulx_d:525; CHECK: // %bb.0:526; CHECK-NEXT: fmulx z0.d, p0/m, z0.d, z1.d527; CHECK-NEXT: ret528 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmulx.u.nxv2f64(<vscale x 2 x i1> %pg,529 <vscale x 2 x double> %a,530 <vscale x 2 x double> %b)531 ret <vscale x 2 x double> %out532}533 534;535; FNMAD536;537 538define <vscale x 8 x half> @fnmad_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {539; CHECK-LABEL: fnmad_h:540; CHECK: // %bb.0:541; CHECK-NEXT: fnmad z0.h, p0/m, z1.h, z2.h542; CHECK-NEXT: ret543 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fnmla.u.nxv8f16(<vscale x 8 x i1> %pg,544 <vscale x 8 x half> %c,545 <vscale x 8 x half> %a,546 <vscale x 8 x half> %b)547 ret <vscale x 8 x half> %out548}549 550define <vscale x 4 x float> @fnmad_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c) {551; CHECK-LABEL: fnmad_s:552; CHECK: // %bb.0:553; CHECK-NEXT: fnmad z0.s, p0/m, z1.s, z2.s554; CHECK-NEXT: ret555 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fnmla.u.nxv4f32(<vscale x 4 x i1> %pg,556 <vscale x 4 x float> %c,557 <vscale x 4 x float> %a,558 <vscale x 4 x float> %b)559 ret <vscale x 4 x float> %out560}561 562define <vscale x 2 x double> @fnmad_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b, <vscale x 2 x double> %c) {563; CHECK-LABEL: fnmad_d:564; CHECK: // %bb.0:565; CHECK-NEXT: fnmad z0.d, p0/m, z1.d, z2.d566; CHECK-NEXT: ret567 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fnmla.u.nxv2f64(<vscale x 2 x i1> %pg,568 <vscale x 2 x double> %c,569 <vscale x 2 x double> %a,570 <vscale x 2 x double> %b)571 ret <vscale x 2 x double> %out572}573 574;575; FNMLA576;577 578define <vscale x 8 x half> @fnmla_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {579; CHECK-LABEL: fnmla_h:580; CHECK: // %bb.0:581; CHECK-NEXT: fnmla z0.h, p0/m, z1.h, z2.h582; CHECK-NEXT: ret583 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fnmla.u.nxv8f16(<vscale x 8 x i1> %pg,584 <vscale x 8 x half> %a,585 <vscale x 8 x half> %b,586 <vscale x 8 x half> %c)587 ret <vscale x 8 x half> %out588}589 590define <vscale x 4 x float> @fnmla_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c) {591; CHECK-LABEL: fnmla_s:592; CHECK: // %bb.0:593; CHECK-NEXT: fnmla z0.s, p0/m, z1.s, z2.s594; CHECK-NEXT: ret595 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fnmla.u.nxv4f32(<vscale x 4 x i1> %pg,596 <vscale x 4 x float> %a,597 <vscale x 4 x float> %b,598 <vscale x 4 x float> %c)599 ret <vscale x 4 x float> %out600}601 602define <vscale x 2 x double> @fnmla_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b, <vscale x 2 x double> %c) {603; CHECK-LABEL: fnmla_d:604; CHECK: // %bb.0:605; CHECK-NEXT: fnmla z0.d, p0/m, z1.d, z2.d606; CHECK-NEXT: ret607 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fnmla.u.nxv2f64(<vscale x 2 x i1> %pg,608 <vscale x 2 x double> %a,609 <vscale x 2 x double> %b,610 <vscale x 2 x double> %c)611 ret <vscale x 2 x double> %out612}613 614;615; FNMLS616;617 618define <vscale x 8 x half> @fnmls_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {619; CHECK-LABEL: fnmls_h:620; CHECK: // %bb.0:621; CHECK-NEXT: fnmls z0.h, p0/m, z1.h, z2.h622; CHECK-NEXT: ret623 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fnmls.u.nxv8f16(<vscale x 8 x i1> %pg,624 <vscale x 8 x half> %a,625 <vscale x 8 x half> %b,626 <vscale x 8 x half> %c)627 ret <vscale x 8 x half> %out628}629 630define <vscale x 4 x float> @fnmls_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c) {631; CHECK-LABEL: fnmls_s:632; CHECK: // %bb.0:633; CHECK-NEXT: fnmls z0.s, p0/m, z1.s, z2.s634; CHECK-NEXT: ret635 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fnmls.u.nxv4f32(<vscale x 4 x i1> %pg,636 <vscale x 4 x float> %a,637 <vscale x 4 x float> %b,638 <vscale x 4 x float> %c)639 ret <vscale x 4 x float> %out640}641 642define <vscale x 2 x double> @fnmls_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b, <vscale x 2 x double> %c) {643; CHECK-LABEL: fnmls_d:644; CHECK: // %bb.0:645; CHECK-NEXT: fnmls z0.d, p0/m, z1.d, z2.d646; CHECK-NEXT: ret647 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fnmls.u.nxv2f64(<vscale x 2 x i1> %pg,648 <vscale x 2 x double> %a,649 <vscale x 2 x double> %b,650 <vscale x 2 x double> %c)651 ret <vscale x 2 x double> %out652}653 654;655; FNMSB656;657 658define <vscale x 8 x half> @fnmsb_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {659; CHECK-LABEL: fnmsb_h:660; CHECK: // %bb.0:661; CHECK-NEXT: fnmsb z0.h, p0/m, z1.h, z2.h662; CHECK-NEXT: ret663 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fnmls.u.nxv8f16(<vscale x 8 x i1> %pg,664 <vscale x 8 x half> %c,665 <vscale x 8 x half> %a,666 <vscale x 8 x half> %b)667 ret <vscale x 8 x half> %out668}669 670define <vscale x 4 x float> @fnmsb_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c) {671; CHECK-LABEL: fnmsb_s:672; CHECK: // %bb.0:673; CHECK-NEXT: fnmsb z0.s, p0/m, z1.s, z2.s674; CHECK-NEXT: ret675 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fnmls.u.nxv4f32(<vscale x 4 x i1> %pg,676 <vscale x 4 x float> %c,677 <vscale x 4 x float> %a,678 <vscale x 4 x float> %b)679 ret <vscale x 4 x float> %out680}681 682define <vscale x 2 x double> @fnmsb_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b, <vscale x 2 x double> %c) {683; CHECK-LABEL: fnmsb_d:684; CHECK: // %bb.0:685; CHECK-NEXT: fnmsb z0.d, p0/m, z1.d, z2.d686; CHECK-NEXT: ret687 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fnmls.u.nxv2f64(<vscale x 2 x i1> %pg,688 <vscale x 2 x double> %c,689 <vscale x 2 x double> %a,690 <vscale x 2 x double> %b)691 ret <vscale x 2 x double> %out692}693 694;695; FSUB696;697 698define <vscale x 8 x half> @fsub_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {699; CHECK-LABEL: fsub_h:700; CHECK: // %bb.0:701; CHECK-NEXT: fsub z0.h, p0/m, z0.h, z1.h702; CHECK-NEXT: ret703 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fsub.u.nxv8f16(<vscale x 8 x i1> %pg,704 <vscale x 8 x half> %a,705 <vscale x 8 x half> %b)706 ret <vscale x 8 x half> %out707}708 709define <vscale x 4 x float> @fsub_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {710; CHECK-LABEL: fsub_s:711; CHECK: // %bb.0:712; CHECK-NEXT: fsub z0.s, p0/m, z0.s, z1.s713; CHECK-NEXT: ret714 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fsub.u.nxv4f32(<vscale x 4 x i1> %pg,715 <vscale x 4 x float> %a,716 <vscale x 4 x float> %b)717 ret <vscale x 4 x float> %out718}719 720define <vscale x 2 x double> @fsub_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {721; CHECK-LABEL: fsub_d:722; CHECK: // %bb.0:723; CHECK-NEXT: fsub z0.d, p0/m, z0.d, z1.d724; CHECK-NEXT: ret725 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fsub.u.nxv2f64(<vscale x 2 x i1> %pg,726 <vscale x 2 x double> %a,727 <vscale x 2 x double> %b)728 ret <vscale x 2 x double> %out729}730 731;732; FSUBR733;734 735define <vscale x 8 x half> @fsubr_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {736; CHECK-LABEL: fsubr_h:737; CHECK: // %bb.0:738; CHECK-NEXT: fsubr z0.h, p0/m, z0.h, z1.h739; CHECK-NEXT: ret740 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fsub.u.nxv8f16(<vscale x 8 x i1> %pg,741 <vscale x 8 x half> %b,742 <vscale x 8 x half> %a)743 ret <vscale x 8 x half> %out744}745 746define <vscale x 4 x float> @fsubr_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {747; CHECK-LABEL: fsubr_s:748; CHECK: // %bb.0:749; CHECK-NEXT: fsubr z0.s, p0/m, z0.s, z1.s750; CHECK-NEXT: ret751 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fsub.u.nxv4f32(<vscale x 4 x i1> %pg,752 <vscale x 4 x float> %b,753 <vscale x 4 x float> %a)754 ret <vscale x 4 x float> %out755}756 757define <vscale x 2 x double> @fsubr_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {758; CHECK-LABEL: fsubr_d:759; CHECK: // %bb.0:760; CHECK-NEXT: fsubr z0.d, p0/m, z0.d, z1.d761; CHECK-NEXT: ret762 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fsub.u.nxv2f64(<vscale x 2 x i1> %pg,763 <vscale x 2 x double> %b,764 <vscale x 2 x double> %a)765 ret <vscale x 2 x double> %out766}767 768declare <vscale x 8 x half> @llvm.aarch64.sve.fabd.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)769declare <vscale x 4 x float> @llvm.aarch64.sve.fabd.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)770declare <vscale x 2 x double> @llvm.aarch64.sve.fabd.u.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)771 772declare <vscale x 8 x half> @llvm.aarch64.sve.fadd.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)773declare <vscale x 4 x float> @llvm.aarch64.sve.fadd.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)774declare <vscale x 2 x double> @llvm.aarch64.sve.fadd.u.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)775 776declare <vscale x 8 x half> @llvm.aarch64.sve.fdiv.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)777declare <vscale x 4 x float> @llvm.aarch64.sve.fdiv.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)778declare <vscale x 2 x double> @llvm.aarch64.sve.fdiv.u.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)779 780declare <vscale x 8 x half> @llvm.aarch64.sve.fmax.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)781declare <vscale x 4 x float> @llvm.aarch64.sve.fmax.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)782declare <vscale x 2 x double> @llvm.aarch64.sve.fmax.u.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)783 784declare <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)785declare <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)786declare <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.u.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)787 788declare <vscale x 8 x half> @llvm.aarch64.sve.fmin.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)789declare <vscale x 4 x float> @llvm.aarch64.sve.fmin.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)790declare <vscale x 2 x double> @llvm.aarch64.sve.fmin.u.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)791 792declare <vscale x 8 x half> @llvm.aarch64.sve.fminnm.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)793declare <vscale x 4 x float> @llvm.aarch64.sve.fminnm.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)794declare <vscale x 2 x double> @llvm.aarch64.sve.fminnm.u.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)795 796declare <vscale x 8 x half> @llvm.aarch64.sve.fmla.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)797declare <vscale x 4 x float> @llvm.aarch64.sve.fmla.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)798declare <vscale x 2 x double> @llvm.aarch64.sve.fmla.u.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)799 800declare <vscale x 8 x half> @llvm.aarch64.sve.fmls.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)801declare <vscale x 4 x float> @llvm.aarch64.sve.fmls.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)802declare <vscale x 2 x double> @llvm.aarch64.sve.fmls.u.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)803 804declare <vscale x 8 x half> @llvm.aarch64.sve.fmul.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)805declare <vscale x 4 x float> @llvm.aarch64.sve.fmul.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)806declare <vscale x 2 x double> @llvm.aarch64.sve.fmul.u.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)807 808declare <vscale x 8 x half> @llvm.aarch64.sve.fmulx.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)809declare <vscale x 4 x float> @llvm.aarch64.sve.fmulx.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)810declare <vscale x 2 x double> @llvm.aarch64.sve.fmulx.u.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)811 812declare <vscale x 8 x half> @llvm.aarch64.sve.fnmla.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)813declare <vscale x 4 x float> @llvm.aarch64.sve.fnmla.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)814declare <vscale x 2 x double> @llvm.aarch64.sve.fnmla.u.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)815 816declare <vscale x 8 x half> @llvm.aarch64.sve.fnmls.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)817declare <vscale x 4 x float> @llvm.aarch64.sve.fnmls.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)818declare <vscale x 2 x double> @llvm.aarch64.sve.fnmls.u.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)819 820declare <vscale x 8 x half> @llvm.aarch64.sve.fsub.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)821declare <vscale x 4 x float> @llvm.aarch64.sve.fsub.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)822declare <vscale x 2 x double> @llvm.aarch64.sve.fsub.u.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)823