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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4;5; LD1B, LD1W, LD1H, LD1D: base + 32-bit unscaled offset, sign (sxtw) or zero6; (uxtw) extended to 64 bits.7; e.g. ld1h { z0.d }, p0/z, [x0, z0.d, uxtw]8;9 10; LD1B11define <vscale x 4 x i32> @gld1b_s_uxtw(<vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %b) {12; CHECK-LABEL: gld1b_s_uxtw:13; CHECK: // %bb.0:14; CHECK-NEXT: ld1b { z0.s }, p0/z, [x0, z0.s, uxtw]15; CHECK-NEXT: ret16 %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i8(<vscale x 4 x i1> %pg,17 ptr %base,18 <vscale x 4 x i32> %b)19 %res = zext <vscale x 4 x i8> %load to <vscale x 4 x i32>20 ret <vscale x 4 x i32> %res21}22 23define <vscale x 4 x i32> @gld1b_s_sxtw(<vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %b) {24; CHECK-LABEL: gld1b_s_sxtw:25; CHECK: // %bb.0:26; CHECK-NEXT: ld1b { z0.s }, p0/z, [x0, z0.s, sxtw]27; CHECK-NEXT: ret28 %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i8(<vscale x 4 x i1> %pg,29 ptr %base,30 <vscale x 4 x i32> %b)31 %res = zext <vscale x 4 x i8> %load to <vscale x 4 x i32>32 ret <vscale x 4 x i32> %res33}34 35define <vscale x 2 x i64> @gld1b_d_uxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {36; CHECK-LABEL: gld1b_d_uxtw:37; CHECK: // %bb.0:38; CHECK-NEXT: ld1b { z0.d }, p0/z, [x0, z0.d, uxtw]39; CHECK-NEXT: ret40 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i8(<vscale x 2 x i1> %pg,41 ptr %base,42 <vscale x 2 x i32> %b)43 %res = zext <vscale x 2 x i8> %load to <vscale x 2 x i64>44 ret <vscale x 2 x i64> %res45}46 47define <vscale x 2 x i64> @gld1b_d_sxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {48; CHECK-LABEL: gld1b_d_sxtw:49; CHECK: // %bb.0:50; CHECK-NEXT: ld1b { z0.d }, p0/z, [x0, z0.d, sxtw]51; CHECK-NEXT: ret52 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i8(<vscale x 2 x i1> %pg,53 ptr %base,54 <vscale x 2 x i32> %b)55 %res = zext <vscale x 2 x i8> %load to <vscale x 2 x i64>56 ret <vscale x 2 x i64> %res57}58 59; LD1H60define <vscale x 4 x i32> @gld1h_s_uxtw(<vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %b) {61; CHECK-LABEL: gld1h_s_uxtw:62; CHECK: // %bb.0:63; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0, z0.s, uxtw]64; CHECK-NEXT: ret65 %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i16(<vscale x 4 x i1> %pg,66 ptr %base,67 <vscale x 4 x i32> %b)68 %res = zext <vscale x 4 x i16> %load to <vscale x 4 x i32>69 ret <vscale x 4 x i32> %res70}71 72define <vscale x 4 x i32> @gld1h_s_sxtw(<vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %b) {73; CHECK-LABEL: gld1h_s_sxtw:74; CHECK: // %bb.0:75; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0, z0.s, sxtw]76; CHECK-NEXT: ret77 %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i16(<vscale x 4 x i1> %pg,78 ptr %base,79 <vscale x 4 x i32> %b)80 %res = zext <vscale x 4 x i16> %load to <vscale x 4 x i32>81 ret <vscale x 4 x i32> %res82}83 84define <vscale x 2 x i64> @gld1h_d_uxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {85; CHECK-LABEL: gld1h_d_uxtw:86; CHECK: // %bb.0:87; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, z0.d, uxtw]88; CHECK-NEXT: ret89 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i16(<vscale x 2 x i1> %pg,90 ptr %base,91 <vscale x 2 x i32> %b)92 %res = zext <vscale x 2 x i16> %load to <vscale x 2 x i64>93 ret <vscale x 2 x i64> %res94}95 96define <vscale x 2 x i64> @gld1h_d_sxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {97; CHECK-LABEL: gld1h_d_sxtw:98; CHECK: // %bb.0:99; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, z0.d, sxtw]100; CHECK-NEXT: ret101 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i16(<vscale x 2 x i1> %pg,102 ptr %base,103 <vscale x 2 x i32> %b)104 %res = zext <vscale x 2 x i16> %load to <vscale x 2 x i64>105 ret <vscale x 2 x i64> %res106}107 108; LD1W109define <vscale x 4 x i32> @gld1w_s_uxtw(<vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %b) {110; CHECK-LABEL: gld1w_s_uxtw:111; CHECK: // %bb.0:112; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, z0.s, uxtw]113; CHECK-NEXT: ret114 %load = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i32(<vscale x 4 x i1> %pg,115 ptr %base,116 <vscale x 4 x i32> %b)117 ret <vscale x 4 x i32> %load118}119 120define <vscale x 4 x i32> @gld1w_s_sxtw(<vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %b) {121; CHECK-LABEL: gld1w_s_sxtw:122; CHECK: // %bb.0:123; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, z0.s, sxtw]124; CHECK-NEXT: ret125 %load = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i32(<vscale x 4 x i1> %pg,126 ptr %base,127 <vscale x 4 x i32> %b)128 ret <vscale x 4 x i32> %load129}130 131define <vscale x 2 x i64> @gld1w_d_uxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {132; CHECK-LABEL: gld1w_d_uxtw:133; CHECK: // %bb.0:134; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0, z0.d, uxtw]135; CHECK-NEXT: ret136 %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i32(<vscale x 2 x i1> %pg,137 ptr %base,138 <vscale x 2 x i32> %b)139 %res = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>140 ret <vscale x 2 x i64> %res141}142 143define <vscale x 2 x i64> @gld1w_d_sxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {144; CHECK-LABEL: gld1w_d_sxtw:145; CHECK: // %bb.0:146; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0, z0.d, sxtw]147; CHECK-NEXT: ret148 %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i32(<vscale x 2 x i1> %pg,149 ptr %base,150 <vscale x 2 x i32> %b)151 %res = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>152 ret <vscale x 2 x i64> %res153}154 155define <vscale x 4 x float> @gld1w_s_uxtw_float(<vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %b) {156; CHECK-LABEL: gld1w_s_uxtw_float:157; CHECK: // %bb.0:158; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, z0.s, uxtw]159; CHECK-NEXT: ret160 %load = call <vscale x 4 x float> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4f32(<vscale x 4 x i1> %pg,161 ptr %base,162 <vscale x 4 x i32> %b)163 ret <vscale x 4 x float> %load164}165 166define <vscale x 4 x float> @gld1w_s_sxtw_float(<vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %b) {167; CHECK-LABEL: gld1w_s_sxtw_float:168; CHECK: // %bb.0:169; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, z0.s, sxtw]170; CHECK-NEXT: ret171 %load = call <vscale x 4 x float> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4f32(<vscale x 4 x i1> %pg,172 ptr %base,173 <vscale x 4 x i32> %b)174 ret <vscale x 4 x float> %load175}176 177; LD1D178define <vscale x 2 x i64> @gld1d_d_uxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {179; CHECK-LABEL: gld1d_d_uxtw:180; CHECK: // %bb.0:181; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, z0.d, uxtw]182; CHECK-NEXT: ret183 %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i64(<vscale x 2 x i1> %pg,184 ptr %base,185 <vscale x 2 x i32> %b)186 ret <vscale x 2 x i64> %load187}188 189define <vscale x 2 x i64> @gld1d_d_sxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {190; CHECK-LABEL: gld1d_d_sxtw:191; CHECK: // %bb.0:192; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, z0.d, sxtw]193; CHECK-NEXT: ret194 %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i64(<vscale x 2 x i1> %pg,195 ptr %base,196 <vscale x 2 x i32> %b)197 ret <vscale x 2 x i64> %load198}199 200define <vscale x 2 x double> @gld1d_d_uxtw_double(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {201; CHECK-LABEL: gld1d_d_uxtw_double:202; CHECK: // %bb.0:203; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, z0.d, uxtw]204; CHECK-NEXT: ret205 %load = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2f64(<vscale x 2 x i1> %pg,206 ptr %base,207 <vscale x 2 x i32> %b)208 ret <vscale x 2 x double> %load209}210 211define <vscale x 2 x double> @gld1d_d_sxtw_double(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {212; CHECK-LABEL: gld1d_d_sxtw_double:213; CHECK: // %bb.0:214; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, z0.d, sxtw]215; CHECK-NEXT: ret216 %load = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2f64(<vscale x 2 x i1> %pg,217 ptr %base,218 <vscale x 2 x i32> %b)219 ret <vscale x 2 x double> %load220}221 222;223; LD1SB, LD1SW, LD1SH: base + 32-bit unscaled offset, sign (sxtw) or zero224; (uxtw) extended to 64 bits.225; e.g. ld1sh { z0.d }, p0/z, [x0, z0.d, uxtw]226;227 228; LD1SB229define <vscale x 4 x i32> @gld1sb_s_uxtw(<vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %b) {230; CHECK-LABEL: gld1sb_s_uxtw:231; CHECK: // %bb.0:232; CHECK-NEXT: ld1sb { z0.s }, p0/z, [x0, z0.s, uxtw]233; CHECK-NEXT: ret234 %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i8(<vscale x 4 x i1> %pg,235 ptr %base,236 <vscale x 4 x i32> %b)237 %res = sext <vscale x 4 x i8> %load to <vscale x 4 x i32>238 ret <vscale x 4 x i32> %res239}240 241define <vscale x 4 x i32> @gld1sb_s_sxtw(<vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %b) {242; CHECK-LABEL: gld1sb_s_sxtw:243; CHECK: // %bb.0:244; CHECK-NEXT: ld1sb { z0.s }, p0/z, [x0, z0.s, sxtw]245; CHECK-NEXT: ret246 %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i8(<vscale x 4 x i1> %pg,247 ptr %base,248 <vscale x 4 x i32> %b)249 %res = sext <vscale x 4 x i8> %load to <vscale x 4 x i32>250 ret <vscale x 4 x i32> %res251}252 253define <vscale x 2 x i64> @gld1sb_d_uxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {254; CHECK-LABEL: gld1sb_d_uxtw:255; CHECK: // %bb.0:256; CHECK-NEXT: ld1sb { z0.d }, p0/z, [x0, z0.d, uxtw]257; CHECK-NEXT: ret258 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i8(<vscale x 2 x i1> %pg,259 ptr %base,260 <vscale x 2 x i32> %b)261 %res = sext <vscale x 2 x i8> %load to <vscale x 2 x i64>262 ret <vscale x 2 x i64> %res263}264 265define <vscale x 2 x i64> @gld1sb_d_sxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {266; CHECK-LABEL: gld1sb_d_sxtw:267; CHECK: // %bb.0:268; CHECK-NEXT: ld1sb { z0.d }, p0/z, [x0, z0.d, sxtw]269; CHECK-NEXT: ret270 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i8(<vscale x 2 x i1> %pg,271 ptr %base,272 <vscale x 2 x i32> %b)273 %res = sext <vscale x 2 x i8> %load to <vscale x 2 x i64>274 ret <vscale x 2 x i64> %res275}276 277; LD1SH278define <vscale x 4 x i32> @gld1sh_s_uxtw(<vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %b) {279; CHECK-LABEL: gld1sh_s_uxtw:280; CHECK: // %bb.0:281; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0, z0.s, uxtw]282; CHECK-NEXT: ret283 %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i16(<vscale x 4 x i1> %pg,284 ptr %base,285 <vscale x 4 x i32> %b)286 %res = sext <vscale x 4 x i16> %load to <vscale x 4 x i32>287 ret <vscale x 4 x i32> %res288}289 290define <vscale x 4 x i32> @gld1sh_s_sxtw(<vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %b) {291; CHECK-LABEL: gld1sh_s_sxtw:292; CHECK: // %bb.0:293; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0, z0.s, sxtw]294; CHECK-NEXT: ret295 %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i16(<vscale x 4 x i1> %pg,296 ptr %base,297 <vscale x 4 x i32> %b)298 %res = sext <vscale x 4 x i16> %load to <vscale x 4 x i32>299 ret <vscale x 4 x i32> %res300}301 302define <vscale x 2 x i64> @gld1sh_d_uxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {303; CHECK-LABEL: gld1sh_d_uxtw:304; CHECK: // %bb.0:305; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x0, z0.d, uxtw]306; CHECK-NEXT: ret307 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i16(<vscale x 2 x i1> %pg,308 ptr %base,309 <vscale x 2 x i32> %b)310 %res = sext <vscale x 2 x i16> %load to <vscale x 2 x i64>311 ret <vscale x 2 x i64> %res312}313 314define <vscale x 2 x i64> @gld1sh_d_sxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {315; CHECK-LABEL: gld1sh_d_sxtw:316; CHECK: // %bb.0:317; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x0, z0.d, sxtw]318; CHECK-NEXT: ret319 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i16(<vscale x 2 x i1> %pg,320 ptr %base,321 <vscale x 2 x i32> %b)322 %res = sext <vscale x 2 x i16> %load to <vscale x 2 x i64>323 ret <vscale x 2 x i64> %res324}325 326; LD1SW327define <vscale x 2 x i64> @gld1sw_d_uxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {328; CHECK-LABEL: gld1sw_d_uxtw:329; CHECK: // %bb.0:330; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0, z0.d, uxtw]331; CHECK-NEXT: ret332 %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i32(<vscale x 2 x i1> %pg,333 ptr %base,334 <vscale x 2 x i32> %b)335 %res = sext <vscale x 2 x i32> %load to <vscale x 2 x i64>336 ret <vscale x 2 x i64> %res337}338 339define <vscale x 2 x i64> @gld1sw_d_sxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %b) {340; CHECK-LABEL: gld1sw_d_sxtw:341; CHECK: // %bb.0:342; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0, z0.d, sxtw]343; CHECK-NEXT: ret344 %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i32(<vscale x 2 x i1> %pg,345 ptr %base,346 <vscale x 2 x i32> %b)347 %res = sext <vscale x 2 x i32> %load to <vscale x 2 x i64>348 ret <vscale x 2 x i64> %res349}350 351; LD1B/LD1SB352declare <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i8(<vscale x 4 x i1>, ptr, <vscale x 4 x i32>)353declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i8(<vscale x 2 x i1>, ptr, <vscale x 2 x i32>)354declare <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i8(<vscale x 4 x i1>, ptr, <vscale x 4 x i32>)355declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i8(<vscale x 2 x i1>, ptr, <vscale x 2 x i32>)356 357; LD1H/LD1SH358declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i16(<vscale x 4 x i1>, ptr, <vscale x 4 x i32>)359declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i16(<vscale x 2 x i1>, ptr, <vscale x 2 x i32>)360declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i16(<vscale x 4 x i1>, ptr, <vscale x 4 x i32>)361declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i16(<vscale x 2 x i1>, ptr, <vscale x 2 x i32>)362 363; LD1W/LD1SW364declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i32(<vscale x 4 x i1>, ptr, <vscale x 4 x i32>)365declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i32(<vscale x 2 x i1>, ptr, <vscale x 2 x i32>)366declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i32(<vscale x 4 x i1>, ptr, <vscale x 4 x i32>)367declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i32(<vscale x 2 x i1>, ptr, <vscale x 2 x i32>)368 369declare <vscale x 4 x float> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4f32(<vscale x 4 x i1>, ptr, <vscale x 4 x i32>)370declare <vscale x 4 x float> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4f32(<vscale x 4 x i1>, ptr, <vscale x 4 x i32>)371 372; LD1D373declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i64(<vscale x 2 x i1>, ptr, <vscale x 2 x i32>)374declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i64(<vscale x 2 x i1>, ptr, <vscale x 2 x i32>)375 376declare <vscale x 2 x double> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2f64(<vscale x 2 x i1>, ptr, <vscale x 2 x i32>)377declare <vscale x 2 x double> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2f64(<vscale x 2 x i1>, ptr, <vscale x 2 x i32>)378