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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4;5; LD1B, LD1W, LD1H, LD1D: base + 64-bit unscaled offset6; e.g. ld1h { z0.d }, p0/z, [x0, z0.d]7;8 9define <vscale x 2 x i64> @gld1b_d(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %b) {10; CHECK-LABEL: gld1b_d:11; CHECK: // %bb.0:12; CHECK-NEXT: ld1b { z0.d }, p0/z, [x0, z0.d]13; CHECK-NEXT: ret14 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.nxv2i8(<vscale x 2 x i1> %pg,15 ptr %base,16 <vscale x 2 x i64> %b)17 %res = zext <vscale x 2 x i8> %load to <vscale x 2 x i64>18 ret <vscale x 2 x i64> %res19}20 21define <vscale x 2 x i64> @gld1h_d(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %b) {22; CHECK-LABEL: gld1h_d:23; CHECK: // %bb.0:24; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, z0.d]25; CHECK-NEXT: ret26 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.nxv2i16(<vscale x 2 x i1> %pg,27 ptr %base,28 <vscale x 2 x i64> %b)29 %res = zext <vscale x 2 x i16> %load to <vscale x 2 x i64>30 ret <vscale x 2 x i64> %res31}32 33define <vscale x 2 x i64> @gld1w_d(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %offsets) {34; CHECK-LABEL: gld1w_d:35; CHECK: // %bb.0:36; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0, z0.d]37; CHECK-NEXT: ret38 %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32(<vscale x 2 x i1> %pg,39 ptr %base,40 <vscale x 2 x i64> %offsets)41 %res = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>42 ret <vscale x 2 x i64> %res43}44 45define <vscale x 2 x i64> @gld1d_d(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %b) {46; CHECK-LABEL: gld1d_d:47; CHECK: // %bb.0:48; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, z0.d]49; CHECK-NEXT: ret50 %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.nxv2i64(<vscale x 2 x i1> %pg,51 ptr %base,52 <vscale x 2 x i64> %b)53 ret <vscale x 2 x i64> %load54}55 56define <vscale x 2 x double> @gld1d_d_double(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %b) {57; CHECK-LABEL: gld1d_d_double:58; CHECK: // %bb.0:59; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, z0.d]60; CHECK-NEXT: ret61 %load = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.gather.nxv2f64(<vscale x 2 x i1> %pg,62 ptr %base,63 <vscale x 2 x i64> %b)64 ret <vscale x 2 x double> %load65}66 67;68; LD1SB, LD1SW, LD1SH: base + 64-bit unscaled offset69; e.g. ld1sh { z0.d }, p0/z, [x0, z0.d]70;71 72define <vscale x 2 x i64> @gld1sb_d(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %b) {73; CHECK-LABEL: gld1sb_d:74; CHECK: // %bb.0:75; CHECK-NEXT: ld1sb { z0.d }, p0/z, [x0, z0.d]76; CHECK-NEXT: ret77 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.nxv2i8(<vscale x 2 x i1> %pg,78 ptr %base,79 <vscale x 2 x i64> %b)80 %res = sext <vscale x 2 x i8> %load to <vscale x 2 x i64>81 ret <vscale x 2 x i64> %res82}83 84define <vscale x 2 x i64> @gld1sh_d(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %b) {85; CHECK-LABEL: gld1sh_d:86; CHECK: // %bb.0:87; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x0, z0.d]88; CHECK-NEXT: ret89 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.nxv2i16(<vscale x 2 x i1> %pg,90 ptr %base,91 <vscale x 2 x i64> %b)92 %res = sext <vscale x 2 x i16> %load to <vscale x 2 x i64>93 ret <vscale x 2 x i64> %res94}95 96define <vscale x 2 x i64> @gld1sw_d(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %offsets) {97; CHECK-LABEL: gld1sw_d:98; CHECK: // %bb.0:99; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0, z0.d]100; CHECK-NEXT: ret101 %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32(<vscale x 2 x i1> %pg,102 ptr %base,103 <vscale x 2 x i64> %offsets)104 %res = sext <vscale x 2 x i32> %load to <vscale x 2 x i64>105 ret <vscale x 2 x i64> %res106}107 108;109; LD1B, LD1W, LD1H, LD1D: base + 64-bit sxtw'd unscaled offset110; e.g. ld1h { z0.d }, p0/z, [x0, z0.d, sxtw]111;112 113define <vscale x 2 x i64> @gld1b_d_sxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %b) {114; CHECK-LABEL: gld1b_d_sxtw:115; CHECK: // %bb.0:116; CHECK-NEXT: ld1b { z0.d }, p0/z, [x0, z0.d, sxtw]117; CHECK-NEXT: ret118 %sxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> poison,119 <vscale x 2 x i1> %pg,120 <vscale x 2 x i64> %b)121 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.nxv2i8(<vscale x 2 x i1> %pg,122 ptr %base,123 <vscale x 2 x i64> %sxtw)124 %res = zext <vscale x 2 x i8> %load to <vscale x 2 x i64>125 ret <vscale x 2 x i64> %res126}127 128define <vscale x 2 x i64> @gld1h_d_sxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %b) {129; CHECK-LABEL: gld1h_d_sxtw:130; CHECK: // %bb.0:131; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, z0.d, sxtw]132; CHECK-NEXT: ret133 %sxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> poison,134 <vscale x 2 x i1> %pg,135 <vscale x 2 x i64> %b)136 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.nxv2i16(<vscale x 2 x i1> %pg,137 ptr %base,138 <vscale x 2 x i64> %sxtw)139 %res = zext <vscale x 2 x i16> %load to <vscale x 2 x i64>140 ret <vscale x 2 x i64> %res141}142 143define <vscale x 2 x i64> @gld1w_d_sxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %offsets) {144; CHECK-LABEL: gld1w_d_sxtw:145; CHECK: // %bb.0:146; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0, z0.d, sxtw]147; CHECK-NEXT: ret148 %sxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> poison,149 <vscale x 2 x i1> %pg,150 <vscale x 2 x i64> %offsets)151 %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32(<vscale x 2 x i1> %pg,152 ptr %base,153 <vscale x 2 x i64> %sxtw)154 %res = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>155 ret <vscale x 2 x i64> %res156}157 158define <vscale x 2 x i64> @gld1d_d_sxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %b) {159; CHECK-LABEL: gld1d_d_sxtw:160; CHECK: // %bb.0:161; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, z0.d, sxtw]162; CHECK-NEXT: ret163 %sxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> poison,164 <vscale x 2 x i1> %pg,165 <vscale x 2 x i64> %b)166 %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.nxv2i64(<vscale x 2 x i1> %pg,167 ptr %base,168 <vscale x 2 x i64> %sxtw)169 ret <vscale x 2 x i64> %load170}171 172define <vscale x 2 x double> @gld1d_d_double_sxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %b) {173; CHECK-LABEL: gld1d_d_double_sxtw:174; CHECK: // %bb.0:175; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, z0.d, sxtw]176; CHECK-NEXT: ret177 %sxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> poison,178 <vscale x 2 x i1> %pg,179 <vscale x 2 x i64> %b)180 %load = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.gather.nxv2f64(<vscale x 2 x i1> %pg,181 ptr %base,182 <vscale x 2 x i64> %sxtw)183 ret <vscale x 2 x double> %load184}185 186;187; LD1SB, LD1SW, LD1SH: base + 64-bit sxtw'd unscaled offset188; e.g. ld1sh { z0.d }, p0/z, [x0, z0.d]189;190 191define <vscale x 2 x i64> @gld1sb_d_sxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %b) {192; CHECK-LABEL: gld1sb_d_sxtw:193; CHECK: // %bb.0:194; CHECK-NEXT: ld1sb { z0.d }, p0/z, [x0, z0.d, sxtw]195; CHECK-NEXT: ret196 %sxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> poison,197 <vscale x 2 x i1> %pg,198 <vscale x 2 x i64> %b)199 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.nxv2i8(<vscale x 2 x i1> %pg,200 ptr %base,201 <vscale x 2 x i64> %sxtw)202 %res = sext <vscale x 2 x i8> %load to <vscale x 2 x i64>203 ret <vscale x 2 x i64> %res204}205 206define <vscale x 2 x i64> @gld1sh_d_sxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %b) {207; CHECK-LABEL: gld1sh_d_sxtw:208; CHECK: // %bb.0:209; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x0, z0.d, sxtw]210; CHECK-NEXT: ret211 %sxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> poison,212 <vscale x 2 x i1> %pg,213 <vscale x 2 x i64> %b)214 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.nxv2i16(<vscale x 2 x i1> %pg,215 ptr %base,216 <vscale x 2 x i64> %sxtw)217 %res = sext <vscale x 2 x i16> %load to <vscale x 2 x i64>218 ret <vscale x 2 x i64> %res219}220 221define <vscale x 2 x i64> @gld1sw_d_sxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %offsets) {222; CHECK-LABEL: gld1sw_d_sxtw:223; CHECK: // %bb.0:224; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0, z0.d, sxtw]225; CHECK-NEXT: ret226 %sxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> poison,227 <vscale x 2 x i1> %pg,228 <vscale x 2 x i64> %offsets)229 %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32(<vscale x 2 x i1> %pg,230 ptr %base,231 <vscale x 2 x i64> %sxtw)232 %res = sext <vscale x 2 x i32> %load to <vscale x 2 x i64>233 ret <vscale x 2 x i64> %res234}235 236;237; LD1B, LD1W, LD1H, LD1D: base + 64-bit uxtw'd unscaled offset238; e.g. ld1h { z0.d }, p0/z, [x0, z0.d, uxtw]239;240 241define <vscale x 2 x i64> @gld1b_d_uxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %b) {242; CHECK-LABEL: gld1b_d_uxtw:243; CHECK: // %bb.0:244; CHECK-NEXT: ld1b { z0.d }, p0/z, [x0, z0.d, uxtw]245; CHECK-NEXT: ret246 %uxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> poison,247 <vscale x 2 x i1> %pg,248 <vscale x 2 x i64> %b)249 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.nxv2i8(<vscale x 2 x i1> %pg,250 ptr %base,251 <vscale x 2 x i64> %uxtw)252 %res = zext <vscale x 2 x i8> %load to <vscale x 2 x i64>253 ret <vscale x 2 x i64> %res254}255 256define <vscale x 2 x i64> @gld1h_d_uxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %b) {257; CHECK-LABEL: gld1h_d_uxtw:258; CHECK: // %bb.0:259; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, z0.d, uxtw]260; CHECK-NEXT: ret261 %uxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> poison,262 <vscale x 2 x i1> %pg,263 <vscale x 2 x i64> %b)264 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.nxv2i16(<vscale x 2 x i1> %pg,265 ptr %base,266 <vscale x 2 x i64> %uxtw)267 %res = zext <vscale x 2 x i16> %load to <vscale x 2 x i64>268 ret <vscale x 2 x i64> %res269}270 271define <vscale x 2 x i64> @gld1w_d_uxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %offsets) {272; CHECK-LABEL: gld1w_d_uxtw:273; CHECK: // %bb.0:274; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0, z0.d, uxtw]275; CHECK-NEXT: ret276 %uxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> poison,277 <vscale x 2 x i1> %pg,278 <vscale x 2 x i64> %offsets)279 %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32(<vscale x 2 x i1> %pg,280 ptr %base,281 <vscale x 2 x i64> %uxtw)282 %res = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>283 ret <vscale x 2 x i64> %res284}285 286define <vscale x 2 x i64> @gld1d_d_uxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %b) {287; CHECK-LABEL: gld1d_d_uxtw:288; CHECK: // %bb.0:289; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, z0.d, uxtw]290; CHECK-NEXT: ret291 %uxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> poison,292 <vscale x 2 x i1> %pg,293 <vscale x 2 x i64> %b)294 %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.nxv2i64(<vscale x 2 x i1> %pg,295 ptr %base,296 <vscale x 2 x i64> %uxtw)297 ret <vscale x 2 x i64> %load298}299 300define <vscale x 2 x double> @gld1d_d_double_uxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %b) {301; CHECK-LABEL: gld1d_d_double_uxtw:302; CHECK: // %bb.0:303; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, z0.d, uxtw]304; CHECK-NEXT: ret305 %uxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> poison,306 <vscale x 2 x i1> %pg,307 <vscale x 2 x i64> %b)308 %load = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.gather.nxv2f64(<vscale x 2 x i1> %pg,309 ptr %base,310 <vscale x 2 x i64> %uxtw)311 ret <vscale x 2 x double> %load312}313 314;315; LD1SB, LD1SW, LD1SH: base + 64-bit uxtw'd unscaled offset316; e.g. ld1sh { z0.d }, p0/z, [x0, z0.d]317;318 319define <vscale x 2 x i64> @gld1sb_d_uxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %b) {320; CHECK-LABEL: gld1sb_d_uxtw:321; CHECK: // %bb.0:322; CHECK-NEXT: ld1sb { z0.d }, p0/z, [x0, z0.d, uxtw]323; CHECK-NEXT: ret324 %uxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> poison,325 <vscale x 2 x i1> %pg,326 <vscale x 2 x i64> %b)327 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.nxv2i8(<vscale x 2 x i1> %pg,328 ptr %base,329 <vscale x 2 x i64> %uxtw)330 %res = sext <vscale x 2 x i8> %load to <vscale x 2 x i64>331 ret <vscale x 2 x i64> %res332}333 334define <vscale x 2 x i64> @gld1sh_d_uxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %b) {335; CHECK-LABEL: gld1sh_d_uxtw:336; CHECK: // %bb.0:337; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x0, z0.d, uxtw]338; CHECK-NEXT: ret339 %uxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> poison,340 <vscale x 2 x i1> %pg,341 <vscale x 2 x i64> %b)342 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.nxv2i16(<vscale x 2 x i1> %pg,343 ptr %base,344 <vscale x 2 x i64> %uxtw)345 %res = sext <vscale x 2 x i16> %load to <vscale x 2 x i64>346 ret <vscale x 2 x i64> %res347}348 349define <vscale x 2 x i64> @gld1sw_d_uxtw(<vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %offsets) {350; CHECK-LABEL: gld1sw_d_uxtw:351; CHECK: // %bb.0:352; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0, z0.d, uxtw]353; CHECK-NEXT: ret354 %uxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> poison,355 <vscale x 2 x i1> %pg,356 <vscale x 2 x i64> %offsets)357 %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32(<vscale x 2 x i1> %pg,358 ptr %base,359 <vscale x 2 x i64> %uxtw)360 %res = sext <vscale x 2 x i32> %load to <vscale x 2 x i64>361 ret <vscale x 2 x i64> %res362}363 364declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.nxv2i8(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>)365declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.nxv2i16(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>)366declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>)367declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.nxv2i64(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>)368declare <vscale x 2 x double> @llvm.aarch64.sve.ld1.gather.nxv2f64(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>)369 370declare <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)371declare <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)372