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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -mattr=+use-experimental-zeroing-pseudos < %s | FileCheck %s3 4;; ASR5define <vscale x 16 x i8> @asr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %pg) {6; CHECK-LABEL: asr_i8:7; CHECK: // %bb.0:8; CHECK-NEXT: movprfx z0.b, p0/z, z0.b9; CHECK-NEXT: asr z0.b, p0/m, z0.b, #810; CHECK-NEXT: ret11 %vsel = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer12 %res = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %vsel, <vscale x 16 x i8> splat(i8 8))13 ret <vscale x 16 x i8> %res14}15 16define <vscale x 8 x i16> @asr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg) {17; CHECK-LABEL: asr_i16:18; CHECK: // %bb.0:19; CHECK-NEXT: movprfx z0.h, p0/z, z0.h20; CHECK-NEXT: asr z0.h, p0/m, z0.h, #1621; CHECK-NEXT: ret22 %vsel = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer23 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %vsel, <vscale x 8 x i16> splat(i16 16))24 ret <vscale x 8 x i16> %res25}26 27define <vscale x 4 x i32> @asr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg) local_unnamed_addr #0 {28; CHECK-LABEL: asr_i32:29; CHECK: // %bb.0:30; CHECK-NEXT: movprfx z0.s, p0/z, z0.s31; CHECK-NEXT: asr z0.s, p0/m, z0.s, #3232; CHECK-NEXT: ret33 %vsel = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer34 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %vsel, <vscale x 4 x i32> splat(i32 32))35 ret <vscale x 4 x i32> %res36}37 38define <vscale x 2 x i64> @asr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg) {39; CHECK-LABEL: asr_i64:40; CHECK: // %bb.0:41; CHECK-NEXT: movprfx z0.d, p0/z, z0.d42; CHECK-NEXT: asr z0.d, p0/m, z0.d, #6443; CHECK-NEXT: ret44 %vsel = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer45 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %vsel, <vscale x 2 x i64> splat(i64 64))46 ret <vscale x 2 x i64> %res47}48 49;; LSL50define <vscale x 16 x i8> @lsl_i8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %pg) {51; CHECK-LABEL: lsl_i8:52; CHECK: // %bb.0:53; CHECK-NEXT: movprfx z0.b, p0/z, z0.b54; CHECK-NEXT: lsl z0.b, p0/m, z0.b, #755; CHECK-NEXT: ret56 %vsel = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer57 %res = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %vsel, <vscale x 16 x i8> splat(i8 7))58 ret <vscale x 16 x i8> %res59}60 61define <vscale x 8 x i16> @lsl_i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg) {62; CHECK-LABEL: lsl_i16:63; CHECK: // %bb.0:64; CHECK-NEXT: movprfx z0.h, p0/z, z0.h65; CHECK-NEXT: lsl z0.h, p0/m, z0.h, #1566; CHECK-NEXT: ret67 %vsel = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer68 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %vsel, <vscale x 8 x i16> splat(i16 15))69 ret <vscale x 8 x i16> %res70}71 72define <vscale x 4 x i32> @lsl_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg) local_unnamed_addr #0 {73; CHECK-LABEL: lsl_i32:74; CHECK: // %bb.0:75; CHECK-NEXT: movprfx z0.s, p0/z, z0.s76; CHECK-NEXT: lsl z0.s, p0/m, z0.s, #3177; CHECK-NEXT: ret78 %vsel = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer79 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %vsel, <vscale x 4 x i32> splat(i32 31))80 ret <vscale x 4 x i32> %res81}82 83define <vscale x 2 x i64> @lsl_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg) {84; CHECK-LABEL: lsl_i64:85; CHECK: // %bb.0:86; CHECK-NEXT: movprfx z0.d, p0/z, z0.d87; CHECK-NEXT: lsl z0.d, p0/m, z0.d, #6388; CHECK-NEXT: ret89 %vsel = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer90 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %vsel, <vscale x 2 x i64> splat(i64 63))91 ret <vscale x 2 x i64> %res92}93 94;; LSR95define <vscale x 16 x i8> @lsr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %pg) {96; CHECK-LABEL: lsr_i8:97; CHECK: // %bb.0:98; CHECK-NEXT: movprfx z0.b, p0/z, z0.b99; CHECK-NEXT: lsr z0.b, p0/m, z0.b, #8100; CHECK-NEXT: ret101 %vsel = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer102 %res = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %vsel, <vscale x 16 x i8> splat(i8 8))103 ret <vscale x 16 x i8> %res104}105 106define <vscale x 8 x i16> @lsr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg) {107; CHECK-LABEL: lsr_i16:108; CHECK: // %bb.0:109; CHECK-NEXT: movprfx z0.h, p0/z, z0.h110; CHECK-NEXT: lsr z0.h, p0/m, z0.h, #16111; CHECK-NEXT: ret112 %vsel = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer113 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %vsel, <vscale x 8 x i16> splat(i16 16))114 ret <vscale x 8 x i16> %res115}116 117define <vscale x 4 x i32> @lsr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg) local_unnamed_addr #0 {118; CHECK-LABEL: lsr_i32:119; CHECK: // %bb.0:120; CHECK-NEXT: movprfx z0.s, p0/z, z0.s121; CHECK-NEXT: lsr z0.s, p0/m, z0.s, #32122; CHECK-NEXT: ret123 %vsel = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer124 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %vsel, <vscale x 4 x i32> splat(i32 32))125 ret <vscale x 4 x i32> %res126}127 128define <vscale x 2 x i64> @lsr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg) {129; CHECK-LABEL: lsr_i64:130; CHECK: // %bb.0:131; CHECK-NEXT: movprfx z0.d, p0/z, z0.d132; CHECK-NEXT: lsr z0.d, p0/m, z0.d, #64133; CHECK-NEXT: ret134 %vsel = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer135 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %vsel, <vscale x 2 x i64> splat(i64 64))136 ret <vscale x 2 x i64> %res137}138 139declare <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)140declare <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)141declare <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)142declare <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)143 144declare <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)145declare <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)146declare <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)147declare <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)148 149declare <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)150declare <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)151declare <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)152declare <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)153