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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4; ADD5 6define <vscale x 16 x i8> @add_i8(<vscale x 16 x i8> %a) {7; CHECK-LABEL: add_i8:8; CHECK: // %bb.0:9; CHECK-NEXT: add z0.b, z0.b, #127 // =0x7f10; CHECK-NEXT: ret11 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)12 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.add.u.nxv16i8(<vscale x 16 x i1> %pg,13 <vscale x 16 x i8> %a,14 <vscale x 16 x i8> splat(i8 127))15 ret <vscale x 16 x i8> %out16}17 18define <vscale x 8 x i16> @add_i16(<vscale x 8 x i16> %a) {19; CHECK-LABEL: add_i16:20; CHECK: // %bb.0:21; CHECK-NEXT: add z0.h, z0.h, #127 // =0x7f22; CHECK-NEXT: ret23 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)24 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.add.u.nxv8i16(<vscale x 8 x i1> %pg,25 <vscale x 8 x i16> %a,26 <vscale x 8 x i16> splat(i16 127))27 ret <vscale x 8 x i16> %out28}29 30define <vscale x 8 x i16> @add_i16_out_of_range(<vscale x 8 x i16> %a) {31; CHECK-LABEL: add_i16_out_of_range:32; CHECK: // %bb.0:33; CHECK-NEXT: dupm z1.b, #0x134; CHECK-NEXT: add z0.h, z0.h, z1.h35; CHECK-NEXT: ret36 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)37 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.add.u.nxv8i16(<vscale x 8 x i1> %pg,38 <vscale x 8 x i16> %a,39 <vscale x 8 x i16> splat(i16 257))40 ret <vscale x 8 x i16> %out41}42 43define <vscale x 4 x i32> @add_i32(<vscale x 4 x i32> %a) {44; CHECK-LABEL: add_i32:45; CHECK: // %bb.0:46; CHECK-NEXT: add z0.s, z0.s, #127 // =0x7f47; CHECK-NEXT: ret48 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)49 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.add.u.nxv4i32(<vscale x 4 x i1> %pg,50 <vscale x 4 x i32> %a,51 <vscale x 4 x i32> splat(i32 127))52 ret <vscale x 4 x i32> %out53}54 55define <vscale x 4 x i32> @add_i32_out_of_range(<vscale x 4 x i32> %a) {56; CHECK-LABEL: add_i32_out_of_range:57; CHECK: // %bb.0:58; CHECK-NEXT: mov w8, #257 // =0x10159; CHECK-NEXT: mov z1.s, w860; CHECK-NEXT: add z0.s, z0.s, z1.s61; CHECK-NEXT: ret62 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)63 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.add.u.nxv4i32(<vscale x 4 x i1> %pg,64 <vscale x 4 x i32> %a,65 <vscale x 4 x i32> splat(i32 257))66 ret <vscale x 4 x i32> %out67}68 69define <vscale x 2 x i64> @add_i64(<vscale x 2 x i64> %a) {70; CHECK-LABEL: add_i64:71; CHECK: // %bb.0:72; CHECK-NEXT: add z0.d, z0.d, #127 // =0x7f73; CHECK-NEXT: ret74 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)75 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.add.u.nxv2i64(<vscale x 2 x i1> %pg,76 <vscale x 2 x i64> %a,77 <vscale x 2 x i64> splat(i64 127))78 ret <vscale x 2 x i64> %out79}80 81define <vscale x 2 x i64> @add_i64_out_of_range(<vscale x 2 x i64> %a) {82; CHECK-LABEL: add_i64_out_of_range:83; CHECK: // %bb.0:84; CHECK-NEXT: mov w8, #257 // =0x10185; CHECK-NEXT: mov z1.d, x886; CHECK-NEXT: add z0.d, z0.d, z1.d87; CHECK-NEXT: ret88 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)89 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.add.u.nxv2i64(<vscale x 2 x i1> %pg,90 <vscale x 2 x i64> %a,91 <vscale x 2 x i64> splat(i64 257))92 ret <vscale x 2 x i64> %out93}94 95; SUB96 97define <vscale x 16 x i8> @sub_i8(<vscale x 16 x i8> %a) {98; CHECK-LABEL: sub_i8:99; CHECK: // %bb.0:100; CHECK-NEXT: sub z0.b, z0.b, #127 // =0x7f101; CHECK-NEXT: ret102 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)103 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.u.nxv16i8(<vscale x 16 x i1> %pg,104 <vscale x 16 x i8> %a,105 <vscale x 16 x i8> splat(i8 127))106 ret <vscale x 16 x i8> %out107}108 109define <vscale x 8 x i16> @sub_i16(<vscale x 8 x i16> %a) {110; CHECK-LABEL: sub_i16:111; CHECK: // %bb.0:112; CHECK-NEXT: sub z0.h, z0.h, #127 // =0x7f113; CHECK-NEXT: ret114 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)115 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.u.nxv8i16(<vscale x 8 x i1> %pg,116 <vscale x 8 x i16> %a,117 <vscale x 8 x i16> splat(i16 127))118 ret <vscale x 8 x i16> %out119}120 121define <vscale x 8 x i16> @sub_i16_out_of_range(<vscale x 8 x i16> %a) {122; CHECK-LABEL: sub_i16_out_of_range:123; CHECK: // %bb.0:124; CHECK-NEXT: dupm z1.b, #0x1125; CHECK-NEXT: sub z0.h, z0.h, z1.h126; CHECK-NEXT: ret127 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)128 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.u.nxv8i16(<vscale x 8 x i1> %pg,129 <vscale x 8 x i16> %a,130 <vscale x 8 x i16> splat(i16 257))131 ret <vscale x 8 x i16> %out132}133 134define <vscale x 4 x i32> @sub_i32(<vscale x 4 x i32> %a) {135; CHECK-LABEL: sub_i32:136; CHECK: // %bb.0:137; CHECK-NEXT: sub z0.s, z0.s, #127 // =0x7f138; CHECK-NEXT: ret139 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)140 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> %pg,141 <vscale x 4 x i32> %a,142 <vscale x 4 x i32> splat(i32 127))143 ret <vscale x 4 x i32> %out144}145 146define <vscale x 4 x i32> @sub_i32_out_of_range(<vscale x 4 x i32> %a) {147; CHECK-LABEL: sub_i32_out_of_range:148; CHECK: // %bb.0:149; CHECK-NEXT: mov w8, #257 // =0x101150; CHECK-NEXT: mov z1.s, w8151; CHECK-NEXT: sub z0.s, z0.s, z1.s152; CHECK-NEXT: ret153 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)154 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> %pg,155 <vscale x 4 x i32> %a,156 <vscale x 4 x i32> splat(i32 257))157 ret <vscale x 4 x i32> %out158}159 160define <vscale x 2 x i64> @sub_i64(<vscale x 2 x i64> %a) {161; CHECK-LABEL: sub_i64:162; CHECK: // %bb.0:163; CHECK-NEXT: sub z0.d, z0.d, #127 // =0x7f164; CHECK-NEXT: ret165 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)166 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.u.nxv2i64(<vscale x 2 x i1> %pg,167 <vscale x 2 x i64> %a,168 <vscale x 2 x i64> splat(i64 127))169 ret <vscale x 2 x i64> %out170}171 172define <vscale x 2 x i64> @sub_i64_out_of_range(<vscale x 2 x i64> %a) {173; CHECK-LABEL: sub_i64_out_of_range:174; CHECK: // %bb.0:175; CHECK-NEXT: mov w8, #257 // =0x101176; CHECK-NEXT: mov z1.d, x8177; CHECK-NEXT: sub z0.d, z0.d, z1.d178; CHECK-NEXT: ret179 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)180 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.u.nxv2i64(<vscale x 2 x i1> %pg,181 <vscale x 2 x i64> %a,182 <vscale x 2 x i64> splat(i64 257))183 ret <vscale x 2 x i64> %out184}185 186; As sub_i32 but where pg is i8 based and thus compatible for i32.187define <vscale x 4 x i32> @sub_i32_ptrue_all_b(<vscale x 4 x i32> %a) #0 {188; CHECK-LABEL: sub_i32_ptrue_all_b:189; CHECK: // %bb.0:190; CHECK-NEXT: sub z0.s, z0.s, #1 // =0x1191; CHECK-NEXT: ret192 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)193 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)194 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)195 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> %pg.s,196 <vscale x 4 x i32> %a,197 <vscale x 4 x i32> %b)198 ret <vscale x 4 x i32> %out199}200 201; As sub_i32 but where pg is i16 based and thus compatible for i32.202define <vscale x 4 x i32> @sub_i32_ptrue_all_h(<vscale x 4 x i32> %a) #0 {203; CHECK-LABEL: sub_i32_ptrue_all_h:204; CHECK: // %bb.0:205; CHECK-NEXT: sub z0.s, z0.s, #1 // =0x1206; CHECK-NEXT: ret207 %pg.h = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)208 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %pg.h)209 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)210 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)211 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> %pg.s,212 <vscale x 4 x i32> %a,213 <vscale x 4 x i32> %b)214 ret <vscale x 4 x i32> %out215}216 217; As sub_i32 but where pg is i64 based, which is not compatibile for i32 and218; thus inactive lanes are important and the immediate form cannot be used.219define <vscale x 4 x i32> @sub_i32_ptrue_all_d(<vscale x 4 x i32> %a) #0 {220; CHECK-LABEL: sub_i32_ptrue_all_d:221; CHECK: // %bb.0:222; CHECK-NEXT: mov z1.s, #1 // =0x1223; CHECK-NEXT: ptrue p0.d224; CHECK-NEXT: sub z0.s, p0/m, z0.s, z1.s225; CHECK-NEXT: ret226 %pg.d = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)227 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg.d)228 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)229 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)230 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1> %pg.s,231 <vscale x 4 x i32> %a,232 <vscale x 4 x i32> %b)233 ret <vscale x 4 x i32> %out234}235 236; SUBR237 238define <vscale x 16 x i8> @subr_i8(<vscale x 16 x i8> %a) {239; CHECK-LABEL: subr_i8:240; CHECK: // %bb.0:241; CHECK-NEXT: subr z0.b, z0.b, #127 // =0x7f242; CHECK-NEXT: ret243 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)244 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1> %pg,245 <vscale x 16 x i8> %a,246 <vscale x 16 x i8> splat(i8 127))247 ret <vscale x 16 x i8> %out248}249 250define <vscale x 8 x i16> @subr_i16(<vscale x 8 x i16> %a) {251; CHECK-LABEL: subr_i16:252; CHECK: // %bb.0:253; CHECK-NEXT: subr z0.h, z0.h, #127 // =0x7f254; CHECK-NEXT: ret255 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)256 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1> %pg,257 <vscale x 8 x i16> %a,258 <vscale x 8 x i16> splat(i16 127))259 ret <vscale x 8 x i16> %out260}261 262define <vscale x 8 x i16> @subr_i16_out_of_range(<vscale x 8 x i16> %a) {263; CHECK-LABEL: subr_i16_out_of_range:264; CHECK: // %bb.0:265; CHECK-NEXT: dupm z1.b, #0x1266; CHECK-NEXT: sub z0.h, z1.h, z0.h267; CHECK-NEXT: ret268 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)269 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1> %pg,270 <vscale x 8 x i16> %a,271 <vscale x 8 x i16> splat(i16 257))272 ret <vscale x 8 x i16> %out273}274 275define <vscale x 4 x i32> @subr_i32(<vscale x 4 x i32> %a) {276; CHECK-LABEL: subr_i32:277; CHECK: // %bb.0:278; CHECK-NEXT: subr z0.s, z0.s, #127 // =0x7f279; CHECK-NEXT: ret280 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)281 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %pg,282 <vscale x 4 x i32> %a,283 <vscale x 4 x i32> splat(i32 127))284 ret <vscale x 4 x i32> %out285}286 287define <vscale x 4 x i32> @subr_i32_out_of_range(<vscale x 4 x i32> %a) {288; CHECK-LABEL: subr_i32_out_of_range:289; CHECK: // %bb.0:290; CHECK-NEXT: mov w8, #257 // =0x101291; CHECK-NEXT: mov z1.s, w8292; CHECK-NEXT: sub z0.s, z1.s, z0.s293; CHECK-NEXT: ret294 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)295 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %pg,296 <vscale x 4 x i32> %a,297 <vscale x 4 x i32> splat(i32 257))298 ret <vscale x 4 x i32> %out299}300 301define <vscale x 2 x i64> @subr_i64(<vscale x 2 x i64> %a) {302; CHECK-LABEL: subr_i64:303; CHECK: // %bb.0:304; CHECK-NEXT: subr z0.d, z0.d, #127 // =0x7f305; CHECK-NEXT: ret306 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)307 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1> %pg,308 <vscale x 2 x i64> %a,309 <vscale x 2 x i64> splat(i64 127))310 ret <vscale x 2 x i64> %out311}312 313define <vscale x 2 x i64> @subr_i64_out_of_range(<vscale x 2 x i64> %a) {314; CHECK-LABEL: subr_i64_out_of_range:315; CHECK: // %bb.0:316; CHECK-NEXT: mov w8, #257 // =0x101317; CHECK-NEXT: mov z1.d, x8318; CHECK-NEXT: sub z0.d, z1.d, z0.d319; CHECK-NEXT: ret320 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)321 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1> %pg,322 <vscale x 2 x i64> %a,323 <vscale x 2 x i64> splat(i64 257))324 ret <vscale x 2 x i64> %out325}326 327; As subr_i32 but where pg is i8 based and thus compatible for i32.328define <vscale x 4 x i32> @subr_i32_ptrue_all_b(<vscale x 4 x i32> %a) #0 {329; CHECK-LABEL: subr_i32_ptrue_all_b:330; CHECK: // %bb.0:331; CHECK-NEXT: subr z0.s, z0.s, #1 // =0x1332; CHECK-NEXT: ret333 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)334 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)335 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)336 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %pg.s,337 <vscale x 4 x i32> %a,338 <vscale x 4 x i32> %b)339 ret <vscale x 4 x i32> %out340}341 342; As subr_i32 but where pg is i16 based and thus compatible for i32.343define <vscale x 4 x i32> @subr_i32_ptrue_all_h(<vscale x 4 x i32> %a) #0 {344; CHECK-LABEL: subr_i32_ptrue_all_h:345; CHECK: // %bb.0:346; CHECK-NEXT: subr z0.s, z0.s, #1 // =0x1347; CHECK-NEXT: ret348 %pg.h = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)349 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %pg.h)350 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)351 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)352 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %pg.s,353 <vscale x 4 x i32> %a,354 <vscale x 4 x i32> %b)355 ret <vscale x 4 x i32> %out356}357 358; As subr_i32 but where pg is i64 based, which is not compatibile for i32 and359; thus inactive lanes are important and the immediate form cannot be used.360define <vscale x 4 x i32> @subr_i32_ptrue_all_d(<vscale x 4 x i32> %a) #0 {361; CHECK-LABEL: subr_i32_ptrue_all_d:362; CHECK: // %bb.0:363; CHECK-NEXT: mov z1.s, #1 // =0x1364; CHECK-NEXT: ptrue p0.d365; CHECK-NEXT: subr z0.s, p0/m, z0.s, z1.s366; CHECK-NEXT: ret367 %pg.d = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)368 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg.d)369 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)370 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)371 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %pg.s,372 <vscale x 4 x i32> %a,373 <vscale x 4 x i32> %b)374 ret <vscale x 4 x i32> %out375}376 377; SMAX378 379define <vscale x 16 x i8> @smax_i8(<vscale x 16 x i8> %a) {380; CHECK-LABEL: smax_i8:381; CHECK: // %bb.0:382; CHECK-NEXT: smax z0.b, z0.b, #-128383; CHECK-NEXT: ret384 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)385 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.smax.u.nxv16i8(<vscale x 16 x i1> %pg,386 <vscale x 16 x i8> %a,387 <vscale x 16 x i8> splat(i8 -128))388 ret <vscale x 16 x i8> %out389}390 391define <vscale x 8 x i16> @smax_i16(<vscale x 8 x i16> %a) {392; CHECK-LABEL: smax_i16:393; CHECK: // %bb.0:394; CHECK-NEXT: smax z0.h, z0.h, #127395; CHECK-NEXT: ret396 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)397 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.smax.u.nxv8i16(<vscale x 8 x i1> %pg,398 <vscale x 8 x i16> %a,399 <vscale x 8 x i16> splat(i16 127))400 ret <vscale x 8 x i16> %out401}402 403define <vscale x 8 x i16> @smax_i16_out_of_range(<vscale x 8 x i16> %a) {404; CHECK-LABEL: smax_i16_out_of_range:405; CHECK: // %bb.0:406; CHECK-NEXT: mov w8, #129 // =0x81407; CHECK-NEXT: ptrue p0.h408; CHECK-NEXT: mov z1.h, w8409; CHECK-NEXT: smax z0.h, p0/m, z0.h, z1.h410; CHECK-NEXT: ret411 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)412 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.smax.u.nxv8i16(<vscale x 8 x i1> %pg,413 <vscale x 8 x i16> %a,414 <vscale x 8 x i16> splat(i16 129))415 ret <vscale x 8 x i16> %out416}417 418define <vscale x 4 x i32> @smax_i32(<vscale x 4 x i32> %a) {419; CHECK-LABEL: smax_i32:420; CHECK: // %bb.0:421; CHECK-NEXT: smax z0.s, z0.s, #-128422; CHECK-NEXT: ret423 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)424 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smax.u.nxv4i32(<vscale x 4 x i1> %pg,425 <vscale x 4 x i32> %a,426 <vscale x 4 x i32> splat(i32 -128))427 ret <vscale x 4 x i32> %out428}429 430define <vscale x 4 x i32> @smax_i32_out_of_range(<vscale x 4 x i32> %a) {431; CHECK-LABEL: smax_i32_out_of_range:432; CHECK: // %bb.0:433; CHECK-NEXT: mov z1.s, #-129 // =0xffffffffffffff7f434; CHECK-NEXT: ptrue p0.s435; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s436; CHECK-NEXT: ret437 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)438 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smax.u.nxv4i32(<vscale x 4 x i1> %pg,439 <vscale x 4 x i32> %a,440 <vscale x 4 x i32> splat(i32 -129))441 ret <vscale x 4 x i32> %out442}443 444define <vscale x 2 x i64> @smax_i64(<vscale x 2 x i64> %a) {445; CHECK-LABEL: smax_i64:446; CHECK: // %bb.0:447; CHECK-NEXT: smax z0.d, z0.d, #127448; CHECK-NEXT: ret449 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)450 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smax.u.nxv2i64(<vscale x 2 x i1> %pg,451 <vscale x 2 x i64> %a,452 <vscale x 2 x i64> splat(i64 127))453 ret <vscale x 2 x i64> %out454}455 456define <vscale x 2 x i64> @smax_i64_out_of_range(<vscale x 2 x i64> %a) {457; CHECK-LABEL: smax_i64_out_of_range:458; CHECK: // %bb.0:459; CHECK-NEXT: mov z1.d, #65535 // =0xffff460; CHECK-NEXT: ptrue p0.d461; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d462; CHECK-NEXT: ret463 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)464 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smax.u.nxv2i64(<vscale x 2 x i1> %pg,465 <vscale x 2 x i64> %a,466 <vscale x 2 x i64> splat(i64 65535))467 ret <vscale x 2 x i64> %out468}469 470; As smax_i32 but where pg is i8 based and thus compatible for i32.471define <vscale x 4 x i32> @smax_i32_ptrue_all_b(<vscale x 4 x i32> %a) #0 {472; CHECK-LABEL: smax_i32_ptrue_all_b:473; CHECK: // %bb.0:474; CHECK-NEXT: smax z0.s, z0.s, #1475; CHECK-NEXT: ret476 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)477 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)478 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)479 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smax.u.nxv4i32(<vscale x 4 x i1> %pg.s,480 <vscale x 4 x i32> %a,481 <vscale x 4 x i32> %b)482 ret <vscale x 4 x i32> %out483}484 485; As smax_i32 but where pg is i16 based and thus compatible for i32.486define <vscale x 4 x i32> @smax_i32_ptrue_all_h(<vscale x 4 x i32> %a) #0 {487; CHECK-LABEL: smax_i32_ptrue_all_h:488; CHECK: // %bb.0:489; CHECK-NEXT: smax z0.s, z0.s, #1490; CHECK-NEXT: ret491 %pg.h = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)492 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %pg.h)493 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)494 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)495 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smax.u.nxv4i32(<vscale x 4 x i1> %pg.s,496 <vscale x 4 x i32> %a,497 <vscale x 4 x i32> %b)498 ret <vscale x 4 x i32> %out499}500 501; As smax_i32 but where pg is i64 based, which is not compatibile for i32 and502; thus inactive lanes are important and the immediate form cannot be used.503define <vscale x 4 x i32> @smax_i32_ptrue_all_d(<vscale x 4 x i32> %a) #0 {504; CHECK-LABEL: smax_i32_ptrue_all_d:505; CHECK: // %bb.0:506; CHECK-NEXT: mov z1.s, #1 // =0x1507; CHECK-NEXT: ptrue p0.d508; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s509; CHECK-NEXT: ret510 %pg.d = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)511 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg.d)512 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)513 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)514 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smax.nxv4i32(<vscale x 4 x i1> %pg.s,515 <vscale x 4 x i32> %a,516 <vscale x 4 x i32> %b)517 ret <vscale x 4 x i32> %out518}519 520; SMIN521 522define <vscale x 16 x i8> @smin_i8(<vscale x 16 x i8> %a) {523; CHECK-LABEL: smin_i8:524; CHECK: // %bb.0:525; CHECK-NEXT: smin z0.b, z0.b, #127526; CHECK-NEXT: ret527 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)528 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.smin.u.nxv16i8(<vscale x 16 x i1> %pg,529 <vscale x 16 x i8> %a,530 <vscale x 16 x i8> splat(i8 127))531 ret <vscale x 16 x i8> %out532}533 534define <vscale x 8 x i16> @smin_i16(<vscale x 8 x i16> %a) {535; CHECK-LABEL: smin_i16:536; CHECK: // %bb.0:537; CHECK-NEXT: smin z0.h, z0.h, #-128538; CHECK-NEXT: ret539 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)540 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.smin.u.nxv8i16(<vscale x 8 x i1> %pg,541 <vscale x 8 x i16> %a,542 <vscale x 8 x i16> splat(i16 -128))543 ret <vscale x 8 x i16> %out544}545 546define <vscale x 8 x i16> @smin_i16_out_of_range(<vscale x 8 x i16> %a) {547; CHECK-LABEL: smin_i16_out_of_range:548; CHECK: // %bb.0:549; CHECK-NEXT: mov z1.h, #-129 // =0xffffffffffffff7f550; CHECK-NEXT: ptrue p0.h551; CHECK-NEXT: smin z0.h, p0/m, z0.h, z1.h552; CHECK-NEXT: ret553 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)554 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.smin.u.nxv8i16(<vscale x 8 x i1> %pg,555 <vscale x 8 x i16> %a,556 <vscale x 8 x i16> splat(i16 -129))557 ret <vscale x 8 x i16> %out558}559 560define <vscale x 4 x i32> @smin_i32(<vscale x 4 x i32> %a) {561; CHECK-LABEL: smin_i32:562; CHECK: // %bb.0:563; CHECK-NEXT: smin z0.s, z0.s, #127564; CHECK-NEXT: ret565 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)566 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smin.u.nxv4i32(<vscale x 4 x i1> %pg,567 <vscale x 4 x i32> %a,568 <vscale x 4 x i32> splat(i32 127))569 ret <vscale x 4 x i32> %out570}571 572define <vscale x 4 x i32> @smin_i32_out_of_range(<vscale x 4 x i32> %a) {573; CHECK-LABEL: smin_i32_out_of_range:574; CHECK: // %bb.0:575; CHECK-NEXT: mov w8, #257 // =0x101576; CHECK-NEXT: ptrue p0.s577; CHECK-NEXT: mov z1.s, w8578; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s579; CHECK-NEXT: ret580 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)581 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smin.u.nxv4i32(<vscale x 4 x i1> %pg,582 <vscale x 4 x i32> %a,583 <vscale x 4 x i32> splat(i32 257))584 ret <vscale x 4 x i32> %out585}586 587 588define <vscale x 2 x i64> @smin_i64(<vscale x 2 x i64> %a) {589; CHECK-LABEL: smin_i64:590; CHECK: // %bb.0:591; CHECK-NEXT: smin z0.d, z0.d, #-128592; CHECK-NEXT: ret593 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)594 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smin.u.nxv2i64(<vscale x 2 x i1> %pg,595 <vscale x 2 x i64> %a,596 <vscale x 2 x i64> splat(i64 -128))597 ret <vscale x 2 x i64> %out598}599 600define <vscale x 2 x i64> @smin_i64_out_of_range(<vscale x 2 x i64> %a) {601; CHECK-LABEL: smin_i64_out_of_range:602; CHECK: // %bb.0:603; CHECK-NEXT: mov z1.d, #-256 // =0xffffffffffffff00604; CHECK-NEXT: ptrue p0.d605; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d606; CHECK-NEXT: ret607 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)608 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smin.u.nxv2i64(<vscale x 2 x i1> %pg,609 <vscale x 2 x i64> %a,610 <vscale x 2 x i64> splat(i64 -256))611 ret <vscale x 2 x i64> %out612}613 614; As smin_i32 but where pg is i8 based and thus compatible for i32.615define <vscale x 4 x i32> @smin_i32_ptrue_all_b(<vscale x 4 x i32> %a) #0 {616; CHECK-LABEL: smin_i32_ptrue_all_b:617; CHECK: // %bb.0:618; CHECK-NEXT: smin z0.s, z0.s, #1619; CHECK-NEXT: ret620 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)621 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)622 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)623 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smin.u.nxv4i32(<vscale x 4 x i1> %pg.s,624 <vscale x 4 x i32> %a,625 <vscale x 4 x i32> %b)626 ret <vscale x 4 x i32> %out627}628 629; As smin_i32 but where pg is i16 based and thus compatible for i32.630define <vscale x 4 x i32> @smin_i32_ptrue_all_h(<vscale x 4 x i32> %a) #0 {631; CHECK-LABEL: smin_i32_ptrue_all_h:632; CHECK: // %bb.0:633; CHECK-NEXT: smin z0.s, z0.s, #1634; CHECK-NEXT: ret635 %pg.h = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)636 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %pg.h)637 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)638 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)639 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smin.u.nxv4i32(<vscale x 4 x i1> %pg.s,640 <vscale x 4 x i32> %a,641 <vscale x 4 x i32> %b)642 ret <vscale x 4 x i32> %out643}644 645; As smin_i32 but where pg is i64 based, which is not compatibile for i32 and646; thus inactive lanes are important and the immediate form cannot be used.647define <vscale x 4 x i32> @smin_i32_ptrue_all_d(<vscale x 4 x i32> %a) #0 {648; CHECK-LABEL: smin_i32_ptrue_all_d:649; CHECK: // %bb.0:650; CHECK-NEXT: mov z1.s, #1 // =0x1651; CHECK-NEXT: ptrue p0.d652; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s653; CHECK-NEXT: ret654 %pg.d = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)655 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg.d)656 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)657 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)658 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smin.nxv4i32(<vscale x 4 x i1> %pg.s,659 <vscale x 4 x i32> %a,660 <vscale x 4 x i32> %b)661 ret <vscale x 4 x i32> %out662}663 664; UMAX665 666define <vscale x 16 x i8> @umax_i8(<vscale x 16 x i8> %a) {667; CHECK-LABEL: umax_i8:668; CHECK: // %bb.0:669; CHECK-NEXT: umax z0.b, z0.b, #0670; CHECK-NEXT: ret671 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)672 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.umax.u.nxv16i8(<vscale x 16 x i1> %pg,673 <vscale x 16 x i8> %a,674 <vscale x 16 x i8> zeroinitializer)675 ret <vscale x 16 x i8> %out676}677 678define <vscale x 8 x i16> @umax_i16(<vscale x 8 x i16> %a) {679; CHECK-LABEL: umax_i16:680; CHECK: // %bb.0:681; CHECK-NEXT: umax z0.h, z0.h, #255682; CHECK-NEXT: ret683 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)684 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.umax.u.nxv8i16(<vscale x 8 x i1> %pg,685 <vscale x 8 x i16> %a,686 <vscale x 8 x i16> splat(i16 255))687 ret <vscale x 8 x i16> %out688}689 690define <vscale x 8 x i16> @umax_i16_out_of_range(<vscale x 8 x i16> %a) {691; CHECK-LABEL: umax_i16_out_of_range:692; CHECK: // %bb.0:693; CHECK-NEXT: dupm z1.b, #0x1694; CHECK-NEXT: ptrue p0.h695; CHECK-NEXT: umax z0.h, p0/m, z0.h, z1.h696; CHECK-NEXT: ret697 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)698 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.umax.u.nxv8i16(<vscale x 8 x i1> %pg,699 <vscale x 8 x i16> %a,700 <vscale x 8 x i16> splat(i16 257))701 ret <vscale x 8 x i16> %out702}703 704define <vscale x 4 x i32> @umax_i32(<vscale x 4 x i32> %a) {705; CHECK-LABEL: umax_i32:706; CHECK: // %bb.0:707; CHECK-NEXT: umax z0.s, z0.s, #0708; CHECK-NEXT: ret709 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)710 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.umax.u.nxv4i32(<vscale x 4 x i1> %pg,711 <vscale x 4 x i32> %a,712 <vscale x 4 x i32> zeroinitializer)713 ret <vscale x 4 x i32> %out714}715 716define <vscale x 4 x i32> @umax_i32_out_of_range(<vscale x 4 x i32> %a) {717; CHECK-LABEL: umax_i32_out_of_range:718; CHECK: // %bb.0:719; CHECK-NEXT: mov w8, #257 // =0x101720; CHECK-NEXT: ptrue p0.s721; CHECK-NEXT: mov z1.s, w8722; CHECK-NEXT: umax z0.s, p0/m, z0.s, z1.s723; CHECK-NEXT: ret724 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)725 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.umax.u.nxv4i32(<vscale x 4 x i1> %pg,726 <vscale x 4 x i32> %a,727 <vscale x 4 x i32> splat(i32 257))728 ret <vscale x 4 x i32> %out729}730 731define <vscale x 2 x i64> @umax_i64(<vscale x 2 x i64> %a) {732; CHECK-LABEL: umax_i64:733; CHECK: // %bb.0:734; CHECK-NEXT: umax z0.d, z0.d, #255735; CHECK-NEXT: ret736 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)737 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.umax.u.nxv2i64(<vscale x 2 x i1> %pg,738 <vscale x 2 x i64> %a,739 <vscale x 2 x i64> splat(i64 255))740 ret <vscale x 2 x i64> %out741}742 743define <vscale x 2 x i64> @umax_i64_out_of_range(<vscale x 2 x i64> %a) {744; CHECK-LABEL: umax_i64_out_of_range:745; CHECK: // %bb.0:746; CHECK-NEXT: mov z1.d, #65535 // =0xffff747; CHECK-NEXT: ptrue p0.d748; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d749; CHECK-NEXT: ret750 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)751 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.umax.u.nxv2i64(<vscale x 2 x i1> %pg,752 <vscale x 2 x i64> %a,753 <vscale x 2 x i64> splat(i64 65535))754 ret <vscale x 2 x i64> %out755}756 757; As umax_i32 but where pg is i8 based and thus compatible for i32.758define <vscale x 4 x i32> @umax_i32_ptrue_all_b(<vscale x 4 x i32> %a) #0 {759; CHECK-LABEL: umax_i32_ptrue_all_b:760; CHECK: // %bb.0:761; CHECK-NEXT: umax z0.s, z0.s, #1762; CHECK-NEXT: ret763 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)764 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)765 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)766 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umax.u.nxv4i32(<vscale x 4 x i1> %pg.s,767 <vscale x 4 x i32> %a,768 <vscale x 4 x i32> %b)769 ret <vscale x 4 x i32> %out770}771 772; As umax_i32 but where pg is i16 based and thus compatible for i32.773define <vscale x 4 x i32> @umax_i32_ptrue_all_h(<vscale x 4 x i32> %a) #0 {774; CHECK-LABEL: umax_i32_ptrue_all_h:775; CHECK: // %bb.0:776; CHECK-NEXT: umax z0.s, z0.s, #1777; CHECK-NEXT: ret778 %pg.h = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)779 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %pg.h)780 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)781 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)782 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umax.u.nxv4i32(<vscale x 4 x i1> %pg.s,783 <vscale x 4 x i32> %a,784 <vscale x 4 x i32> %b)785 ret <vscale x 4 x i32> %out786}787 788; As umax_i32 but where pg is i64 based, which is not compatibile for i32 and789; thus inactive lanes are important and the immediate form cannot be used.790define <vscale x 4 x i32> @umax_i32_ptrue_all_d(<vscale x 4 x i32> %a) #0 {791; CHECK-LABEL: umax_i32_ptrue_all_d:792; CHECK: // %bb.0:793; CHECK-NEXT: mov z1.s, #1 // =0x1794; CHECK-NEXT: ptrue p0.d795; CHECK-NEXT: umax z0.s, p0/m, z0.s, z1.s796; CHECK-NEXT: ret797 %pg.d = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)798 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg.d)799 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)800 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)801 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umax.nxv4i32(<vscale x 4 x i1> %pg.s,802 <vscale x 4 x i32> %a,803 <vscale x 4 x i32> %b)804 ret <vscale x 4 x i32> %out805}806 807; UMIN808 809define <vscale x 16 x i8> @umin_i8(<vscale x 16 x i8> %a) {810; CHECK-LABEL: umin_i8:811; CHECK: // %bb.0:812; CHECK-NEXT: umin z0.b, z0.b, #255813; CHECK-NEXT: ret814 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)815 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.umin.u.nxv16i8(<vscale x 16 x i1> %pg,816 <vscale x 16 x i8> %a,817 <vscale x 16 x i8> splat(i8 255))818 ret <vscale x 16 x i8> %out819}820 821define <vscale x 8 x i16> @umin_i16(<vscale x 8 x i16> %a) {822; CHECK-LABEL: umin_i16:823; CHECK: // %bb.0:824; CHECK-NEXT: umin z0.h, z0.h, #0825; CHECK-NEXT: ret826 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)827 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.umin.u.nxv8i16(<vscale x 8 x i1> %pg,828 <vscale x 8 x i16> %a,829 <vscale x 8 x i16> zeroinitializer)830 ret <vscale x 8 x i16> %out831}832 833define <vscale x 8 x i16> @umin_i16_out_of_range(<vscale x 8 x i16> %a) {834; CHECK-LABEL: umin_i16_out_of_range:835; CHECK: // %bb.0:836; CHECK-NEXT: dupm z1.b, #0x1837; CHECK-NEXT: ptrue p0.h838; CHECK-NEXT: umin z0.h, p0/m, z0.h, z1.h839; CHECK-NEXT: ret840 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)841 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.umin.u.nxv8i16(<vscale x 8 x i1> %pg,842 <vscale x 8 x i16> %a,843 <vscale x 8 x i16> splat(i16 257))844 ret <vscale x 8 x i16> %out845}846 847define <vscale x 4 x i32> @umin_i32(<vscale x 4 x i32> %a) {848; CHECK-LABEL: umin_i32:849; CHECK: // %bb.0:850; CHECK-NEXT: umin z0.s, z0.s, #255851; CHECK-NEXT: ret852 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)853 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.umin.u.nxv4i32(<vscale x 4 x i1> %pg,854 <vscale x 4 x i32> %a,855 <vscale x 4 x i32> splat(i32 255))856 ret <vscale x 4 x i32> %out857}858 859define <vscale x 4 x i32> @umin_i32_out_of_range(<vscale x 4 x i32> %a) {860; CHECK-LABEL: umin_i32_out_of_range:861; CHECK: // %bb.0:862; CHECK-NEXT: mov w8, #257 // =0x101863; CHECK-NEXT: ptrue p0.s864; CHECK-NEXT: mov z1.s, w8865; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s866; CHECK-NEXT: ret867 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)868 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.umin.u.nxv4i32(<vscale x 4 x i1> %pg,869 <vscale x 4 x i32> %a,870 <vscale x 4 x i32> splat(i32 257))871 ret <vscale x 4 x i32> %out872}873 874define <vscale x 2 x i64> @umin_i64(<vscale x 2 x i64> %a) {875; CHECK-LABEL: umin_i64:876; CHECK: // %bb.0:877; CHECK-NEXT: umin z0.d, z0.d, #0878; CHECK-NEXT: ret879 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)880 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.umin.u.nxv2i64(<vscale x 2 x i1> %pg,881 <vscale x 2 x i64> %a,882 <vscale x 2 x i64> zeroinitializer)883 ret <vscale x 2 x i64> %out884}885 886define <vscale x 2 x i64> @umin_i64_out_of_range(<vscale x 2 x i64> %a) {887; CHECK-LABEL: umin_i64_out_of_range:888; CHECK: // %bb.0:889; CHECK-NEXT: mov z1.d, #65535 // =0xffff890; CHECK-NEXT: ptrue p0.d891; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d892; CHECK-NEXT: ret893 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)894 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.umin.u.nxv2i64(<vscale x 2 x i1> %pg,895 <vscale x 2 x i64> %a,896 <vscale x 2 x i64> splat(i64 65535))897 ret <vscale x 2 x i64> %out898}899 900; As umin_i32 but where pg is i8 based and thus compatible for i32.901define <vscale x 4 x i32> @umin_i32_ptrue_all_b(<vscale x 4 x i32> %a) #0 {902; CHECK-LABEL: umin_i32_ptrue_all_b:903; CHECK: // %bb.0:904; CHECK-NEXT: umin z0.s, z0.s, #1905; CHECK-NEXT: ret906 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)907 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)908 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)909 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umin.u.nxv4i32(<vscale x 4 x i1> %pg.s,910 <vscale x 4 x i32> %a,911 <vscale x 4 x i32> %b)912 ret <vscale x 4 x i32> %out913}914 915; As umin_i32 but where pg is i16 based and thus compatible for i32.916define <vscale x 4 x i32> @umin_i32_ptrue_all_h(<vscale x 4 x i32> %a) #0 {917; CHECK-LABEL: umin_i32_ptrue_all_h:918; CHECK: // %bb.0:919; CHECK-NEXT: umin z0.s, z0.s, #1920; CHECK-NEXT: ret921 %pg.h = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)922 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %pg.h)923 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)924 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)925 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umin.u.nxv4i32(<vscale x 4 x i1> %pg.s,926 <vscale x 4 x i32> %a,927 <vscale x 4 x i32> %b)928 ret <vscale x 4 x i32> %out929}930 931; As umin_i32 but where pg is i64 based, which is not compatibile for i32 and932; thus inactive lanes are important and the immediate form cannot be used.933define <vscale x 4 x i32> @umin_i32_ptrue_all_d(<vscale x 4 x i32> %a) #0 {934; CHECK-LABEL: umin_i32_ptrue_all_d:935; CHECK: // %bb.0:936; CHECK-NEXT: mov z1.s, #1 // =0x1937; CHECK-NEXT: ptrue p0.d938; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s939; CHECK-NEXT: ret940 %pg.d = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)941 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg.d)942 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)943 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)944 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umin.nxv4i32(<vscale x 4 x i1> %pg.s,945 <vscale x 4 x i32> %a,946 <vscale x 4 x i32> %b)947 ret <vscale x 4 x i32> %out948}949 950; SQADD951 952define <vscale x 16 x i8> @sqadd_b_lowimm(<vscale x 16 x i8> %a) {953; CHECK-LABEL: sqadd_b_lowimm:954; CHECK: // %bb.0:955; CHECK-NEXT: sqadd z0.b, z0.b, #27 // =0x1b956; CHECK-NEXT: ret957 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.x.nxv16i8(<vscale x 16 x i8> %a,958 <vscale x 16 x i8> splat(i8 27))959 ret <vscale x 16 x i8> %out960}961 962; Immediate instruction form only supports positive values.963define <vscale x 16 x i8> @sqadd_b_negimm(<vscale x 16 x i8> %a) {964; CHECK-LABEL: sqadd_b_negimm:965; CHECK: // %bb.0:966; CHECK-NEXT: sqsub z0.b, z0.b, #128 // =0x80967; CHECK-NEXT: ret968 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.x.nxv16i8(<vscale x 16 x i8> %a,969 <vscale x 16 x i8> splat(i8 -128))970 ret <vscale x 16 x i8> %out971}972 973define <vscale x 8 x i16> @sqadd_h_lowimm(<vscale x 8 x i16> %a) {974; CHECK-LABEL: sqadd_h_lowimm:975; CHECK: // %bb.0:976; CHECK-NEXT: sqadd z0.h, z0.h, #43 // =0x2b977; CHECK-NEXT: ret978 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16> %a,979 <vscale x 8 x i16> splat(i16 43))980 ret <vscale x 8 x i16> %out981}982 983define <vscale x 8 x i16> @sqadd_h_highimm(<vscale x 8 x i16> %a) {984; CHECK-LABEL: sqadd_h_highimm:985; CHECK: // %bb.0:986; CHECK-NEXT: sqadd z0.h, z0.h, #2048 // =0x800987; CHECK-NEXT: ret988 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16> %a,989 <vscale x 8 x i16> splat(i16 2048))990 ret <vscale x 8 x i16> %out991}992 993; Immediate instruction form only supports positive values.994define <vscale x 8 x i16> @sqadd_h_negimm(<vscale x 8 x i16> %a) {995; CHECK-LABEL: sqadd_h_negimm:996; CHECK: // %bb.0:997; CHECK-NEXT: sqsub z0.h, z0.h, #1 // =0x1998; CHECK-NEXT: ret999 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16> %a,1000 <vscale x 8 x i16> splat(i16 -1))1001 ret <vscale x 8 x i16> %out1002}1003 1004define <vscale x 4 x i32> @sqadd_s_lowimm(<vscale x 4 x i32> %a) {1005; CHECK-LABEL: sqadd_s_lowimm:1006; CHECK: // %bb.0:1007; CHECK-NEXT: sqadd z0.s, z0.s, #1 // =0x11008; CHECK-NEXT: ret1009 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32> %a,1010 <vscale x 4 x i32> splat(i32 1))1011 ret <vscale x 4 x i32> %out1012}1013 1014define <vscale x 4 x i32> @sqadd_s_highimm(<vscale x 4 x i32> %a) {1015; CHECK-LABEL: sqadd_s_highimm:1016; CHECK: // %bb.0:1017; CHECK-NEXT: sqadd z0.s, z0.s, #8192 // =0x20001018; CHECK-NEXT: ret1019 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32> %a,1020 <vscale x 4 x i32> splat(i32 8192))1021 ret <vscale x 4 x i32> %out1022}1023 1024; Immediate instruction form only supports positive values.1025define <vscale x 4 x i32> @sqadd_s_negimm(<vscale x 4 x i32> %a) {1026; CHECK-LABEL: sqadd_s_negimm:1027; CHECK: // %bb.0:1028; CHECK-NEXT: sqsub z0.s, z0.s, #65280 // =0xff001029; CHECK-NEXT: ret1030 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32> %a,1031 <vscale x 4 x i32> splat(i32 -65280))1032 ret <vscale x 4 x i32> %out1033}1034 1035define <vscale x 2 x i64> @sqadd_d_lowimm(<vscale x 2 x i64> %a) {1036; CHECK-LABEL: sqadd_d_lowimm:1037; CHECK: // %bb.0:1038; CHECK-NEXT: sqadd z0.d, z0.d, #255 // =0xff1039; CHECK-NEXT: ret1040 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.x.nxv2i64(<vscale x 2 x i64> %a,1041 <vscale x 2 x i64> splat(i64 255))1042 ret <vscale x 2 x i64> %out1043}1044 1045define <vscale x 2 x i64> @sqadd_d_highimm(<vscale x 2 x i64> %a) {1046; CHECK-LABEL: sqadd_d_highimm:1047; CHECK: // %bb.0:1048; CHECK-NEXT: sqadd z0.d, z0.d, #65280 // =0xff001049; CHECK-NEXT: ret1050 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.x.nxv2i64(<vscale x 2 x i64> %a,1051 <vscale x 2 x i64> splat(i64 65280))1052 ret <vscale x 2 x i64> %out1053}1054 1055; Immediate instruction form only supports positive values.1056define <vscale x 2 x i64> @sqadd_d_negimm(<vscale x 2 x i64> %a) {1057; CHECK-LABEL: sqadd_d_negimm:1058; CHECK: // %bb.0:1059; CHECK-NEXT: sqsub z0.d, z0.d, #3840 // =0xf001060; CHECK-NEXT: ret1061 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.x.nxv2i64(<vscale x 2 x i64> %a,1062 <vscale x 2 x i64> splat(i64 -3840))1063 ret <vscale x 2 x i64> %out1064}1065 1066; SQSUB1067 1068define <vscale x 16 x i8> @sqsub_b_lowimm(<vscale x 16 x i8> %a) {1069; CHECK-LABEL: sqsub_b_lowimm:1070; CHECK: // %bb.0:1071; CHECK-NEXT: sqsub z0.b, z0.b, #27 // =0x1b1072; CHECK-NEXT: ret1073 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.x.nxv16i8(<vscale x 16 x i8> %a,1074 <vscale x 16 x i8> splat(i8 27))1075 ret <vscale x 16 x i8> %out1076}1077 1078; Immediate instruction form only supports positive values.1079define <vscale x 16 x i8> @sqsub_b_negimm(<vscale x 16 x i8> %a) {1080; CHECK-LABEL: sqsub_b_negimm:1081; CHECK: // %bb.0:1082; CHECK-NEXT: sqadd z0.b, z0.b, #1 // =0x11083; CHECK-NEXT: ret1084 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.x.nxv16i8(<vscale x 16 x i8> %a,1085 <vscale x 16 x i8> splat(i8 -1))1086 ret <vscale x 16 x i8> %out1087}1088 1089define <vscale x 8 x i16> @sqsub_h_lowimm(<vscale x 8 x i16> %a) {1090; CHECK-LABEL: sqsub_h_lowimm:1091; CHECK: // %bb.0:1092; CHECK-NEXT: sqsub z0.h, z0.h, #43 // =0x2b1093; CHECK-NEXT: ret1094 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.x.nxv8i16(<vscale x 8 x i16> %a,1095 <vscale x 8 x i16> splat(i16 43))1096 ret <vscale x 8 x i16> %out1097}1098 1099define <vscale x 8 x i16> @sqsub_h_highimm(<vscale x 8 x i16> %a) {1100; CHECK-LABEL: sqsub_h_highimm:1101; CHECK: // %bb.0:1102; CHECK-NEXT: sqsub z0.h, z0.h, #2048 // =0x8001103; CHECK-NEXT: ret1104 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.x.nxv8i16(<vscale x 8 x i16> %a,1105 <vscale x 8 x i16> splat(i16 2048))1106 ret <vscale x 8 x i16> %out1107}1108 1109; Immediate instruction form only supports positive values.1110define <vscale x 8 x i16> @sqsub_h_negimm(<vscale x 8 x i16> %a) {1111; CHECK-LABEL: sqsub_h_negimm:1112; CHECK: // %bb.0:1113; CHECK-NEXT: sqadd z0.h, z0.h, #128 // =0x801114; CHECK-NEXT: ret1115 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.x.nxv8i16(<vscale x 8 x i16> %a,1116 <vscale x 8 x i16> splat(i16 -128))1117 ret <vscale x 8 x i16> %out1118}1119 1120define <vscale x 4 x i32> @sqsub_s_lowimm(<vscale x 4 x i32> %a) {1121; CHECK-LABEL: sqsub_s_lowimm:1122; CHECK: // %bb.0:1123; CHECK-NEXT: sqsub z0.s, z0.s, #1 // =0x11124; CHECK-NEXT: ret1125 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.x.nxv4i32(<vscale x 4 x i32> %a,1126 <vscale x 4 x i32> splat(i32 1))1127 ret <vscale x 4 x i32> %out1128}1129 1130define <vscale x 4 x i32> @sqsub_s_highimm(<vscale x 4 x i32> %a) {1131; CHECK-LABEL: sqsub_s_highimm:1132; CHECK: // %bb.0:1133; CHECK-NEXT: sqsub z0.s, z0.s, #8192 // =0x20001134; CHECK-NEXT: ret1135 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.x.nxv4i32(<vscale x 4 x i32> %a,1136 <vscale x 4 x i32> splat(i32 8192))1137 ret <vscale x 4 x i32> %out1138}1139 1140; Immediate instruction form only supports positive values.1141define <vscale x 4 x i32> @sqsub_s_negimm(<vscale x 4 x i32> %a) {1142; CHECK-LABEL: sqsub_s_negimm:1143; CHECK: // %bb.0:1144; CHECK-NEXT: sqadd z0.s, z0.s, #32768 // =0x80001145; CHECK-NEXT: ret1146 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.x.nxv4i32(<vscale x 4 x i32> %a,1147 <vscale x 4 x i32> splat(i32 -32768))1148 ret <vscale x 4 x i32> %out1149}1150 1151define <vscale x 2 x i64> @sqsub_d_lowimm(<vscale x 2 x i64> %a) {1152; CHECK-LABEL: sqsub_d_lowimm:1153; CHECK: // %bb.0:1154; CHECK-NEXT: sqsub z0.d, z0.d, #255 // =0xff1155; CHECK-NEXT: ret1156 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.x.nxv2i64(<vscale x 2 x i64> %a,1157 <vscale x 2 x i64> splat(i64 255))1158 ret <vscale x 2 x i64> %out1159}1160 1161define <vscale x 2 x i64> @sqsub_d_highimm(<vscale x 2 x i64> %a) {1162; CHECK-LABEL: sqsub_d_highimm:1163; CHECK: // %bb.0:1164; CHECK-NEXT: sqsub z0.d, z0.d, #65280 // =0xff001165; CHECK-NEXT: ret1166 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.x.nxv2i64(<vscale x 2 x i64> %a,1167 <vscale x 2 x i64> splat(i64 65280))1168 ret <vscale x 2 x i64> %out1169}1170 1171; Immediate instruction form only supports positive values.1172define <vscale x 2 x i64> @sqsub_d_negimm(<vscale x 2 x i64> %a) {1173; CHECK-LABEL: sqsub_d_negimm:1174; CHECK: // %bb.0:1175; CHECK-NEXT: sqadd z0.d, z0.d, #57344 // =0xe0001176; CHECK-NEXT: ret1177 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.x.nxv2i64(<vscale x 2 x i64> %a,1178 <vscale x 2 x i64> splat(i64 -57344))1179 ret <vscale x 2 x i64> %out1180}1181 1182; UQADD1183 1184define <vscale x 16 x i8> @uqadd_b_lowimm(<vscale x 16 x i8> %a) {1185; CHECK-LABEL: uqadd_b_lowimm:1186; CHECK: // %bb.0:1187; CHECK-NEXT: uqadd z0.b, z0.b, #27 // =0x1b1188; CHECK-NEXT: ret1189 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqadd.x.nxv16i8(<vscale x 16 x i8> %a,1190 <vscale x 16 x i8> splat(i8 27))1191 ret <vscale x 16 x i8> %out1192}1193 1194define <vscale x 8 x i16> @uqadd_h_lowimm(<vscale x 8 x i16> %a) {1195; CHECK-LABEL: uqadd_h_lowimm:1196; CHECK: // %bb.0:1197; CHECK-NEXT: uqadd z0.h, z0.h, #43 // =0x2b1198; CHECK-NEXT: ret1199 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.x.nxv8i16(<vscale x 8 x i16> %a,1200 <vscale x 8 x i16> splat(i16 43))1201 ret <vscale x 8 x i16> %out1202}1203 1204define <vscale x 8 x i16> @uqadd_h_highimm(<vscale x 8 x i16> %a) {1205; CHECK-LABEL: uqadd_h_highimm:1206; CHECK: // %bb.0:1207; CHECK-NEXT: uqadd z0.h, z0.h, #2048 // =0x8001208; CHECK-NEXT: ret1209 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.x.nxv8i16(<vscale x 8 x i16> %a,1210 <vscale x 8 x i16> splat(i16 2048))1211 ret <vscale x 8 x i16> %out1212}1213 1214define <vscale x 4 x i32> @uqadd_s_lowimm(<vscale x 4 x i32> %a) {1215; CHECK-LABEL: uqadd_s_lowimm:1216; CHECK: // %bb.0:1217; CHECK-NEXT: uqadd z0.s, z0.s, #1 // =0x11218; CHECK-NEXT: ret1219 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.x.nxv4i32(<vscale x 4 x i32> %a,1220 <vscale x 4 x i32> splat(i32 1))1221 ret <vscale x 4 x i32> %out1222}1223 1224define <vscale x 4 x i32> @uqadd_s_highimm(<vscale x 4 x i32> %a) {1225; CHECK-LABEL: uqadd_s_highimm:1226; CHECK: // %bb.0:1227; CHECK-NEXT: uqadd z0.s, z0.s, #8192 // =0x20001228; CHECK-NEXT: ret1229 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.x.nxv4i32(<vscale x 4 x i32> %a,1230 <vscale x 4 x i32> splat(i32 8192))1231 ret <vscale x 4 x i32> %out1232}1233 1234define <vscale x 2 x i64> @uqadd_d_lowimm(<vscale x 2 x i64> %a) {1235; CHECK-LABEL: uqadd_d_lowimm:1236; CHECK: // %bb.0:1237; CHECK-NEXT: uqadd z0.d, z0.d, #255 // =0xff1238; CHECK-NEXT: ret1239 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.x.nxv2i64(<vscale x 2 x i64> %a,1240 <vscale x 2 x i64> splat(i64 255))1241 ret <vscale x 2 x i64> %out1242}1243 1244define <vscale x 2 x i64> @uqadd_d_highimm(<vscale x 2 x i64> %a) {1245; CHECK-LABEL: uqadd_d_highimm:1246; CHECK: // %bb.0:1247; CHECK-NEXT: uqadd z0.d, z0.d, #65280 // =0xff001248; CHECK-NEXT: ret1249 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.x.nxv2i64(<vscale x 2 x i64> %a,1250 <vscale x 2 x i64> splat(i64 65280))1251 ret <vscale x 2 x i64> %out1252}1253 1254; UQSUB1255 1256define <vscale x 16 x i8> @uqsub_b_lowimm(<vscale x 16 x i8> %a) {1257; CHECK-LABEL: uqsub_b_lowimm:1258; CHECK: // %bb.0:1259; CHECK-NEXT: uqsub z0.b, z0.b, #27 // =0x1b1260; CHECK-NEXT: ret1261 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.x.nxv16i8(<vscale x 16 x i8> %a,1262 <vscale x 16 x i8> splat(i8 27))1263 ret <vscale x 16 x i8> %out1264}1265 1266define <vscale x 8 x i16> @uqsub_h_lowimm(<vscale x 8 x i16> %a) {1267; CHECK-LABEL: uqsub_h_lowimm:1268; CHECK: // %bb.0:1269; CHECK-NEXT: uqsub z0.h, z0.h, #43 // =0x2b1270; CHECK-NEXT: ret1271 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.x.nxv8i16(<vscale x 8 x i16> %a,1272 <vscale x 8 x i16> splat(i16 43))1273 ret <vscale x 8 x i16> %out1274}1275 1276define <vscale x 8 x i16> @uqsub_h_highimm(<vscale x 8 x i16> %a) {1277; CHECK-LABEL: uqsub_h_highimm:1278; CHECK: // %bb.0:1279; CHECK-NEXT: uqsub z0.h, z0.h, #2048 // =0x8001280; CHECK-NEXT: ret1281 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.x.nxv8i16(<vscale x 8 x i16> %a,1282 <vscale x 8 x i16> splat(i16 2048))1283 ret <vscale x 8 x i16> %out1284}1285 1286define <vscale x 4 x i32> @uqsub_s_lowimm(<vscale x 4 x i32> %a) {1287; CHECK-LABEL: uqsub_s_lowimm:1288; CHECK: // %bb.0:1289; CHECK-NEXT: uqsub z0.s, z0.s, #1 // =0x11290; CHECK-NEXT: ret1291 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.x.nxv4i32(<vscale x 4 x i32> %a,1292 <vscale x 4 x i32> splat(i32 1))1293 ret <vscale x 4 x i32> %out1294}1295 1296define <vscale x 4 x i32> @uqsub_s_highimm(<vscale x 4 x i32> %a) {1297; CHECK-LABEL: uqsub_s_highimm:1298; CHECK: // %bb.0:1299; CHECK-NEXT: uqsub z0.s, z0.s, #8192 // =0x20001300; CHECK-NEXT: ret1301 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.x.nxv4i32(<vscale x 4 x i32> %a,1302 <vscale x 4 x i32> splat(i32 8192))1303 ret <vscale x 4 x i32> %out1304}1305 1306define <vscale x 2 x i64> @uqsub_d_lowimm(<vscale x 2 x i64> %a) {1307; CHECK-LABEL: uqsub_d_lowimm:1308; CHECK: // %bb.0:1309; CHECK-NEXT: uqsub z0.d, z0.d, #255 // =0xff1310; CHECK-NEXT: ret1311 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.x.nxv2i64(<vscale x 2 x i64> %a,1312 <vscale x 2 x i64> splat(i64 255))1313 ret <vscale x 2 x i64> %out1314}1315 1316define <vscale x 2 x i64> @uqsub_d_highimm(<vscale x 2 x i64> %a) {1317; CHECK-LABEL: uqsub_d_highimm:1318; CHECK: // %bb.0:1319; CHECK-NEXT: uqsub z0.d, z0.d, #65280 // =0xff001320; CHECK-NEXT: ret1321 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.x.nxv2i64(<vscale x 2 x i64> %a,1322 <vscale x 2 x i64> splat(i64 65280))1323 ret <vscale x 2 x i64> %out1324}1325 1326; ASR1327 1328define <vscale x 16 x i8> @asr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {1329; CHECK-LABEL: asr_i8:1330; CHECK: // %bb.0:1331; CHECK-NEXT: asr z0.b, p0/m, z0.b, #81332; CHECK-NEXT: ret1333 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %pg,1334 <vscale x 16 x i8> %a,1335 <vscale x 16 x i8> splat(i8 9))1336 ret <vscale x 16 x i8> %out1337}1338 1339define <vscale x 16 x i8> @asr_i8_all_active(<vscale x 16 x i8> %a) {1340; CHECK-LABEL: asr_i8_all_active:1341; CHECK: // %bb.0:1342; CHECK-NEXT: asr z0.b, z0.b, #81343; CHECK-NEXT: ret1344 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)1345 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.u.nxv16i8(<vscale x 16 x i1> %pg,1346 <vscale x 16 x i8> %a,1347 <vscale x 16 x i8> splat(i8 8))1348 ret <vscale x 16 x i8> %out1349}1350 1351; Ensure we don't match a right shift by zero to the immediate form.1352define <vscale x 16 x i8> @asr_i8_too_small(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {1353; CHECK-LABEL: asr_i8_too_small:1354; CHECK: // %bb.0:1355; CHECK-NEXT: movi v1.2d, #00000000000000001356; CHECK-NEXT: asr z0.b, p0/m, z0.b, z1.b1357; CHECK-NEXT: ret1358 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %pg,1359 <vscale x 16 x i8> %a,1360 <vscale x 16 x i8> zeroinitializer)1361 ret <vscale x 16 x i8> %out1362}1363 1364define <vscale x 8 x i16> @asr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {1365; CHECK-LABEL: asr_i16:1366; CHECK: // %bb.0:1367; CHECK-NEXT: asr z0.h, p0/m, z0.h, #161368; CHECK-NEXT: ret1369 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %pg,1370 <vscale x 8 x i16> %a,1371 <vscale x 8 x i16> splat(i16 17))1372 ret <vscale x 8 x i16> %out1373}1374 1375define <vscale x 8 x i16> @asr_i16_all_active(<vscale x 8 x i16> %a) {1376; CHECK-LABEL: asr_i16_all_active:1377; CHECK: // %bb.0:1378; CHECK-NEXT: asr z0.h, z0.h, #161379; CHECK-NEXT: ret1380 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)1381 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.u.nxv8i16(<vscale x 8 x i1> %pg,1382 <vscale x 8 x i16> %a,1383 <vscale x 8 x i16> splat(i16 16))1384 ret <vscale x 8 x i16> %out1385}1386 1387; Ensure we don't match a right shift by zero to the immediate form.1388define <vscale x 8 x i16> @asr_i16_too_small(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {1389; CHECK-LABEL: asr_i16_too_small:1390; CHECK: // %bb.0:1391; CHECK-NEXT: movi v1.2d, #00000000000000001392; CHECK-NEXT: asr z0.h, p0/m, z0.h, z1.h1393; CHECK-NEXT: ret1394 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %pg,1395 <vscale x 8 x i16> %a,1396 <vscale x 8 x i16> zeroinitializer)1397 ret <vscale x 8 x i16> %out1398}1399 1400define <vscale x 4 x i32> @asr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {1401; CHECK-LABEL: asr_i32:1402; CHECK: // %bb.0:1403; CHECK-NEXT: asr z0.s, p0/m, z0.s, #321404; CHECK-NEXT: ret1405 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %pg,1406 <vscale x 4 x i32> %a,1407 <vscale x 4 x i32> splat(i32 33))1408 ret <vscale x 4 x i32> %out1409}1410 1411define <vscale x 4 x i32> @asr_i32_all_active(<vscale x 4 x i32> %a) {1412; CHECK-LABEL: asr_i32_all_active:1413; CHECK: // %bb.0:1414; CHECK-NEXT: asr z0.s, z0.s, #321415; CHECK-NEXT: ret1416 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)1417 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.u.nxv4i32(<vscale x 4 x i1> %pg,1418 <vscale x 4 x i32> %a,1419 <vscale x 4 x i32> splat(i32 32))1420 ret <vscale x 4 x i32> %out1421}1422 1423; Ensure we don't match a right shift by zero to the immediate form.1424define <vscale x 4 x i32> @asr_i32_too_small(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {1425; CHECK-LABEL: asr_i32_too_small:1426; CHECK: // %bb.0:1427; CHECK-NEXT: movi v1.2d, #00000000000000001428; CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.s1429; CHECK-NEXT: ret1430 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %pg,1431 <vscale x 4 x i32> %a,1432 <vscale x 4 x i32> zeroinitializer)1433 ret <vscale x 4 x i32> %out1434}1435 1436define <vscale x 2 x i64> @asr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {1437; CHECK-LABEL: asr_i64:1438; CHECK: // %bb.0:1439; CHECK-NEXT: asr z0.d, p0/m, z0.d, #641440; CHECK-NEXT: ret1441 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %pg,1442 <vscale x 2 x i64> %a,1443 <vscale x 2 x i64> splat(i64 65))1444 ret <vscale x 2 x i64> %out1445}1446 1447define <vscale x 2 x i64> @asr_i64_all_active(<vscale x 2 x i64> %a) {1448; CHECK-LABEL: asr_i64_all_active:1449; CHECK: // %bb.0:1450; CHECK-NEXT: asr z0.d, z0.d, #641451; CHECK-NEXT: ret1452 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)1453 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.u.nxv2i64(<vscale x 2 x i1> %pg,1454 <vscale x 2 x i64> %a,1455 <vscale x 2 x i64> splat(i64 64))1456 ret <vscale x 2 x i64> %out1457}1458 1459; Ensure we don't match a right shift by zero to the immediate form.1460define <vscale x 2 x i64> @asr_i64_too_small(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {1461; CHECK-LABEL: asr_i64_too_small:1462; CHECK: // %bb.0:1463; CHECK-NEXT: movi v1.2d, #00000000000000001464; CHECK-NEXT: asr z0.d, p0/m, z0.d, z1.d1465; CHECK-NEXT: ret1466 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %pg,1467 <vscale x 2 x i64> %a,1468 <vscale x 2 x i64> zeroinitializer)1469 ret <vscale x 2 x i64> %out1470}1471 1472; LSL1473 1474define <vscale x 16 x i8> @lsl_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {1475; CHECK-LABEL: lsl_i8:1476; CHECK: // %bb.0:1477; CHECK-NEXT: lsl z0.b, p0/m, z0.b, #71478; CHECK-NEXT: ret1479 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %pg,1480 <vscale x 16 x i8> %a,1481 <vscale x 16 x i8> splat(i8 7))1482 ret <vscale x 16 x i8> %out1483}1484 1485define <vscale x 16 x i8> @lsl_i8_all_active(<vscale x 16 x i8> %a) {1486; CHECK-LABEL: lsl_i8_all_active:1487; CHECK: // %bb.0:1488; CHECK-NEXT: lsl z0.b, z0.b, #71489; CHECK-NEXT: ret1490 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)1491 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.u.nxv16i8(<vscale x 16 x i1> %pg,1492 <vscale x 16 x i8> %a,1493 <vscale x 16 x i8> splat(i8 7))1494 ret <vscale x 16 x i8> %out1495}1496 1497; Ensure we don't match a left shift bigger than its bitwidth to the immediate form.1498define <vscale x 16 x i8> @lsl_i8_too_big(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {1499; CHECK-LABEL: lsl_i8_too_big:1500; CHECK: // %bb.0:1501; CHECK-NEXT: mov z1.b, #8 // =0x81502; CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.b1503; CHECK-NEXT: ret1504 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %pg,1505 <vscale x 16 x i8> %a,1506 <vscale x 16 x i8> splat(i8 8))1507 ret <vscale x 16 x i8> %out1508}1509 1510define <vscale x 16 x i8> @lsl_i8_zero(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {1511; CHECK-LABEL: lsl_i8_zero:1512; CHECK: // %bb.0:1513; CHECK-NEXT: lsl z0.b, p0/m, z0.b, #01514; CHECK-NEXT: ret1515 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %pg,1516 <vscale x 16 x i8> %a,1517 <vscale x 16 x i8> zeroinitializer)1518 ret <vscale x 16 x i8> %out1519}1520 1521define <vscale x 8 x i16> @lsl_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {1522; CHECK-LABEL: lsl_i16:1523; CHECK: // %bb.0:1524; CHECK-NEXT: lsl z0.h, p0/m, z0.h, #151525; CHECK-NEXT: ret1526 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %pg,1527 <vscale x 8 x i16> %a,1528 <vscale x 8 x i16> splat(i16 15))1529 ret <vscale x 8 x i16> %out1530}1531 1532define <vscale x 8 x i16> @lsl_i16_all_active(<vscale x 8 x i16> %a) {1533; CHECK-LABEL: lsl_i16_all_active:1534; CHECK: // %bb.0:1535; CHECK-NEXT: lsl z0.h, z0.h, #151536; CHECK-NEXT: ret1537 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)1538 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.u.nxv8i16(<vscale x 8 x i1> %pg,1539 <vscale x 8 x i16> %a,1540 <vscale x 8 x i16> splat(i16 15))1541 ret <vscale x 8 x i16> %out1542}1543 1544; Ensure we don't match a left shift bigger than its bitwidth to the immediate form.1545define <vscale x 8 x i16> @lsl_i16_too_big(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {1546; CHECK-LABEL: lsl_i16_too_big:1547; CHECK: // %bb.0:1548; CHECK-NEXT: mov z1.h, #16 // =0x101549; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h1550; CHECK-NEXT: ret1551 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %pg,1552 <vscale x 8 x i16> %a,1553 <vscale x 8 x i16> splat(i16 16))1554 ret <vscale x 8 x i16> %out1555}1556 1557define <vscale x 8 x i16> @lsl_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {1558; CHECK-LABEL: lsl_i16_zero:1559; CHECK: // %bb.0:1560; CHECK-NEXT: lsl z0.h, p0/m, z0.h, #01561; CHECK-NEXT: ret1562 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %pg,1563 <vscale x 8 x i16> %a,1564 <vscale x 8 x i16> zeroinitializer)1565 ret <vscale x 8 x i16> %out1566}1567 1568define <vscale x 4 x i32> @lsl_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {1569; CHECK-LABEL: lsl_i32:1570; CHECK: // %bb.0:1571; CHECK-NEXT: lsl z0.s, p0/m, z0.s, #311572; CHECK-NEXT: ret1573 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %pg,1574 <vscale x 4 x i32> %a,1575 <vscale x 4 x i32> splat(i32 31))1576 ret <vscale x 4 x i32> %out1577}1578 1579define <vscale x 4 x i32> @lsl_i32_all_active(<vscale x 4 x i32> %a) {1580; CHECK-LABEL: lsl_i32_all_active:1581; CHECK: // %bb.0:1582; CHECK-NEXT: lsl z0.s, z0.s, #311583; CHECK-NEXT: ret1584 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)1585 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.u.nxv4i32(<vscale x 4 x i1> %pg,1586 <vscale x 4 x i32> %a,1587 <vscale x 4 x i32> splat(i32 31))1588 ret <vscale x 4 x i32> %out1589}1590 1591; Ensure we don't match a left shift bigger than its bitwidth to the immediate form.1592define <vscale x 4 x i32> @lsl_i32_too_big(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {1593; CHECK-LABEL: lsl_i32_too_big:1594; CHECK: // %bb.0:1595; CHECK-NEXT: mov z1.s, #32 // =0x201596; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s1597; CHECK-NEXT: ret1598 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %pg,1599 <vscale x 4 x i32> %a,1600 <vscale x 4 x i32> splat(i32 32))1601 ret <vscale x 4 x i32> %out1602}1603 1604define <vscale x 4 x i32> @lsl_i32_zero(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {1605; CHECK-LABEL: lsl_i32_zero:1606; CHECK: // %bb.0:1607; CHECK-NEXT: lsl z0.s, p0/m, z0.s, #01608; CHECK-NEXT: ret1609 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %pg,1610 <vscale x 4 x i32> %a,1611 <vscale x 4 x i32> zeroinitializer)1612 ret <vscale x 4 x i32> %out1613}1614 1615define <vscale x 2 x i64> @lsl_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {1616; CHECK-LABEL: lsl_i64:1617; CHECK: // %bb.0:1618; CHECK-NEXT: lsl z0.d, p0/m, z0.d, #631619; CHECK-NEXT: ret1620 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %pg,1621 <vscale x 2 x i64> %a,1622 <vscale x 2 x i64> splat(i64 63))1623 ret <vscale x 2 x i64> %out1624}1625 1626define <vscale x 2 x i64> @lsl_i64_all_active(<vscale x 2 x i64> %a) {1627; CHECK-LABEL: lsl_i64_all_active:1628; CHECK: // %bb.0:1629; CHECK-NEXT: lsl z0.d, z0.d, #631630; CHECK-NEXT: ret1631 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)1632 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.u.nxv2i64(<vscale x 2 x i1> %pg,1633 <vscale x 2 x i64> %a,1634 <vscale x 2 x i64> splat(i64 63))1635 ret <vscale x 2 x i64> %out1636}1637 1638; Ensure we don't match a left shift bigger than its bitwidth to the immediate form.1639define <vscale x 2 x i64> @lsl_i64_too_big(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {1640; CHECK-LABEL: lsl_i64_too_big:1641; CHECK: // %bb.0:1642; CHECK-NEXT: mov z1.d, #64 // =0x401643; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d1644; CHECK-NEXT: ret1645 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %pg,1646 <vscale x 2 x i64> %a,1647 <vscale x 2 x i64> splat(i64 64))1648 ret <vscale x 2 x i64> %out1649}1650 1651define <vscale x 2 x i64> @lsl_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {1652; CHECK-LABEL: lsl_i64_zero:1653; CHECK: // %bb.0:1654; CHECK-NEXT: lsl z0.d, p0/m, z0.d, #01655; CHECK-NEXT: ret1656 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %pg,1657 <vscale x 2 x i64> %a,1658 <vscale x 2 x i64> zeroinitializer)1659 ret <vscale x 2 x i64> %out1660}1661 1662; LSR1663 1664define <vscale x 16 x i8> @lsr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {1665; CHECK-LABEL: lsr_i8:1666; CHECK: // %bb.0:1667; CHECK-NEXT: lsr z0.b, p0/m, z0.b, #81668; CHECK-NEXT: ret1669 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %pg,1670 <vscale x 16 x i8> %a,1671 <vscale x 16 x i8> splat(i8 9))1672 ret <vscale x 16 x i8> %out1673}1674 1675define <vscale x 16 x i8> @lsr_i8_all_active(<vscale x 16 x i8> %a) {1676; CHECK-LABEL: lsr_i8_all_active:1677; CHECK: // %bb.0:1678; CHECK-NEXT: lsr z0.b, z0.b, #81679; CHECK-NEXT: ret1680 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)1681 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.u.nxv16i8(<vscale x 16 x i1> %pg,1682 <vscale x 16 x i8> %a,1683 <vscale x 16 x i8> splat(i8 8))1684 ret <vscale x 16 x i8> %out1685}1686 1687; Ensure we don't match a right shift by zero to the immediate form.1688define <vscale x 16 x i8> @lsr_i8_too_small(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {1689; CHECK-LABEL: lsr_i8_too_small:1690; CHECK: // %bb.0:1691; CHECK-NEXT: movi v1.2d, #00000000000000001692; CHECK-NEXT: lsr z0.b, p0/m, z0.b, z1.b1693; CHECK-NEXT: ret1694 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %pg,1695 <vscale x 16 x i8> %a,1696 <vscale x 16 x i8> zeroinitializer)1697 ret <vscale x 16 x i8> %out1698}1699 1700define <vscale x 8 x i16> @lsr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {1701; CHECK-LABEL: lsr_i16:1702; CHECK: // %bb.0:1703; CHECK-NEXT: lsr z0.h, p0/m, z0.h, #161704; CHECK-NEXT: ret1705 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> %pg,1706 <vscale x 8 x i16> %a,1707 <vscale x 8 x i16> splat(i16 17))1708 ret <vscale x 8 x i16> %out1709}1710 1711define <vscale x 8 x i16> @lsr_i16_all_active(<vscale x 8 x i16> %a) {1712; CHECK-LABEL: lsr_i16_all_active:1713; CHECK: // %bb.0:1714; CHECK-NEXT: lsr z0.h, z0.h, #161715; CHECK-NEXT: ret1716 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)1717 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.u.nxv8i16(<vscale x 8 x i1> %pg,1718 <vscale x 8 x i16> %a,1719 <vscale x 8 x i16> splat(i16 16))1720 ret <vscale x 8 x i16> %out1721}1722 1723; Ensure we don't match a right shift by zero to the immediate form.1724define <vscale x 8 x i16> @lsr_i16_too_small(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {1725; CHECK-LABEL: lsr_i16_too_small:1726; CHECK: // %bb.0:1727; CHECK-NEXT: movi v1.2d, #00000000000000001728; CHECK-NEXT: lsr z0.h, p0/m, z0.h, z1.h1729; CHECK-NEXT: ret1730 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> %pg,1731 <vscale x 8 x i16> %a,1732 <vscale x 8 x i16> zeroinitializer)1733 ret <vscale x 8 x i16> %out1734}1735 1736define <vscale x 4 x i32> @lsr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {1737; CHECK-LABEL: lsr_i32:1738; CHECK: // %bb.0:1739; CHECK-NEXT: lsr z0.s, p0/m, z0.s, #321740; CHECK-NEXT: ret1741 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %pg,1742 <vscale x 4 x i32> %a,1743 <vscale x 4 x i32> splat(i32 33))1744 ret <vscale x 4 x i32> %out1745}1746 1747define <vscale x 4 x i32> @lsr_i32_all_active(<vscale x 4 x i32> %a) {1748; CHECK-LABEL: lsr_i32_all_active:1749; CHECK: // %bb.0:1750; CHECK-NEXT: lsr z0.s, z0.s, #321751; CHECK-NEXT: ret1752 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)1753 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.u.nxv4i32(<vscale x 4 x i1> %pg,1754 <vscale x 4 x i32> %a,1755 <vscale x 4 x i32> splat(i32 32))1756 ret <vscale x 4 x i32> %out1757}1758 1759; Ensure we don't match a right shift by zero to the immediate form.1760define <vscale x 4 x i32> @lsr_i32_too_small(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {1761; CHECK-LABEL: lsr_i32_too_small:1762; CHECK: // %bb.0:1763; CHECK-NEXT: movi v1.2d, #00000000000000001764; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z1.s1765; CHECK-NEXT: ret1766 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %pg,1767 <vscale x 4 x i32> %a,1768 <vscale x 4 x i32> zeroinitializer)1769 ret <vscale x 4 x i32> %out1770}1771 1772define <vscale x 2 x i64> @lsr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {1773; CHECK-LABEL: lsr_i64:1774; CHECK: // %bb.0:1775; CHECK-NEXT: lsr z0.d, p0/m, z0.d, #641776; CHECK-NEXT: ret1777 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> %pg,1778 <vscale x 2 x i64> %a,1779 <vscale x 2 x i64> splat(i64 65))1780 ret <vscale x 2 x i64> %out1781}1782 1783define <vscale x 2 x i64> @lsr_i64_all_active(<vscale x 2 x i64> %a) {1784; CHECK-LABEL: lsr_i64_all_active:1785; CHECK: // %bb.0:1786; CHECK-NEXT: lsr z0.d, z0.d, #641787; CHECK-NEXT: ret1788 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)1789 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.u.nxv2i64(<vscale x 2 x i1> %pg,1790 <vscale x 2 x i64> %a,1791 <vscale x 2 x i64> splat(i64 64))1792 ret <vscale x 2 x i64> %out1793}1794 1795; Ensure we don't match a right shift by zero to the immediate form.1796define <vscale x 2 x i64> @lsr_i64_too_small(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {1797; CHECK-LABEL: lsr_i64_too_small:1798; CHECK: // %bb.0:1799; CHECK-NEXT: movi v1.2d, #00000000000000001800; CHECK-NEXT: lsr z0.d, p0/m, z0.d, z1.d1801; CHECK-NEXT: ret1802 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> %pg,1803 <vscale x 2 x i64> %a,1804 <vscale x 2 x i64> zeroinitializer)1805 ret <vscale x 2 x i64> %out1806}1807 1808; As lsr_i32 but where pg is i8 based and thus compatible for i32.1809define <vscale x 4 x i32> @lsr_i32_ptrue_all_b(<vscale x 4 x i32> %a) #0 {1810; CHECK-LABEL: lsr_i32_ptrue_all_b:1811; CHECK: // %bb.0:1812; CHECK-NEXT: lsr z0.s, z0.s, #11813; CHECK-NEXT: ret1814 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)1815 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)1816 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)1817 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.u.nxv4i32(<vscale x 4 x i1> %pg.s,1818 <vscale x 4 x i32> %a,1819 <vscale x 4 x i32> %b)1820 ret <vscale x 4 x i32> %out1821}1822 1823; As lsr_i32 but where pg is i16 based and thus compatible for i32.1824define <vscale x 4 x i32> @lsr_i32_ptrue_all_h(<vscale x 4 x i32> %a) #0 {1825; CHECK-LABEL: lsr_i32_ptrue_all_h:1826; CHECK: // %bb.0:1827; CHECK-NEXT: lsr z0.s, z0.s, #11828; CHECK-NEXT: ret1829 %pg.h = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)1830 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %pg.h)1831 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)1832 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)1833 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.u.nxv4i32(<vscale x 4 x i1> %pg.s,1834 <vscale x 4 x i32> %a,1835 <vscale x 4 x i32> %b)1836 ret <vscale x 4 x i32> %out1837}1838 1839; As lsr_i32 but where pg is i64 based, which is not compatibile for i32 and1840; thus inactive lanes are important and the immediate form cannot be used.1841define <vscale x 4 x i32> @lsr_i32_ptrue_all_d(<vscale x 4 x i32> %a) #0 {1842; CHECK-LABEL: lsr_i32_ptrue_all_d:1843; CHECK: // %bb.0:1844; CHECK-NEXT: ptrue p0.d1845; CHECK-NEXT: lsr z0.s, p0/m, z0.s, #11846; CHECK-NEXT: ret1847 %pg.d = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)1848 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg.d)1849 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)1850 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)1851 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %pg.s,1852 <vscale x 4 x i32> %a,1853 <vscale x 4 x i32> %b)1854 ret <vscale x 4 x i32> %out1855}1856 1857;1858; MUL1859;1860 1861; As mul_i32 but where pg is i8 based and thus compatible for i32.1862define <vscale x 4 x i32> @mul_i32_ptrue_all_b(<vscale x 4 x i32> %a) #0 {1863; CHECK-LABEL: mul_i32_ptrue_all_b:1864; CHECK: // %bb.0:1865; CHECK-NEXT: mul z0.s, z0.s, #11866; CHECK-NEXT: ret1867 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)1868 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)1869 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)1870 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1> %pg.s,1871 <vscale x 4 x i32> %a,1872 <vscale x 4 x i32> %b)1873 ret <vscale x 4 x i32> %out1874}1875 1876; As mul_i32 but where pg is i16 based and thus compatible for i32.1877define <vscale x 4 x i32> @mul_i32_ptrue_all_h(<vscale x 4 x i32> %a) #0 {1878; CHECK-LABEL: mul_i32_ptrue_all_h:1879; CHECK: // %bb.0:1880; CHECK-NEXT: mul z0.s, z0.s, #11881; CHECK-NEXT: ret1882 %pg.h = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)1883 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %pg.h)1884 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)1885 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)1886 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1> %pg.s,1887 <vscale x 4 x i32> %a,1888 <vscale x 4 x i32> %b)1889 ret <vscale x 4 x i32> %out1890}1891 1892; As mul_i32 but where pg is i64 based, which is not compatibile for i32 and1893; thus inactive lanes are important and the immediate form cannot be used.1894define <vscale x 4 x i32> @mul_i32_ptrue_all_d(<vscale x 4 x i32> %a) #0 {1895; CHECK-LABEL: mul_i32_ptrue_all_d:1896; CHECK: // %bb.0:1897; CHECK-NEXT: mov z1.s, #1 // =0x11898; CHECK-NEXT: ptrue p0.d1899; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s1900; CHECK-NEXT: ret1901 %pg.d = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)1902 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg.d)1903 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)1904 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1)1905 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1> %pg.s,1906 <vscale x 4 x i32> %a,1907 <vscale x 4 x i32> %b)1908 ret <vscale x 4 x i32> %out1909}1910 1911declare <vscale x 16 x i8> @llvm.aarch64.sve.add.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1912declare <vscale x 8 x i16> @llvm.aarch64.sve.add.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1913declare <vscale x 4 x i32> @llvm.aarch64.sve.add.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1914declare <vscale x 2 x i64> @llvm.aarch64.sve.add.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1915 1916declare <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1917 1918declare <vscale x 16 x i8> @llvm.aarch64.sve.sub.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1919declare <vscale x 8 x i16> @llvm.aarch64.sve.sub.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1920declare <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1921declare <vscale x 2 x i64> @llvm.aarch64.sve.sub.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1922 1923declare <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1924declare <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1925declare <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1926declare <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1927 1928declare <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)1929declare <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)1930declare <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)1931declare <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)1932 1933declare <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)1934declare <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)1935declare <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)1936declare <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)1937 1938declare <vscale x 16 x i8> @llvm.aarch64.sve.uqadd.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)1939declare <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)1940declare <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)1941declare <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)1942 1943declare <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)1944declare <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)1945declare <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)1946declare <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)1947 1948declare <vscale x 4 x i32> @llvm.aarch64.sve.smax.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1949 1950declare <vscale x 16 x i8> @llvm.aarch64.sve.smax.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1951declare <vscale x 8 x i16> @llvm.aarch64.sve.smax.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1952declare <vscale x 4 x i32> @llvm.aarch64.sve.smax.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1953declare <vscale x 2 x i64> @llvm.aarch64.sve.smax.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1954 1955declare <vscale x 4 x i32> @llvm.aarch64.sve.smin.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1956 1957declare <vscale x 16 x i8> @llvm.aarch64.sve.smin.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1958declare <vscale x 8 x i16> @llvm.aarch64.sve.smin.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1959declare <vscale x 4 x i32> @llvm.aarch64.sve.smin.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1960declare <vscale x 2 x i64> @llvm.aarch64.sve.smin.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1961 1962declare <vscale x 4 x i32> @llvm.aarch64.sve.umax.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1963 1964declare <vscale x 16 x i8> @llvm.aarch64.sve.umax.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1965declare <vscale x 8 x i16> @llvm.aarch64.sve.umax.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1966declare <vscale x 4 x i32> @llvm.aarch64.sve.umax.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1967declare <vscale x 2 x i64> @llvm.aarch64.sve.umax.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1968 1969declare <vscale x 4 x i32> @llvm.aarch64.sve.umin.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1970 1971declare <vscale x 16 x i8> @llvm.aarch64.sve.umin.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1972declare <vscale x 8 x i16> @llvm.aarch64.sve.umin.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1973declare <vscale x 4 x i32> @llvm.aarch64.sve.umin.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1974declare <vscale x 2 x i64> @llvm.aarch64.sve.umin.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1975 1976declare <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1977declare <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1978declare <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1979declare <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1980 1981declare <vscale x 16 x i8> @llvm.aarch64.sve.asr.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1982declare <vscale x 8 x i16> @llvm.aarch64.sve.asr.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1983declare <vscale x 4 x i32> @llvm.aarch64.sve.asr.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1984declare <vscale x 2 x i64> @llvm.aarch64.sve.asr.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1985 1986declare <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1987declare <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1988declare <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1989declare <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1990 1991declare <vscale x 16 x i8> @llvm.aarch64.sve.lsl.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1992declare <vscale x 8 x i16> @llvm.aarch64.sve.lsl.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1993declare <vscale x 4 x i32> @llvm.aarch64.sve.lsl.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1994declare <vscale x 2 x i64> @llvm.aarch64.sve.lsl.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1995 1996declare <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1997declare <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1998declare <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1999declare <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)2000 2001declare <vscale x 16 x i8> @llvm.aarch64.sve.lsr.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)2002declare <vscale x 8 x i16> @llvm.aarch64.sve.lsr.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)2003declare <vscale x 4 x i32> @llvm.aarch64.sve.lsr.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)2004declare <vscale x 2 x i64> @llvm.aarch64.sve.lsr.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)2005 2006declare <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)2007 2008declare <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)2009declare <vscale x 8 x i16> @llvm.aarch64.sve.mul.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)2010declare <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)2011declare <vscale x 2 x i64> @llvm.aarch64.sve.mul.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)2012 2013declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>)2014declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>)2015declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>)2016 2017declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 16 x i1>)2018declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>)2019declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>)2020 2021declare <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32)2022 2023declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 %pattern)2024declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 %pattern)2025declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 %pattern)2026declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 %pattern)2027