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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -mattr=+use-experimental-zeroing-pseudos < %s | FileCheck %s3 4;5; ADD6;7 8define <vscale x 16 x i8> @add_i8_zero(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {9; CHECK-LABEL: add_i8_zero:10; CHECK: // %bb.0:11; CHECK-NEXT: movprfx z0.b, p0/z, z0.b12; CHECK-NEXT: add z0.b, p0/m, z0.b, z1.b13; CHECK-NEXT: ret14 %a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer15 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1> %pg,16 <vscale x 16 x i8> %a_z,17 <vscale x 16 x i8> %b)18 ret <vscale x 16 x i8> %out19}20 21define <vscale x 8 x i16> @add_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {22; CHECK-LABEL: add_i16_zero:23; CHECK: // %bb.0:24; CHECK-NEXT: movprfx z0.h, p0/z, z0.h25; CHECK-NEXT: add z0.h, p0/m, z0.h, z1.h26; CHECK-NEXT: ret27 %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer28 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.add.nxv8i16(<vscale x 8 x i1> %pg,29 <vscale x 8 x i16> %a_z,30 <vscale x 8 x i16> %b)31 ret <vscale x 8 x i16> %out32}33 34define <vscale x 4 x i32> @add_i32_zero(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {35; CHECK-LABEL: add_i32_zero:36; CHECK: // %bb.0:37; CHECK-NEXT: movprfx z0.s, p0/z, z0.s38; CHECK-NEXT: add z0.s, p0/m, z0.s, z1.s39; CHECK-NEXT: ret40 %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer41 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> %pg,42 <vscale x 4 x i32> %a_z,43 <vscale x 4 x i32> %b)44 ret <vscale x 4 x i32> %out45}46 47define <vscale x 2 x i64> @add_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {48; CHECK-LABEL: add_i64_zero:49; CHECK: // %bb.0:50; CHECK-NEXT: movprfx z0.d, p0/z, z0.d51; CHECK-NEXT: add z0.d, p0/m, z0.d, z1.d52; CHECK-NEXT: ret53 %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer54 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.add.nxv2i64(<vscale x 2 x i1> %pg,55 <vscale x 2 x i64> %a_z,56 <vscale x 2 x i64> %b)57 ret <vscale x 2 x i64> %out58}59 60;61; SUB62;63 64define <vscale x 16 x i8> @sub_i8_zero(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {65; CHECK-LABEL: sub_i8_zero:66; CHECK: // %bb.0:67; CHECK-NEXT: movprfx z0.b, p0/z, z0.b68; CHECK-NEXT: sub z0.b, p0/m, z0.b, z1.b69; CHECK-NEXT: ret70 %a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer71 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1> %pg,72 <vscale x 16 x i8> %a_z,73 <vscale x 16 x i8> %b)74 ret <vscale x 16 x i8> %out75}76 77define <vscale x 8 x i16> @sub_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {78; CHECK-LABEL: sub_i16_zero:79; CHECK: // %bb.0:80; CHECK-NEXT: movprfx z0.h, p0/z, z0.h81; CHECK-NEXT: sub z0.h, p0/m, z0.h, z1.h82; CHECK-NEXT: ret83 %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer84 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.nxv8i16(<vscale x 8 x i1> %pg,85 <vscale x 8 x i16> %a_z,86 <vscale x 8 x i16> %b)87 ret <vscale x 8 x i16> %out88}89 90define <vscale x 4 x i32> @sub_i32_zero(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {91; CHECK-LABEL: sub_i32_zero:92; CHECK: // %bb.0:93; CHECK-NEXT: movprfx z0.s, p0/z, z0.s94; CHECK-NEXT: sub z0.s, p0/m, z0.s, z1.s95; CHECK-NEXT: ret96 %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer97 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1> %pg,98 <vscale x 4 x i32> %a_z,99 <vscale x 4 x i32> %b)100 ret <vscale x 4 x i32> %out101}102 103define <vscale x 2 x i64> @sub_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {104; CHECK-LABEL: sub_i64_zero:105; CHECK: // %bb.0:106; CHECK-NEXT: movprfx z0.d, p0/z, z0.d107; CHECK-NEXT: sub z0.d, p0/m, z0.d, z1.d108; CHECK-NEXT: ret109 %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer110 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.nxv2i64(<vscale x 2 x i1> %pg,111 <vscale x 2 x i64> %a_z,112 <vscale x 2 x i64> %b)113 ret <vscale x 2 x i64> %out114}115 116;117; SUBR118;119 120define <vscale x 16 x i8> @subr_i8_zero(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {121; CHECK-LABEL: subr_i8_zero:122; CHECK: // %bb.0:123; CHECK-NEXT: movprfx z0.b, p0/z, z0.b124; CHECK-NEXT: subr z0.b, p0/m, z0.b, z1.b125; CHECK-NEXT: ret126 %a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer127 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1> %pg,128 <vscale x 16 x i8> %a_z,129 <vscale x 16 x i8> %b)130 ret <vscale x 16 x i8> %out131}132 133define <vscale x 8 x i16> @subr_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {134; CHECK-LABEL: subr_i16_zero:135; CHECK: // %bb.0:136; CHECK-NEXT: movprfx z0.h, p0/z, z0.h137; CHECK-NEXT: subr z0.h, p0/m, z0.h, z1.h138; CHECK-NEXT: ret139 %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer140 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1> %pg,141 <vscale x 8 x i16> %a_z,142 <vscale x 8 x i16> %b)143 ret <vscale x 8 x i16> %out144}145 146define <vscale x 4 x i32> @subr_i32_zero(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {147; CHECK-LABEL: subr_i32_zero:148; CHECK: // %bb.0:149; CHECK-NEXT: movprfx z0.s, p0/z, z0.s150; CHECK-NEXT: subr z0.s, p0/m, z0.s, z1.s151; CHECK-NEXT: ret152 %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer153 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %pg,154 <vscale x 4 x i32> %a_z,155 <vscale x 4 x i32> %b)156 ret <vscale x 4 x i32> %out157}158 159define <vscale x 2 x i64> @subr_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {160; CHECK-LABEL: subr_i64_zero:161; CHECK: // %bb.0:162; CHECK-NEXT: movprfx z0.d, p0/z, z0.d163; CHECK-NEXT: subr z0.d, p0/m, z0.d, z1.d164; CHECK-NEXT: ret165 %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer166 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1> %pg,167 <vscale x 2 x i64> %a_z,168 <vscale x 2 x i64> %b)169 ret <vscale x 2 x i64> %out170}171 172;173; ORR174;175 176define <vscale x 16 x i8> @orr_i8_zero(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {177; CHECK-LABEL: orr_i8_zero:178; CHECK: // %bb.0:179; CHECK-NEXT: movprfx z0.b, p0/z, z0.b180; CHECK-NEXT: orr z0.b, p0/m, z0.b, z1.b181; CHECK-NEXT: ret182 %a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer183 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> %pg,184 <vscale x 16 x i8> %a_z,185 <vscale x 16 x i8> %b)186 ret <vscale x 16 x i8> %out187}188 189define <vscale x 8 x i16> @orr_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {190; CHECK-LABEL: orr_i16_zero:191; CHECK: // %bb.0:192; CHECK-NEXT: movprfx z0.h, p0/z, z0.h193; CHECK-NEXT: orr z0.h, p0/m, z0.h, z1.h194; CHECK-NEXT: ret195 %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer196 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> %pg,197 <vscale x 8 x i16> %a_z,198 <vscale x 8 x i16> %b)199 ret <vscale x 8 x i16> %out200}201 202define <vscale x 4 x i32> @orr_i32_zero(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {203; CHECK-LABEL: orr_i32_zero:204; CHECK: // %bb.0:205; CHECK-NEXT: movprfx z0.s, p0/z, z0.s206; CHECK-NEXT: orr z0.s, p0/m, z0.s, z1.s207; CHECK-NEXT: ret208 %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer209 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> %pg,210 <vscale x 4 x i32> %a_z,211 <vscale x 4 x i32> %b)212 ret <vscale x 4 x i32> %out213}214 215define <vscale x 2 x i64> @orr_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {216; CHECK-LABEL: orr_i64_zero:217; CHECK: // %bb.0:218; CHECK-NEXT: movprfx z0.d, p0/z, z0.d219; CHECK-NEXT: orr z0.d, p0/m, z0.d, z1.d220; CHECK-NEXT: ret221 %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer222 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> %pg,223 <vscale x 2 x i64> %a_z,224 <vscale x 2 x i64> %b)225 ret <vscale x 2 x i64> %out226}227 228;229; EOR230;231 232define <vscale x 16 x i8> @eor_i8_zero(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {233; CHECK-LABEL: eor_i8_zero:234; CHECK: // %bb.0:235; CHECK-NEXT: movprfx z0.b, p0/z, z0.b236; CHECK-NEXT: eor z0.b, p0/m, z0.b, z1.b237; CHECK-NEXT: ret238 %a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer239 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.eor.nxv16i8(<vscale x 16 x i1> %pg,240 <vscale x 16 x i8> %a_z,241 <vscale x 16 x i8> %b)242 ret <vscale x 16 x i8> %out243}244 245define <vscale x 8 x i16> @eor_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {246; CHECK-LABEL: eor_i16_zero:247; CHECK: // %bb.0:248; CHECK-NEXT: movprfx z0.h, p0/z, z0.h249; CHECK-NEXT: eor z0.h, p0/m, z0.h, z1.h250; CHECK-NEXT: ret251 %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer252 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.eor.nxv8i16(<vscale x 8 x i1> %pg,253 <vscale x 8 x i16> %a_z,254 <vscale x 8 x i16> %b)255 ret <vscale x 8 x i16> %out256}257 258define <vscale x 4 x i32> @eor_i32_zero(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {259; CHECK-LABEL: eor_i32_zero:260; CHECK: // %bb.0:261; CHECK-NEXT: movprfx z0.s, p0/z, z0.s262; CHECK-NEXT: eor z0.s, p0/m, z0.s, z1.s263; CHECK-NEXT: ret264 %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer265 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1> %pg,266 <vscale x 4 x i32> %a_z,267 <vscale x 4 x i32> %b)268 ret <vscale x 4 x i32> %out269}270 271define <vscale x 2 x i64> @eor_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {272; CHECK-LABEL: eor_i64_zero:273; CHECK: // %bb.0:274; CHECK-NEXT: movprfx z0.d, p0/z, z0.d275; CHECK-NEXT: eor z0.d, p0/m, z0.d, z1.d276; CHECK-NEXT: ret277 %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer278 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.eor.nxv2i64(<vscale x 2 x i1> %pg,279 <vscale x 2 x i64> %a_z,280 <vscale x 2 x i64> %b)281 ret <vscale x 2 x i64> %out282}283 284;285; AND286;287 288define <vscale x 16 x i8> @and_i8_zero(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {289; CHECK-LABEL: and_i8_zero:290; CHECK: // %bb.0:291; CHECK-NEXT: movprfx z0.b, p0/z, z0.b292; CHECK-NEXT: and z0.b, p0/m, z0.b, z1.b293; CHECK-NEXT: ret294 %a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer295 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.and.nxv16i8(<vscale x 16 x i1> %pg,296 <vscale x 16 x i8> %a_z,297 <vscale x 16 x i8> %b)298 ret <vscale x 16 x i8> %out299}300 301define <vscale x 8 x i16> @and_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {302; CHECK-LABEL: and_i16_zero:303; CHECK: // %bb.0:304; CHECK-NEXT: movprfx z0.h, p0/z, z0.h305; CHECK-NEXT: and z0.h, p0/m, z0.h, z1.h306; CHECK-NEXT: ret307 %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer308 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.and.nxv8i16(<vscale x 8 x i1> %pg,309 <vscale x 8 x i16> %a_z,310 <vscale x 8 x i16> %b)311 ret <vscale x 8 x i16> %out312}313 314define <vscale x 4 x i32> @and_i32_zero(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {315; CHECK-LABEL: and_i32_zero:316; CHECK: // %bb.0:317; CHECK-NEXT: movprfx z0.s, p0/z, z0.s318; CHECK-NEXT: and z0.s, p0/m, z0.s, z1.s319; CHECK-NEXT: ret320 %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer321 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1> %pg,322 <vscale x 4 x i32> %a_z,323 <vscale x 4 x i32> %b)324 ret <vscale x 4 x i32> %out325}326 327define <vscale x 2 x i64> @and_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {328; CHECK-LABEL: and_i64_zero:329; CHECK: // %bb.0:330; CHECK-NEXT: movprfx z0.d, p0/z, z0.d331; CHECK-NEXT: and z0.d, p0/m, z0.d, z1.d332; CHECK-NEXT: ret333 %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer334 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.and.nxv2i64(<vscale x 2 x i1> %pg,335 <vscale x 2 x i64> %a_z,336 <vscale x 2 x i64> %b)337 ret <vscale x 2 x i64> %out338}339 340;341; BIC342;343 344define <vscale x 16 x i8> @bic_i8_zero(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {345; CHECK-LABEL: bic_i8_zero:346; CHECK: // %bb.0:347; CHECK-NEXT: movprfx z0.b, p0/z, z0.b348; CHECK-NEXT: bic z0.b, p0/m, z0.b, z1.b349; CHECK-NEXT: ret350 %a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer351 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.bic.nxv16i8(<vscale x 16 x i1> %pg,352 <vscale x 16 x i8> %a_z,353 <vscale x 16 x i8> %b)354 ret <vscale x 16 x i8> %out355}356 357define <vscale x 8 x i16> @bic_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {358; CHECK-LABEL: bic_i16_zero:359; CHECK: // %bb.0:360; CHECK-NEXT: movprfx z0.h, p0/z, z0.h361; CHECK-NEXT: bic z0.h, p0/m, z0.h, z1.h362; CHECK-NEXT: ret363 %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer364 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv8i16(<vscale x 8 x i1> %pg,365 <vscale x 8 x i16> %a_z,366 <vscale x 8 x i16> %b)367 ret <vscale x 8 x i16> %out368}369 370define <vscale x 4 x i32> @bic_i32_zero(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {371; CHECK-LABEL: bic_i32_zero:372; CHECK: // %bb.0:373; CHECK-NEXT: movprfx z0.s, p0/z, z0.s374; CHECK-NEXT: bic z0.s, p0/m, z0.s, z1.s375; CHECK-NEXT: ret376 %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer377 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.bic.nxv4i32(<vscale x 4 x i1> %pg,378 <vscale x 4 x i32> %a_z,379 <vscale x 4 x i32> %b)380 ret <vscale x 4 x i32> %out381}382 383define <vscale x 2 x i64> @bic_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {384; CHECK-LABEL: bic_i64_zero:385; CHECK: // %bb.0:386; CHECK-NEXT: movprfx z0.d, p0/z, z0.d387; CHECK-NEXT: bic z0.d, p0/m, z0.d, z1.d388; CHECK-NEXT: ret389 %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer390 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.bic.nxv2i64(<vscale x 2 x i1> %pg,391 <vscale x 2 x i64> %a_z,392 <vscale x 2 x i64> %b)393 ret <vscale x 2 x i64> %out394}395 396; BIC (i.e. A & ~A) is illegal operation with movprfx, so the codegen depend on IR before expand-pseudo397define <vscale x 2 x i64> @bic_i64_zero_no_unique_reg(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {398; CHECK-LABEL: bic_i64_zero_no_unique_reg:399; CHECK: // %bb.0:400; CHECK-NEXT: movi v1.2d, #0000000000000000401; CHECK-NEXT: mov z1.d, p0/m, z0.d402; CHECK-NEXT: movprfx z0.d, p0/z, z0.d403; CHECK-NEXT: bic z0.d, p0/m, z0.d, z1.d404; CHECK-NEXT: ret405 %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer406 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.bic.nxv2i64(<vscale x 2 x i1> %pg,407 <vscale x 2 x i64> %a_z,408 <vscale x 2 x i64> %a_z)409 ret <vscale x 2 x i64> %out410}411 412; BIC (i.e. A & ~B) is not a commutative operation, so disable it when the413; destination operand is not the destructive operand414define <vscale x 2 x i64> @bic_i64_zero_no_comm(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {415; CHECK-LABEL: bic_i64_zero_no_comm:416; CHECK: // %bb.0:417; CHECK-NEXT: movi v2.2d, #0000000000000000418; CHECK-NEXT: mov z2.d, p0/m, z0.d419; CHECK-NEXT: mov z0.d, z1.d420; CHECK-NEXT: bic z0.d, p0/m, z0.d, z2.d421; CHECK-NEXT: ret422 %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer423 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.bic.nxv2i64(<vscale x 2 x i1> %pg,424 <vscale x 2 x i64> %b,425 <vscale x 2 x i64> %a_z)426 ret <vscale x 2 x i64> %out427}428 429declare <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)430declare <vscale x 8 x i16> @llvm.aarch64.sve.add.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)431declare <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)432declare <vscale x 2 x i64> @llvm.aarch64.sve.add.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)433 434declare <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)435declare <vscale x 8 x i16> @llvm.aarch64.sve.sub.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)436declare <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)437declare <vscale x 2 x i64> @llvm.aarch64.sve.sub.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)438 439declare <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)440declare <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)441declare <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)442declare <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)443 444declare <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)445declare <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)446declare <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)447declare <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)448 449declare <vscale x 16 x i8> @llvm.aarch64.sve.eor.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)450declare <vscale x 8 x i16> @llvm.aarch64.sve.eor.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)451declare <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)452declare <vscale x 2 x i64> @llvm.aarch64.sve.eor.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)453 454declare <vscale x 16 x i8> @llvm.aarch64.sve.and.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)455declare <vscale x 8 x i16> @llvm.aarch64.sve.and.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)456declare <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)457declare <vscale x 2 x i64> @llvm.aarch64.sve.and.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)458 459declare <vscale x 16 x i8> @llvm.aarch64.sve.bic.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)460declare <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)461declare <vscale x 4 x i32> @llvm.aarch64.sve.bic.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)462declare <vscale x 2 x i64> @llvm.aarch64.sve.bic.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)463