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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64 -mattr=+sve -mattr=+use-experimental-zeroing-pseudos -run-pass=aarch64-expand-pseudo %s -o - | FileCheck %s3 4# Should create an additional LSL to zero the lanes as the DstReg is not unique5 6--- |7 define <vscale x 8 x i16> @bic_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a){8 %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer9 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a_z, <vscale x 8 x i16> %a_z)10 ret <vscale x 8 x i16> %out11 }12 13 declare <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)14...15---16name: bic_i16_zero17alignment: 418tracksRegLiveness: true19tracksDebugUserValues: true20registers: []21liveins:22 - { reg: '$p0', virtual-reg: '' }23 - { reg: '$z0', virtual-reg: '' }24body: |25 bb.0 (%ir-block.0):26 liveins: $p0, $z027 28 ; CHECK-LABEL: name: bic_i16_zero29 ; CHECK: liveins: $p0, $z030 ; CHECK-NEXT: {{ $}}31 ; CHECK-NEXT: BUNDLE implicit-def $z0, implicit killed $p0, implicit $z0 {32 ; CHECK-NEXT: $z0 = MOVPRFX_ZPzZ_H $p0, $z033 ; CHECK-NEXT: $z0 = LSL_ZPmI_H killed renamable $p0, internal $z0, 034 ; CHECK-NEXT: $z0 = BIC_ZPmZ_H killed renamable $p0, internal killed $z0, internal killed renamable $z035 ; CHECK-NEXT: }36 ; CHECK-NEXT: RET undef $lr, implicit $z037 renamable $z0 = BIC_ZPZZ_H_ZERO killed renamable $p0, killed renamable $z0, killed renamable $z038 RET_ReallyLR implicit $z039...40