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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mattr=+sve < %s | FileCheck %s -check-prefixes=CHECK,SVE13; RUN: llc -mattr=+sve2 < %s | FileCheck %s -check-prefixes=CHECK,SVE24 5target triple = "aarch64-unknown-linux-gnu"6 7;8; ADD9;10 11define <vscale x 16 x i8> @add_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {12; CHECK-LABEL: add_i8:13; CHECK: // %bb.0:14; CHECK-NEXT: add z0.b, z0.b, z1.b15; CHECK-NEXT: ret16 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.add.u.nxv16i8(<vscale x 16 x i1> %pg,17 <vscale x 16 x i8> %a,18 <vscale x 16 x i8> %b)19 ret <vscale x 16 x i8> %out20}21 22define <vscale x 8 x i16> @add_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {23; CHECK-LABEL: add_i16:24; CHECK: // %bb.0:25; CHECK-NEXT: add z0.h, z0.h, z1.h26; CHECK-NEXT: ret27 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.add.u.nxv8i16(<vscale x 8 x i1> %pg,28 <vscale x 8 x i16> %a,29 <vscale x 8 x i16> %b)30 ret <vscale x 8 x i16> %out31}32 33define <vscale x 4 x i32> @add_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {34; CHECK-LABEL: add_i32:35; CHECK: // %bb.0:36; CHECK-NEXT: add z0.s, z0.s, z1.s37; CHECK-NEXT: ret38 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.add.u.nxv4i32(<vscale x 4 x i1> %pg,39 <vscale x 4 x i32> %a,40 <vscale x 4 x i32> %b)41 ret <vscale x 4 x i32> %out42}43 44define <vscale x 2 x i64> @add_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {45; CHECK-LABEL: add_i64:46; CHECK: // %bb.0:47; CHECK-NEXT: add z0.d, z0.d, z1.d48; CHECK-NEXT: ret49 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.add.u.nxv2i64(<vscale x 2 x i1> %pg,50 <vscale x 2 x i64> %a,51 <vscale x 2 x i64> %b)52 ret <vscale x 2 x i64> %out53}54 55;56; ADD (immediate)57;58 59define <vscale x 16 x i8> @add_imm_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {60; CHECK-LABEL: add_imm_i8:61; CHECK: // %bb.0:62; CHECK-NEXT: add z0.b, z0.b, #3 // =0x363; CHECK-NEXT: ret64 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.add.u.nxv16i8(<vscale x 16 x i1> %pg,65 <vscale x 16 x i8> %a,66 <vscale x 16 x i8> splat(i8 3))67 ret <vscale x 16 x i8> %out68}69 70define <vscale x 8 x i16> @add_imm_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {71; CHECK-LABEL: add_imm_i16:72; CHECK: // %bb.0:73; CHECK-NEXT: add z0.h, z0.h, #4 // =0x474; CHECK-NEXT: ret75 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.add.u.nxv8i16(<vscale x 8 x i1> %pg,76 <vscale x 8 x i16> %a,77 <vscale x 8 x i16> splat(i16 4))78 ret <vscale x 8 x i16> %out79}80 81define <vscale x 4 x i32> @add_imm_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {82; CHECK-LABEL: add_imm_i32:83; CHECK: // %bb.0:84; CHECK-NEXT: add z0.s, z0.s, #5 // =0x585; CHECK-NEXT: ret86 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.add.u.nxv4i32(<vscale x 4 x i1> %pg,87 <vscale x 4 x i32> %a,88 <vscale x 4 x i32> splat(i32 5))89 ret <vscale x 4 x i32> %out90}91 92define <vscale x 2 x i64> @add_imm_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {93; CHECK-LABEL: add_imm_i64:94; CHECK: // %bb.0:95; CHECK-NEXT: add z0.d, z0.d, #6 // =0x696; CHECK-NEXT: ret97 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.add.u.nxv2i64(<vscale x 2 x i1> %pg,98 <vscale x 2 x i64> %a,99 <vscale x 2 x i64> splat(i64 6))100 ret <vscale x 2 x i64> %out101}102 103;104; MLA105;106 107define <vscale x 16 x i8> @mla_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {108; CHECK-LABEL: mla_i8:109; CHECK: // %bb.0:110; CHECK-NEXT: mla z0.b, p0/m, z1.b, z2.b111; CHECK-NEXT: ret112 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.mla.u.nxv16i8(<vscale x 16 x i1> %pg,113 <vscale x 16 x i8> %a,114 <vscale x 16 x i8> %b,115 <vscale x 16 x i8> %c)116 ret <vscale x 16 x i8> %out117}118 119define <vscale x 8 x i16> @mla_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {120; CHECK-LABEL: mla_i16:121; CHECK: // %bb.0:122; CHECK-NEXT: mla z0.h, p0/m, z1.h, z2.h123; CHECK-NEXT: ret124 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.mla.u.nxv8i16(<vscale x 8 x i1> %pg,125 <vscale x 8 x i16> %a,126 <vscale x 8 x i16> %b,127 <vscale x 8 x i16> %c)128 ret <vscale x 8 x i16> %out129}130 131define <vscale x 4 x i32> @mla_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {132; CHECK-LABEL: mla_i32:133; CHECK: // %bb.0:134; CHECK-NEXT: mla z0.s, p0/m, z1.s, z2.s135; CHECK-NEXT: ret136 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> %pg,137 <vscale x 4 x i32> %a,138 <vscale x 4 x i32> %b,139 <vscale x 4 x i32> %c)140 ret <vscale x 4 x i32> %out141}142 143define <vscale x 2 x i64> @mla_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {144; CHECK-LABEL: mla_i64:145; CHECK: // %bb.0:146; CHECK-NEXT: mla z0.d, p0/m, z1.d, z2.d147; CHECK-NEXT: ret148 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.mla.u.nxv2i64(<vscale x 2 x i1> %pg,149 <vscale x 2 x i64> %a,150 <vscale x 2 x i64> %b,151 <vscale x 2 x i64> %c)152 ret <vscale x 2 x i64> %out153}154 155;156; MLS157;158 159define <vscale x 16 x i8> @mls_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {160; CHECK-LABEL: mls_i8:161; CHECK: // %bb.0:162; CHECK-NEXT: mls z0.b, p0/m, z1.b, z2.b163; CHECK-NEXT: ret164 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.mls.u.nxv16i8(<vscale x 16 x i1> %pg,165 <vscale x 16 x i8> %a,166 <vscale x 16 x i8> %b,167 <vscale x 16 x i8> %c)168 ret <vscale x 16 x i8> %out169}170 171define <vscale x 8 x i16> @mls_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {172; CHECK-LABEL: mls_i16:173; CHECK: // %bb.0:174; CHECK-NEXT: mls z0.h, p0/m, z1.h, z2.h175; CHECK-NEXT: ret176 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.mls.u.nxv8i16(<vscale x 8 x i1> %pg,177 <vscale x 8 x i16> %a,178 <vscale x 8 x i16> %b,179 <vscale x 8 x i16> %c)180 ret <vscale x 8 x i16> %out181}182 183define <vscale x 4 x i32> @mls_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {184; CHECK-LABEL: mls_i32:185; CHECK: // %bb.0:186; CHECK-NEXT: mls z0.s, p0/m, z1.s, z2.s187; CHECK-NEXT: ret188 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mls.u.nxv4i32(<vscale x 4 x i1> %pg,189 <vscale x 4 x i32> %a,190 <vscale x 4 x i32> %b,191 <vscale x 4 x i32> %c)192 ret <vscale x 4 x i32> %out193}194 195define <vscale x 2 x i64> @mls_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {196; CHECK-LABEL: mls_i64:197; CHECK: // %bb.0:198; CHECK-NEXT: mls z0.d, p0/m, z1.d, z2.d199; CHECK-NEXT: ret200 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.mls.u.nxv2i64(<vscale x 2 x i1> %pg,201 <vscale x 2 x i64> %a,202 <vscale x 2 x i64> %b,203 <vscale x 2 x i64> %c)204 ret <vscale x 2 x i64> %out205}206 207;208; MUL209;210 211define <vscale x 16 x i8> @mul_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {212; SVE1-LABEL: mul_i8:213; SVE1: // %bb.0:214; SVE1-NEXT: mul z0.b, p0/m, z0.b, z1.b215; SVE1-NEXT: ret216;217; SVE2-LABEL: mul_i8:218; SVE2: // %bb.0:219; SVE2-NEXT: mul z0.b, z0.b, z1.b220; SVE2-NEXT: ret221 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1> %pg,222 <vscale x 16 x i8> %a,223 <vscale x 16 x i8> %b)224 ret <vscale x 16 x i8> %out225}226 227define <vscale x 8 x i16> @mul_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {228; SVE1-LABEL: mul_i16:229; SVE1: // %bb.0:230; SVE1-NEXT: mul z0.h, p0/m, z0.h, z1.h231; SVE1-NEXT: ret232;233; SVE2-LABEL: mul_i16:234; SVE2: // %bb.0:235; SVE2-NEXT: mul z0.h, z0.h, z1.h236; SVE2-NEXT: ret237 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.mul.u.nxv8i16(<vscale x 8 x i1> %pg,238 <vscale x 8 x i16> %a,239 <vscale x 8 x i16> %b)240 ret <vscale x 8 x i16> %out241}242 243define <vscale x 4 x i32> @mul_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {244; SVE1-LABEL: mul_i32:245; SVE1: // %bb.0:246; SVE1-NEXT: mul z0.s, p0/m, z0.s, z1.s247; SVE1-NEXT: ret248;249; SVE2-LABEL: mul_i32:250; SVE2: // %bb.0:251; SVE2-NEXT: mul z0.s, z0.s, z1.s252; SVE2-NEXT: ret253 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1> %pg,254 <vscale x 4 x i32> %a,255 <vscale x 4 x i32> %b)256 ret <vscale x 4 x i32> %out257}258 259define <vscale x 2 x i64> @mul_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {260; SVE1-LABEL: mul_i64:261; SVE1: // %bb.0:262; SVE1-NEXT: mul z0.d, p0/m, z0.d, z1.d263; SVE1-NEXT: ret264;265; SVE2-LABEL: mul_i64:266; SVE2: // %bb.0:267; SVE2-NEXT: mul z0.d, z0.d, z1.d268; SVE2-NEXT: ret269 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.mul.u.nxv2i64(<vscale x 2 x i1> %pg,270 <vscale x 2 x i64> %a,271 <vscale x 2 x i64> %b)272 ret <vscale x 2 x i64> %out273}274 275;276; MUL (immediate)277;278 279define <vscale x 16 x i8> @mul_imm_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {280; CHECK-LABEL: mul_imm_i8:281; CHECK: // %bb.0:282; CHECK-NEXT: mul z0.b, z0.b, #3283; CHECK-NEXT: ret284 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1> %pg,285 <vscale x 16 x i8> %a,286 <vscale x 16 x i8> splat(i8 3))287 ret <vscale x 16 x i8> %out288}289 290define <vscale x 8 x i16> @mul_imm_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {291; CHECK-LABEL: mul_imm_i16:292; CHECK: // %bb.0:293; CHECK-NEXT: mul z0.h, z0.h, #4294; CHECK-NEXT: ret295 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.mul.u.nxv8i16(<vscale x 8 x i1> %pg,296 <vscale x 8 x i16> %a,297 <vscale x 8 x i16> splat(i16 4))298 ret <vscale x 8 x i16> %out299}300 301define <vscale x 4 x i32> @mul_imm_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {302; CHECK-LABEL: mul_imm_i32:303; CHECK: // %bb.0:304; CHECK-NEXT: mul z0.s, z0.s, #5305; CHECK-NEXT: ret306 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1> %pg,307 <vscale x 4 x i32> %a,308 <vscale x 4 x i32> splat(i32 5))309 ret <vscale x 4 x i32> %out310}311 312define <vscale x 2 x i64> @mul_imm_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {313; CHECK-LABEL: mul_imm_i64:314; CHECK: // %bb.0:315; CHECK-NEXT: mul z0.d, z0.d, #6316; CHECK-NEXT: ret317 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.mul.u.nxv2i64(<vscale x 2 x i1> %pg,318 <vscale x 2 x i64> %a,319 <vscale x 2 x i64> splat(i64 6))320 ret <vscale x 2 x i64> %out321}322 323;324; SABD325;326 327define <vscale x 16 x i8> @sabd_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {328; CHECK-LABEL: sabd_i8:329; CHECK: // %bb.0:330; CHECK-NEXT: ptrue p0.b331; CHECK-NEXT: sabd z0.b, p0/m, z0.b, z1.b332; CHECK-NEXT: ret333 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sabd.u.nxv16i8(<vscale x 16 x i1> %pg,334 <vscale x 16 x i8> %a,335 <vscale x 16 x i8> %b)336 ret <vscale x 16 x i8> %out337}338 339define <vscale x 8 x i16> @sabd_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {340; CHECK-LABEL: sabd_i16:341; CHECK: // %bb.0:342; CHECK-NEXT: ptrue p0.h343; CHECK-NEXT: sabd z0.h, p0/m, z0.h, z1.h344; CHECK-NEXT: ret345 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sabd.u.nxv8i16(<vscale x 8 x i1> %pg,346 <vscale x 8 x i16> %a,347 <vscale x 8 x i16> %b)348 ret <vscale x 8 x i16> %out349}350 351define <vscale x 4 x i32> @sabd_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {352; CHECK-LABEL: sabd_i32:353; CHECK: // %bb.0:354; CHECK-NEXT: ptrue p0.s355; CHECK-NEXT: sabd z0.s, p0/m, z0.s, z1.s356; CHECK-NEXT: ret357 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sabd.u.nxv4i32(<vscale x 4 x i1> %pg,358 <vscale x 4 x i32> %a,359 <vscale x 4 x i32> %b)360 ret <vscale x 4 x i32> %out361}362 363define <vscale x 2 x i64> @sabd_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {364; CHECK-LABEL: sabd_i64:365; CHECK: // %bb.0:366; CHECK-NEXT: ptrue p0.d367; CHECK-NEXT: sabd z0.d, p0/m, z0.d, z1.d368; CHECK-NEXT: ret369 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sabd.u.nxv2i64(<vscale x 2 x i1> %pg,370 <vscale x 2 x i64> %a,371 <vscale x 2 x i64> %b)372 ret <vscale x 2 x i64> %out373}374 375;376; SDIV377;378 379define <vscale x 4 x i32> @sdiv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {380; CHECK-LABEL: sdiv_i32:381; CHECK: // %bb.0:382; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s383; CHECK-NEXT: ret384 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.u.nxv4i32(<vscale x 4 x i1> %pg,385 <vscale x 4 x i32> %a,386 <vscale x 4 x i32> %b)387 ret <vscale x 4 x i32> %out388}389 390define <vscale x 2 x i64> @sdiv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {391; CHECK-LABEL: sdiv_i64:392; CHECK: // %bb.0:393; CHECK-NEXT: sdiv z0.d, p0/m, z0.d, z1.d394; CHECK-NEXT: ret395 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.u.nxv2i64(<vscale x 2 x i1> %pg,396 <vscale x 2 x i64> %a,397 <vscale x 2 x i64> %b)398 ret <vscale x 2 x i64> %out399}400 401;402; SDIVR403;404 405define <vscale x 4 x i32> @sdivr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {406; CHECK-LABEL: sdivr_i32:407; CHECK: // %bb.0:408; CHECK-NEXT: sdivr z0.s, p0/m, z0.s, z1.s409; CHECK-NEXT: ret410 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.u.nxv4i32(<vscale x 4 x i1> %pg,411 <vscale x 4 x i32> %b,412 <vscale x 4 x i32> %a)413 ret <vscale x 4 x i32> %out414}415 416define <vscale x 2 x i64> @sdivr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {417; CHECK-LABEL: sdivr_i64:418; CHECK: // %bb.0:419; CHECK-NEXT: sdivr z0.d, p0/m, z0.d, z1.d420; CHECK-NEXT: ret421 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.u.nxv2i64(<vscale x 2 x i1> %pg,422 <vscale x 2 x i64> %b,423 <vscale x 2 x i64> %a)424 ret <vscale x 2 x i64> %out425}426 427;428; SMAX429;430 431define <vscale x 16 x i8> @smax_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {432; CHECK-LABEL: smax_i8:433; CHECK: // %bb.0:434; CHECK-NEXT: smax z0.b, p0/m, z0.b, z1.b435; CHECK-NEXT: ret436 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.smax.u.nxv16i8(<vscale x 16 x i1> %pg,437 <vscale x 16 x i8> %a,438 <vscale x 16 x i8> %b)439 ret <vscale x 16 x i8> %out440}441 442define <vscale x 8 x i16> @smax_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {443; CHECK-LABEL: smax_i16:444; CHECK: // %bb.0:445; CHECK-NEXT: smax z0.h, p0/m, z0.h, z1.h446; CHECK-NEXT: ret447 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.smax.u.nxv8i16(<vscale x 8 x i1> %pg,448 <vscale x 8 x i16> %a,449 <vscale x 8 x i16> %b)450 ret <vscale x 8 x i16> %out451}452 453define <vscale x 4 x i32> @smax_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {454; CHECK-LABEL: smax_i32:455; CHECK: // %bb.0:456; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s457; CHECK-NEXT: ret458 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smax.u.nxv4i32(<vscale x 4 x i1> %pg,459 <vscale x 4 x i32> %a,460 <vscale x 4 x i32> %b)461 ret <vscale x 4 x i32> %out462}463 464define <vscale x 2 x i64> @smax_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {465; CHECK-LABEL: smax_i64:466; CHECK: // %bb.0:467; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d468; CHECK-NEXT: ret469 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smax.u.nxv2i64(<vscale x 2 x i1> %pg,470 <vscale x 2 x i64> %a,471 <vscale x 2 x i64> %b)472 ret <vscale x 2 x i64> %out473}474 475;476; SMAX (immediate)477;478 479define <vscale x 16 x i8> @smax_imm_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {480; CHECK-LABEL: smax_imm_i8:481; CHECK: // %bb.0:482; CHECK-NEXT: smax z0.b, z0.b, #3483; CHECK-NEXT: ret484 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.smax.u.nxv16i8(<vscale x 16 x i1> %pg,485 <vscale x 16 x i8> %a,486 <vscale x 16 x i8> splat(i8 3))487 ret <vscale x 16 x i8> %out488}489 490define <vscale x 8 x i16> @smax_imm_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {491; CHECK-LABEL: smax_imm_i16:492; CHECK: // %bb.0:493; CHECK-NEXT: smax z0.h, z0.h, #4494; CHECK-NEXT: ret495 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.smax.u.nxv8i16(<vscale x 8 x i1> %pg,496 <vscale x 8 x i16> %a,497 <vscale x 8 x i16> splat(i16 4))498 ret <vscale x 8 x i16> %out499}500 501define <vscale x 4 x i32> @smax_imm_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {502; CHECK-LABEL: smax_imm_i32:503; CHECK: // %bb.0:504; CHECK-NEXT: smax z0.s, z0.s, #5505; CHECK-NEXT: ret506 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smax.u.nxv4i32(<vscale x 4 x i1> %pg,507 <vscale x 4 x i32> %a,508 <vscale x 4 x i32> splat(i32 5))509 ret <vscale x 4 x i32> %out510}511 512define <vscale x 2 x i64> @smax_imm_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {513; CHECK-LABEL: smax_imm_i64:514; CHECK: // %bb.0:515; CHECK-NEXT: smax z0.d, z0.d, #6516; CHECK-NEXT: ret517 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smax.u.nxv2i64(<vscale x 2 x i1> %pg,518 <vscale x 2 x i64> %a,519 <vscale x 2 x i64> splat(i64 6))520 ret <vscale x 2 x i64> %out521}522 523;524; SMIN525;526 527define <vscale x 16 x i8> @smin_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {528; CHECK-LABEL: smin_i8:529; CHECK: // %bb.0:530; CHECK-NEXT: smin z0.b, p0/m, z0.b, z1.b531; CHECK-NEXT: ret532 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.smin.u.nxv16i8(<vscale x 16 x i1> %pg,533 <vscale x 16 x i8> %a,534 <vscale x 16 x i8> %b)535 ret <vscale x 16 x i8> %out536}537 538define <vscale x 8 x i16> @smin_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {539; CHECK-LABEL: smin_i16:540; CHECK: // %bb.0:541; CHECK-NEXT: smin z0.h, p0/m, z0.h, z1.h542; CHECK-NEXT: ret543 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.smin.u.nxv8i16(<vscale x 8 x i1> %pg,544 <vscale x 8 x i16> %a,545 <vscale x 8 x i16> %b)546 ret <vscale x 8 x i16> %out547}548 549define <vscale x 4 x i32> @smin_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {550; CHECK-LABEL: smin_i32:551; CHECK: // %bb.0:552; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s553; CHECK-NEXT: ret554 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smin.u.nxv4i32(<vscale x 4 x i1> %pg,555 <vscale x 4 x i32> %a,556 <vscale x 4 x i32> %b)557 ret <vscale x 4 x i32> %out558}559 560define <vscale x 2 x i64> @smin_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {561; CHECK-LABEL: smin_i64:562; CHECK: // %bb.0:563; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d564; CHECK-NEXT: ret565 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smin.u.nxv2i64(<vscale x 2 x i1> %pg,566 <vscale x 2 x i64> %a,567 <vscale x 2 x i64> %b)568 ret <vscale x 2 x i64> %out569}570 571;572; SMIN (immediate)573;574 575define <vscale x 16 x i8> @smin_imm_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {576; CHECK-LABEL: smin_imm_i8:577; CHECK: // %bb.0:578; CHECK-NEXT: smin z0.b, z0.b, #3579; CHECK-NEXT: ret580 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.smin.u.nxv16i8(<vscale x 16 x i1> %pg,581 <vscale x 16 x i8> %a,582 <vscale x 16 x i8> splat(i8 3))583 ret <vscale x 16 x i8> %out584}585 586define <vscale x 8 x i16> @smin_imm_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {587; CHECK-LABEL: smin_imm_i16:588; CHECK: // %bb.0:589; CHECK-NEXT: smin z0.h, z0.h, #4590; CHECK-NEXT: ret591 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.smin.u.nxv8i16(<vscale x 8 x i1> %pg,592 <vscale x 8 x i16> %a,593 <vscale x 8 x i16> splat(i16 4))594 ret <vscale x 8 x i16> %out595}596 597define <vscale x 4 x i32> @smin_imm_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {598; CHECK-LABEL: smin_imm_i32:599; CHECK: // %bb.0:600; CHECK-NEXT: smin z0.s, z0.s, #5601; CHECK-NEXT: ret602 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smin.u.nxv4i32(<vscale x 4 x i1> %pg,603 <vscale x 4 x i32> %a,604 <vscale x 4 x i32> splat(i32 5))605 ret <vscale x 4 x i32> %out606}607 608define <vscale x 2 x i64> @smin_imm_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {609; CHECK-LABEL: smin_imm_i64:610; CHECK: // %bb.0:611; CHECK-NEXT: smin z0.d, z0.d, #6612; CHECK-NEXT: ret613 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smin.u.nxv2i64(<vscale x 2 x i1> %pg,614 <vscale x 2 x i64> %a,615 <vscale x 2 x i64> splat(i64 6))616 ret <vscale x 2 x i64> %out617}618 619;620; SMULH621;622 623define <vscale x 16 x i8> @smulh_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {624; SVE1-LABEL: smulh_i8:625; SVE1: // %bb.0:626; SVE1-NEXT: smulh z0.b, p0/m, z0.b, z1.b627; SVE1-NEXT: ret628;629; SVE2-LABEL: smulh_i8:630; SVE2: // %bb.0:631; SVE2-NEXT: smulh z0.b, z0.b, z1.b632; SVE2-NEXT: ret633 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.smulh.u.nxv16i8(<vscale x 16 x i1> %pg,634 <vscale x 16 x i8> %a,635 <vscale x 16 x i8> %b)636 ret <vscale x 16 x i8> %out637}638 639define <vscale x 8 x i16> @smulh_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {640; SVE1-LABEL: smulh_i16:641; SVE1: // %bb.0:642; SVE1-NEXT: smulh z0.h, p0/m, z0.h, z1.h643; SVE1-NEXT: ret644;645; SVE2-LABEL: smulh_i16:646; SVE2: // %bb.0:647; SVE2-NEXT: smulh z0.h, z0.h, z1.h648; SVE2-NEXT: ret649 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.smulh.u.nxv8i16(<vscale x 8 x i1> %pg,650 <vscale x 8 x i16> %a,651 <vscale x 8 x i16> %b)652 ret <vscale x 8 x i16> %out653}654 655define <vscale x 4 x i32> @smulh_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {656; SVE1-LABEL: smulh_i32:657; SVE1: // %bb.0:658; SVE1-NEXT: smulh z0.s, p0/m, z0.s, z1.s659; SVE1-NEXT: ret660;661; SVE2-LABEL: smulh_i32:662; SVE2: // %bb.0:663; SVE2-NEXT: smulh z0.s, z0.s, z1.s664; SVE2-NEXT: ret665 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smulh.u.nxv4i32(<vscale x 4 x i1> %pg,666 <vscale x 4 x i32> %a,667 <vscale x 4 x i32> %b)668 ret <vscale x 4 x i32> %out669}670 671define <vscale x 2 x i64> @smulh_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {672; SVE1-LABEL: smulh_i64:673; SVE1: // %bb.0:674; SVE1-NEXT: smulh z0.d, p0/m, z0.d, z1.d675; SVE1-NEXT: ret676;677; SVE2-LABEL: smulh_i64:678; SVE2: // %bb.0:679; SVE2-NEXT: smulh z0.d, z0.d, z1.d680; SVE2-NEXT: ret681 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smulh.u.nxv2i64(<vscale x 2 x i1> %pg,682 <vscale x 2 x i64> %a,683 <vscale x 2 x i64> %b)684 ret <vscale x 2 x i64> %out685}686 687;688; SUB689;690 691define <vscale x 16 x i8> @sub_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {692; CHECK-LABEL: sub_i8:693; CHECK: // %bb.0:694; CHECK-NEXT: sub z0.b, z0.b, z1.b695; CHECK-NEXT: ret696 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.u.nxv16i8(<vscale x 16 x i1> %pg,697 <vscale x 16 x i8> %a,698 <vscale x 16 x i8> %b)699 ret <vscale x 16 x i8> %out700}701 702define <vscale x 8 x i16> @sub_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {703; CHECK-LABEL: sub_i16:704; CHECK: // %bb.0:705; CHECK-NEXT: sub z0.h, z0.h, z1.h706; CHECK-NEXT: ret707 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.u.nxv8i16(<vscale x 8 x i1> %pg,708 <vscale x 8 x i16> %a,709 <vscale x 8 x i16> %b)710 ret <vscale x 8 x i16> %out711}712 713define <vscale x 4 x i32> @sub_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {714; CHECK-LABEL: sub_i32:715; CHECK: // %bb.0:716; CHECK-NEXT: sub z0.s, z0.s, z1.s717; CHECK-NEXT: ret718 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> %pg,719 <vscale x 4 x i32> %a,720 <vscale x 4 x i32> %b)721 ret <vscale x 4 x i32> %out722}723 724define <vscale x 2 x i64> @sub_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {725; CHECK-LABEL: sub_i64:726; CHECK: // %bb.0:727; CHECK-NEXT: sub z0.d, z0.d, z1.d728; CHECK-NEXT: ret729 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.u.nxv2i64(<vscale x 2 x i1> %pg,730 <vscale x 2 x i64> %a,731 <vscale x 2 x i64> %b)732 ret <vscale x 2 x i64> %out733}734 735;736; SUB (immediate)737;738 739define <vscale x 16 x i8> @sub_imm_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {740; CHECK-LABEL: sub_imm_i8:741; CHECK: // %bb.0:742; CHECK-NEXT: sub z0.b, z0.b, #3 // =0x3743; CHECK-NEXT: ret744 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.u.nxv16i8(<vscale x 16 x i1> %pg,745 <vscale x 16 x i8> %a,746 <vscale x 16 x i8> splat(i8 3))747 ret <vscale x 16 x i8> %out748}749 750define <vscale x 8 x i16> @sub_imm_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {751; CHECK-LABEL: sub_imm_i16:752; CHECK: // %bb.0:753; CHECK-NEXT: sub z0.h, z0.h, #4 // =0x4754; CHECK-NEXT: ret755 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.u.nxv8i16(<vscale x 8 x i1> %pg,756 <vscale x 8 x i16> %a,757 <vscale x 8 x i16> splat(i16 4))758 ret <vscale x 8 x i16> %out759}760 761define <vscale x 4 x i32> @sub_imm_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {762; CHECK-LABEL: sub_imm_i32:763; CHECK: // %bb.0:764; CHECK-NEXT: sub z0.s, z0.s, #5 // =0x5765; CHECK-NEXT: ret766 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> %pg,767 <vscale x 4 x i32> %a,768 <vscale x 4 x i32> splat(i32 5))769 ret <vscale x 4 x i32> %out770}771 772define <vscale x 2 x i64> @sub_imm_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {773; CHECK-LABEL: sub_imm_i64:774; CHECK: // %bb.0:775; CHECK-NEXT: sub z0.d, z0.d, #6 // =0x6776; CHECK-NEXT: ret777 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.u.nxv2i64(<vscale x 2 x i1> %pg,778 <vscale x 2 x i64> %a,779 <vscale x 2 x i64> splat(i64 6))780 ret <vscale x 2 x i64> %out781}782 783;784; SUBR785;786 787define <vscale x 16 x i8> @subr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {788; CHECK-LABEL: subr_i8:789; CHECK: // %bb.0:790; CHECK-NEXT: sub z0.b, z1.b, z0.b791; CHECK-NEXT: ret792 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.u.nxv16i8(<vscale x 16 x i1> %pg,793 <vscale x 16 x i8> %b,794 <vscale x 16 x i8> %a)795 ret <vscale x 16 x i8> %out796}797 798define <vscale x 8 x i16> @subr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {799; CHECK-LABEL: subr_i16:800; CHECK: // %bb.0:801; CHECK-NEXT: sub z0.h, z1.h, z0.h802; CHECK-NEXT: ret803 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.u.nxv8i16(<vscale x 8 x i1> %pg,804 <vscale x 8 x i16> %b,805 <vscale x 8 x i16> %a)806 ret <vscale x 8 x i16> %out807}808 809define <vscale x 4 x i32> @subr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {810; CHECK-LABEL: subr_i32:811; CHECK: // %bb.0:812; CHECK-NEXT: sub z0.s, z1.s, z0.s813; CHECK-NEXT: ret814 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> %pg,815 <vscale x 4 x i32> %b,816 <vscale x 4 x i32> %a)817 ret <vscale x 4 x i32> %out818}819 820define <vscale x 2 x i64> @subr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {821; CHECK-LABEL: subr_i64:822; CHECK: // %bb.0:823; CHECK-NEXT: sub z0.d, z1.d, z0.d824; CHECK-NEXT: ret825 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.u.nxv2i64(<vscale x 2 x i1> %pg,826 <vscale x 2 x i64> %b,827 <vscale x 2 x i64> %a)828 ret <vscale x 2 x i64> %out829}830 831;832; SUBR (immediate)833;834 835define <vscale x 16 x i8> @subr_imm_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {836; CHECK-LABEL: subr_imm_i8:837; CHECK: // %bb.0:838; CHECK-NEXT: subr z0.b, z0.b, #3 // =0x3839; CHECK-NEXT: ret840 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.u.nxv16i8(<vscale x 16 x i1> %pg,841 <vscale x 16 x i8> splat(i8 3),842 <vscale x 16 x i8> %a)843 ret <vscale x 16 x i8> %out844}845 846define <vscale x 8 x i16> @subr_imm_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {847; CHECK-LABEL: subr_imm_i16:848; CHECK: // %bb.0:849; CHECK-NEXT: subr z0.h, z0.h, #4 // =0x4850; CHECK-NEXT: ret851 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.u.nxv8i16(<vscale x 8 x i1> %pg,852 <vscale x 8 x i16> splat(i16 4),853 <vscale x 8 x i16> %a)854 ret <vscale x 8 x i16> %out855}856 857define <vscale x 4 x i32> @subr_imm_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {858; CHECK-LABEL: subr_imm_i32:859; CHECK: // %bb.0:860; CHECK-NEXT: subr z0.s, z0.s, #5 // =0x5861; CHECK-NEXT: ret862 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> %pg,863 <vscale x 4 x i32> splat(i32 5),864 <vscale x 4 x i32> %a)865 ret <vscale x 4 x i32> %out866}867 868define <vscale x 2 x i64> @subr_imm_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {869; CHECK-LABEL: subr_imm_i64:870; CHECK: // %bb.0:871; CHECK-NEXT: subr z0.d, z0.d, #6 // =0x6872; CHECK-NEXT: ret873 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.u.nxv2i64(<vscale x 2 x i1> %pg,874 <vscale x 2 x i64> splat(i64 6),875 <vscale x 2 x i64> %a)876 ret <vscale x 2 x i64> %out877}878 879;880; UABD881;882 883define <vscale x 16 x i8> @uabd_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {884; CHECK-LABEL: uabd_i8:885; CHECK: // %bb.0:886; CHECK-NEXT: ptrue p0.b887; CHECK-NEXT: uabd z0.b, p0/m, z0.b, z1.b888; CHECK-NEXT: ret889 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uabd.u.nxv16i8(<vscale x 16 x i1> %pg,890 <vscale x 16 x i8> %a,891 <vscale x 16 x i8> %b)892 ret <vscale x 16 x i8> %out893}894 895define <vscale x 8 x i16> @uabd_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {896; CHECK-LABEL: uabd_i16:897; CHECK: // %bb.0:898; CHECK-NEXT: ptrue p0.h899; CHECK-NEXT: uabd z0.h, p0/m, z0.h, z1.h900; CHECK-NEXT: ret901 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uabd.u.nxv8i16(<vscale x 8 x i1> %pg,902 <vscale x 8 x i16> %a,903 <vscale x 8 x i16> %b)904 ret <vscale x 8 x i16> %out905}906 907define <vscale x 4 x i32> @uabd_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {908; CHECK-LABEL: uabd_i32:909; CHECK: // %bb.0:910; CHECK-NEXT: ptrue p0.s911; CHECK-NEXT: uabd z0.s, p0/m, z0.s, z1.s912; CHECK-NEXT: ret913 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uabd.u.nxv4i32(<vscale x 4 x i1> %pg,914 <vscale x 4 x i32> %a,915 <vscale x 4 x i32> %b)916 ret <vscale x 4 x i32> %out917}918 919define <vscale x 2 x i64> @uabd_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {920; CHECK-LABEL: uabd_i64:921; CHECK: // %bb.0:922; CHECK-NEXT: ptrue p0.d923; CHECK-NEXT: uabd z0.d, p0/m, z0.d, z1.d924; CHECK-NEXT: ret925 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uabd.u.nxv2i64(<vscale x 2 x i1> %pg,926 <vscale x 2 x i64> %a,927 <vscale x 2 x i64> %b)928 ret <vscale x 2 x i64> %out929}930 931;932; UDIV933;934 935define <vscale x 4 x i32> @udiv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {936; CHECK-LABEL: udiv_i32:937; CHECK: // %bb.0:938; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s939; CHECK-NEXT: ret940 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.u.nxv4i32(<vscale x 4 x i1> %pg,941 <vscale x 4 x i32> %a,942 <vscale x 4 x i32> %b)943 ret <vscale x 4 x i32> %out944}945 946define <vscale x 2 x i64> @udiv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {947; CHECK-LABEL: udiv_i64:948; CHECK: // %bb.0:949; CHECK-NEXT: udiv z0.d, p0/m, z0.d, z1.d950; CHECK-NEXT: ret951 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.udiv.u.nxv2i64(<vscale x 2 x i1> %pg,952 <vscale x 2 x i64> %a,953 <vscale x 2 x i64> %b)954 ret <vscale x 2 x i64> %out955}956 957;958; UDIVR959;960 961define <vscale x 4 x i32> @udivr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {962; CHECK-LABEL: udivr_i32:963; CHECK: // %bb.0:964; CHECK-NEXT: udivr z0.s, p0/m, z0.s, z1.s965; CHECK-NEXT: ret966 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.u.nxv4i32(<vscale x 4 x i1> %pg,967 <vscale x 4 x i32> %b,968 <vscale x 4 x i32> %a)969 ret <vscale x 4 x i32> %out970}971 972define <vscale x 2 x i64> @udivr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {973; CHECK-LABEL: udivr_i64:974; CHECK: // %bb.0:975; CHECK-NEXT: udivr z0.d, p0/m, z0.d, z1.d976; CHECK-NEXT: ret977 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.udiv.u.nxv2i64(<vscale x 2 x i1> %pg,978 <vscale x 2 x i64> %b,979 <vscale x 2 x i64> %a)980 ret <vscale x 2 x i64> %out981}982 983;984; UMAX985;986 987define <vscale x 16 x i8> @umax_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {988; CHECK-LABEL: umax_i8:989; CHECK: // %bb.0:990; CHECK-NEXT: umax z0.b, p0/m, z0.b, z1.b991; CHECK-NEXT: ret992 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.umax.u.nxv16i8(<vscale x 16 x i1> %pg,993 <vscale x 16 x i8> %a,994 <vscale x 16 x i8> %b)995 ret <vscale x 16 x i8> %out996}997 998define <vscale x 8 x i16> @umax_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {999; CHECK-LABEL: umax_i16:1000; CHECK: // %bb.0:1001; CHECK-NEXT: umax z0.h, p0/m, z0.h, z1.h1002; CHECK-NEXT: ret1003 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.umax.u.nxv8i16(<vscale x 8 x i1> %pg,1004 <vscale x 8 x i16> %a,1005 <vscale x 8 x i16> %b)1006 ret <vscale x 8 x i16> %out1007}1008 1009define <vscale x 4 x i32> @umax_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {1010; CHECK-LABEL: umax_i32:1011; CHECK: // %bb.0:1012; CHECK-NEXT: umax z0.s, p0/m, z0.s, z1.s1013; CHECK-NEXT: ret1014 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.umax.u.nxv4i32(<vscale x 4 x i1> %pg,1015 <vscale x 4 x i32> %a,1016 <vscale x 4 x i32> %b)1017 ret <vscale x 4 x i32> %out1018}1019 1020define <vscale x 2 x i64> @umax_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {1021; CHECK-LABEL: umax_i64:1022; CHECK: // %bb.0:1023; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d1024; CHECK-NEXT: ret1025 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.umax.u.nxv2i64(<vscale x 2 x i1> %pg,1026 <vscale x 2 x i64> %a,1027 <vscale x 2 x i64> %b)1028 ret <vscale x 2 x i64> %out1029}1030 1031;1032; UMAX (immediate)1033;1034 1035define <vscale x 16 x i8> @umax_imm_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {1036; CHECK-LABEL: umax_imm_i8:1037; CHECK: // %bb.0:1038; CHECK-NEXT: umax z0.b, z0.b, #31039; CHECK-NEXT: ret1040 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.umax.u.nxv16i8(<vscale x 16 x i1> %pg,1041 <vscale x 16 x i8> %a,1042 <vscale x 16 x i8> splat(i8 3))1043 ret <vscale x 16 x i8> %out1044}1045 1046define <vscale x 8 x i16> @umax_imm_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {1047; CHECK-LABEL: umax_imm_i16:1048; CHECK: // %bb.0:1049; CHECK-NEXT: umax z0.h, z0.h, #41050; CHECK-NEXT: ret1051 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.umax.u.nxv8i16(<vscale x 8 x i1> %pg,1052 <vscale x 8 x i16> %a,1053 <vscale x 8 x i16> splat(i16 4))1054 ret <vscale x 8 x i16> %out1055}1056 1057define <vscale x 4 x i32> @umax_imm_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {1058; CHECK-LABEL: umax_imm_i32:1059; CHECK: // %bb.0:1060; CHECK-NEXT: umax z0.s, z0.s, #51061; CHECK-NEXT: ret1062 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.umax.u.nxv4i32(<vscale x 4 x i1> %pg,1063 <vscale x 4 x i32> %a,1064 <vscale x 4 x i32> splat(i32 5))1065 ret <vscale x 4 x i32> %out1066}1067 1068define <vscale x 2 x i64> @umax_imm_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {1069; CHECK-LABEL: umax_imm_i64:1070; CHECK: // %bb.0:1071; CHECK-NEXT: umax z0.d, z0.d, #61072; CHECK-NEXT: ret1073 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.umax.u.nxv2i64(<vscale x 2 x i1> %pg,1074 <vscale x 2 x i64> %a,1075 <vscale x 2 x i64> splat(i64 6))1076 ret <vscale x 2 x i64> %out1077}1078 1079;1080; UMIN1081;1082 1083define <vscale x 16 x i8> @umin_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {1084; CHECK-LABEL: umin_i8:1085; CHECK: // %bb.0:1086; CHECK-NEXT: umin z0.b, p0/m, z0.b, z1.b1087; CHECK-NEXT: ret1088 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.umin.u.nxv16i8(<vscale x 16 x i1> %pg,1089 <vscale x 16 x i8> %a,1090 <vscale x 16 x i8> %b)1091 ret <vscale x 16 x i8> %out1092}1093 1094define <vscale x 8 x i16> @umin_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {1095; CHECK-LABEL: umin_i16:1096; CHECK: // %bb.0:1097; CHECK-NEXT: umin z0.h, p0/m, z0.h, z1.h1098; CHECK-NEXT: ret1099 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.umin.u.nxv8i16(<vscale x 8 x i1> %pg,1100 <vscale x 8 x i16> %a,1101 <vscale x 8 x i16> %b)1102 ret <vscale x 8 x i16> %out1103}1104 1105define <vscale x 4 x i32> @umin_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {1106; CHECK-LABEL: umin_i32:1107; CHECK: // %bb.0:1108; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s1109; CHECK-NEXT: ret1110 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.umin.u.nxv4i32(<vscale x 4 x i1> %pg,1111 <vscale x 4 x i32> %a,1112 <vscale x 4 x i32> %b)1113 ret <vscale x 4 x i32> %out1114}1115 1116define <vscale x 2 x i64> @umin_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {1117; CHECK-LABEL: umin_i64:1118; CHECK: // %bb.0:1119; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d1120; CHECK-NEXT: ret1121 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.umin.u.nxv2i64(<vscale x 2 x i1> %pg,1122 <vscale x 2 x i64> %a,1123 <vscale x 2 x i64> %b)1124 ret <vscale x 2 x i64> %out1125}1126 1127;1128; UMIN (immediate)1129;1130 1131define <vscale x 16 x i8> @umin_imm_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {1132; CHECK-LABEL: umin_imm_i8:1133; CHECK: // %bb.0:1134; CHECK-NEXT: umin z0.b, z0.b, #31135; CHECK-NEXT: ret1136 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.umin.u.nxv16i8(<vscale x 16 x i1> %pg,1137 <vscale x 16 x i8> %a,1138 <vscale x 16 x i8> splat(i8 3))1139 ret <vscale x 16 x i8> %out1140}1141 1142define <vscale x 8 x i16> @umin_imm_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {1143; CHECK-LABEL: umin_imm_i16:1144; CHECK: // %bb.0:1145; CHECK-NEXT: umin z0.h, z0.h, #41146; CHECK-NEXT: ret1147 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.umin.u.nxv8i16(<vscale x 8 x i1> %pg,1148 <vscale x 8 x i16> %a,1149 <vscale x 8 x i16> splat(i16 4))1150 ret <vscale x 8 x i16> %out1151}1152 1153define <vscale x 4 x i32> @umin_imm_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {1154; CHECK-LABEL: umin_imm_i32:1155; CHECK: // %bb.0:1156; CHECK-NEXT: umin z0.s, z0.s, #51157; CHECK-NEXT: ret1158 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.umin.u.nxv4i32(<vscale x 4 x i1> %pg,1159 <vscale x 4 x i32> %a,1160 <vscale x 4 x i32> splat(i32 5))1161 ret <vscale x 4 x i32> %out1162}1163 1164define <vscale x 2 x i64> @umin_imm_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {1165; CHECK-LABEL: umin_imm_i64:1166; CHECK: // %bb.0:1167; CHECK-NEXT: umin z0.d, z0.d, #61168; CHECK-NEXT: ret1169 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.umin.u.nxv2i64(<vscale x 2 x i1> %pg,1170 <vscale x 2 x i64> %a,1171 <vscale x 2 x i64> splat(i64 6))1172 ret <vscale x 2 x i64> %out1173}1174 1175;1176; UMULH1177;1178 1179define <vscale x 16 x i8> @umulh_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {1180; SVE1-LABEL: umulh_i8:1181; SVE1: // %bb.0:1182; SVE1-NEXT: umulh z0.b, p0/m, z0.b, z1.b1183; SVE1-NEXT: ret1184;1185; SVE2-LABEL: umulh_i8:1186; SVE2: // %bb.0:1187; SVE2-NEXT: umulh z0.b, z0.b, z1.b1188; SVE2-NEXT: ret1189 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.umulh.u.nxv16i8(<vscale x 16 x i1> %pg,1190 <vscale x 16 x i8> %a,1191 <vscale x 16 x i8> %b)1192 ret <vscale x 16 x i8> %out1193}1194 1195define <vscale x 8 x i16> @umulh_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {1196; SVE1-LABEL: umulh_i16:1197; SVE1: // %bb.0:1198; SVE1-NEXT: umulh z0.h, p0/m, z0.h, z1.h1199; SVE1-NEXT: ret1200;1201; SVE2-LABEL: umulh_i16:1202; SVE2: // %bb.0:1203; SVE2-NEXT: umulh z0.h, z0.h, z1.h1204; SVE2-NEXT: ret1205 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.umulh.u.nxv8i16(<vscale x 8 x i1> %pg,1206 <vscale x 8 x i16> %a,1207 <vscale x 8 x i16> %b)1208 ret <vscale x 8 x i16> %out1209}1210 1211define <vscale x 4 x i32> @umulh_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {1212; SVE1-LABEL: umulh_i32:1213; SVE1: // %bb.0:1214; SVE1-NEXT: umulh z0.s, p0/m, z0.s, z1.s1215; SVE1-NEXT: ret1216;1217; SVE2-LABEL: umulh_i32:1218; SVE2: // %bb.0:1219; SVE2-NEXT: umulh z0.s, z0.s, z1.s1220; SVE2-NEXT: ret1221 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.umulh.u.nxv4i32(<vscale x 4 x i1> %pg,1222 <vscale x 4 x i32> %a,1223 <vscale x 4 x i32> %b)1224 ret <vscale x 4 x i32> %out1225}1226 1227define <vscale x 2 x i64> @umulh_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {1228; SVE1-LABEL: umulh_i64:1229; SVE1: // %bb.0:1230; SVE1-NEXT: umulh z0.d, p0/m, z0.d, z1.d1231; SVE1-NEXT: ret1232;1233; SVE2-LABEL: umulh_i64:1234; SVE2: // %bb.0:1235; SVE2-NEXT: umulh z0.d, z0.d, z1.d1236; SVE2-NEXT: ret1237 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.umulh.u.nxv2i64(<vscale x 2 x i1> %pg,1238 <vscale x 2 x i64> %a,1239 <vscale x 2 x i64> %b)1240 ret <vscale x 2 x i64> %out1241}1242 1243 1244declare <vscale x 16 x i8> @llvm.aarch64.sve.add.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1245declare <vscale x 8 x i16> @llvm.aarch64.sve.add.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1246declare <vscale x 4 x i32> @llvm.aarch64.sve.add.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1247declare <vscale x 2 x i64> @llvm.aarch64.sve.add.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1248 1249declare <vscale x 16 x i8> @llvm.aarch64.sve.mla.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)1250declare <vscale x 8 x i16> @llvm.aarch64.sve.mla.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)1251declare <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)1252declare <vscale x 2 x i64> @llvm.aarch64.sve.mla.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)1253 1254declare <vscale x 16 x i8> @llvm.aarch64.sve.mls.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)1255declare <vscale x 8 x i16> @llvm.aarch64.sve.mls.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)1256declare <vscale x 4 x i32> @llvm.aarch64.sve.mls.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)1257declare <vscale x 2 x i64> @llvm.aarch64.sve.mls.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)1258 1259declare <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1260declare <vscale x 8 x i16> @llvm.aarch64.sve.mul.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1261declare <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1262declare <vscale x 2 x i64> @llvm.aarch64.sve.mul.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1263 1264declare <vscale x 16 x i8> @llvm.aarch64.sve.sabd.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1265declare <vscale x 8 x i16> @llvm.aarch64.sve.sabd.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1266declare <vscale x 4 x i32> @llvm.aarch64.sve.sabd.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1267declare <vscale x 2 x i64> @llvm.aarch64.sve.sabd.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1268 1269declare <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1270declare <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1271 1272declare <vscale x 16 x i8> @llvm.aarch64.sve.smax.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1273declare <vscale x 8 x i16> @llvm.aarch64.sve.smax.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1274declare <vscale x 4 x i32> @llvm.aarch64.sve.smax.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1275declare <vscale x 2 x i64> @llvm.aarch64.sve.smax.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1276 1277declare <vscale x 16 x i8> @llvm.aarch64.sve.smin.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1278declare <vscale x 8 x i16> @llvm.aarch64.sve.smin.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1279declare <vscale x 4 x i32> @llvm.aarch64.sve.smin.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1280declare <vscale x 2 x i64> @llvm.aarch64.sve.smin.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1281 1282declare <vscale x 16 x i8> @llvm.aarch64.sve.smulh.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1283declare <vscale x 8 x i16> @llvm.aarch64.sve.smulh.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1284declare <vscale x 4 x i32> @llvm.aarch64.sve.smulh.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1285declare <vscale x 2 x i64> @llvm.aarch64.sve.smulh.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1286 1287declare <vscale x 16 x i8> @llvm.aarch64.sve.sub.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1288declare <vscale x 8 x i16> @llvm.aarch64.sve.sub.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1289declare <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1290declare <vscale x 2 x i64> @llvm.aarch64.sve.sub.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1291 1292declare <vscale x 16 x i8> @llvm.aarch64.sve.uabd.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1293declare <vscale x 8 x i16> @llvm.aarch64.sve.uabd.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1294declare <vscale x 4 x i32> @llvm.aarch64.sve.uabd.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1295declare <vscale x 2 x i64> @llvm.aarch64.sve.uabd.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1296 1297declare <vscale x 4 x i32> @llvm.aarch64.sve.udiv.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1298declare <vscale x 2 x i64> @llvm.aarch64.sve.udiv.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1299 1300declare <vscale x 16 x i8> @llvm.aarch64.sve.umax.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1301declare <vscale x 8 x i16> @llvm.aarch64.sve.umax.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1302declare <vscale x 4 x i32> @llvm.aarch64.sve.umax.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1303declare <vscale x 2 x i64> @llvm.aarch64.sve.umax.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1304 1305declare <vscale x 16 x i8> @llvm.aarch64.sve.umin.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1306declare <vscale x 8 x i16> @llvm.aarch64.sve.umin.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1307declare <vscale x 4 x i32> @llvm.aarch64.sve.umin.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1308declare <vscale x 2 x i64> @llvm.aarch64.sve.umin.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1309 1310declare <vscale x 16 x i8> @llvm.aarch64.sve.umulh.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1311declare <vscale x 8 x i16> @llvm.aarch64.sve.umulh.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1312declare <vscale x 4 x i32> @llvm.aarch64.sve.umulh.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1313declare <vscale x 2 x i64> @llvm.aarch64.sve.umulh.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1314