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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4;5; ABS6;7 8define <vscale x 16 x i8> @abs_i8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %b) {9; CHECK-LABEL: abs_i8:10; CHECK: // %bb.0:11; CHECK-NEXT: abs z0.b, p0/m, z1.b12; CHECK-NEXT: ret13 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> %a,14 <vscale x 16 x i1> %pg,15 <vscale x 16 x i8> %b)16 ret <vscale x 16 x i8> %out17}18 19define <vscale x 8 x i16> @abs_i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %b) {20; CHECK-LABEL: abs_i16:21; CHECK: // %bb.0:22; CHECK-NEXT: abs z0.h, p0/m, z1.h23; CHECK-NEXT: ret24 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> %a,25 <vscale x 8 x i1> %pg,26 <vscale x 8 x i16> %b)27 ret <vscale x 8 x i16> %out28}29 30define <vscale x 4 x i32> @abs_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b) {31; CHECK-LABEL: abs_i32:32; CHECK: // %bb.0:33; CHECK-NEXT: abs z0.s, p0/m, z1.s34; CHECK-NEXT: ret35 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> %a,36 <vscale x 4 x i1> %pg,37 <vscale x 4 x i32> %b)38 ret <vscale x 4 x i32> %out39}40 41define <vscale x 2 x i64> @abs_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b) {42; CHECK-LABEL: abs_i64:43; CHECK: // %bb.0:44; CHECK-NEXT: abs z0.d, p0/m, z1.d45; CHECK-NEXT: ret46 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64> %a,47 <vscale x 2 x i1> %pg,48 <vscale x 2 x i64> %b)49 ret <vscale x 2 x i64> %out50}51 52;53; NEG54;55 56define <vscale x 16 x i8> @neg_i8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %b) {57; CHECK-LABEL: neg_i8:58; CHECK: // %bb.0:59; CHECK-NEXT: neg z0.b, p0/m, z1.b60; CHECK-NEXT: ret61 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8> %a,62 <vscale x 16 x i1> %pg,63 <vscale x 16 x i8> %b)64 ret <vscale x 16 x i8> %out65}66 67define <vscale x 8 x i16> @neg_i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %b) {68; CHECK-LABEL: neg_i16:69; CHECK: // %bb.0:70; CHECK-NEXT: neg z0.h, p0/m, z1.h71; CHECK-NEXT: ret72 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16> %a,73 <vscale x 8 x i1> %pg,74 <vscale x 8 x i16> %b)75 ret <vscale x 8 x i16> %out76}77 78define <vscale x 4 x i32> @neg_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b) {79; CHECK-LABEL: neg_i32:80; CHECK: // %bb.0:81; CHECK-NEXT: neg z0.s, p0/m, z1.s82; CHECK-NEXT: ret83 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32> %a,84 <vscale x 4 x i1> %pg,85 <vscale x 4 x i32> %b)86 ret <vscale x 4 x i32> %out87}88 89define <vscale x 2 x i64> @neg_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b) {90; CHECK-LABEL: neg_i64:91; CHECK: // %bb.0:92; CHECK-NEXT: neg z0.d, p0/m, z1.d93; CHECK-NEXT: ret94 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.neg.nxv2i64(<vscale x 2 x i64> %a,95 <vscale x 2 x i1> %pg,96 <vscale x 2 x i64> %b)97 ret <vscale x 2 x i64> %out98}99 100; SDOT101 102define <vscale x 4 x i32> @sdot_i32(<vscale x 4 x i32> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {103; CHECK-LABEL: sdot_i32:104; CHECK: // %bb.0:105; CHECK-NEXT: sdot z0.s, z1.b, z2.b106; CHECK-NEXT: ret107 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32> %a,108 <vscale x 16 x i8> %b,109 <vscale x 16 x i8> %c)110 ret <vscale x 4 x i32> %out111}112 113define <vscale x 2 x i64> @sdot_i64(<vscale x 2 x i64> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {114; CHECK-LABEL: sdot_i64:115; CHECK: // %bb.0:116; CHECK-NEXT: sdot z0.d, z1.h, z2.h117; CHECK-NEXT: ret118 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64> %a,119 <vscale x 8 x i16> %b,120 <vscale x 8 x i16> %c)121 ret <vscale x 2 x i64> %out122}123 124define <vscale x 2 x i64> @test_sdot_i64_zero(<vscale x 2 x i64> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {125; CHECK-LABEL: test_sdot_i64_zero:126; CHECK: // %bb.0: // %entry127; CHECK-NEXT: sdot z0.d, z1.h, z2.h128; CHECK-NEXT: ret129entry:130 %vdot1.i = call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c)131 %ret = add <vscale x 2 x i64> %vdot1.i, %a132 ret <vscale x 2 x i64> %ret133}134 135define <vscale x 4 x i32> @test_sdot_i32_zero(<vscale x 4 x i32> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {136; CHECK-LABEL: test_sdot_i32_zero:137; CHECK: // %bb.0: // %entry138; CHECK-NEXT: sdot z0.s, z1.b, z2.b139; CHECK-NEXT: ret140entry:141 %vdot1.i = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)142 %ret = add <vscale x 4 x i32> %vdot1.i, %a143 ret <vscale x 4 x i32> %ret144}145 146; SDOT (Indexed)147 148define <vscale x 4 x i32> @sdot_lane_i32(<vscale x 4 x i32> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {149; CHECK-LABEL: sdot_lane_i32:150; CHECK: // %bb.0:151; CHECK-NEXT: sdot z0.s, z1.b, z2.b[2]152; CHECK-NEXT: ret153 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.nxv4i32(<vscale x 4 x i32> %a,154 <vscale x 16 x i8> %b,155 <vscale x 16 x i8> %c,156 i32 2)157 ret <vscale x 4 x i32> %out158}159 160define <vscale x 2 x i64> @sdot_lane_i64(<vscale x 2 x i64> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {161; CHECK-LABEL: sdot_lane_i64:162; CHECK: // %bb.0:163; CHECK-NEXT: sdot z0.d, z1.h, z2.h[1]164; CHECK-NEXT: ret165 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.lane.nxv2i64(<vscale x 2 x i64> %a,166 <vscale x 8 x i16> %b,167 <vscale x 8 x i16> %c,168 i32 1)169 ret <vscale x 2 x i64> %out170}171 172; SQADD173 174define <vscale x 16 x i8> @sqadd_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {175; CHECK-LABEL: sqadd_i8:176; CHECK: // %bb.0:177; CHECK-NEXT: sqadd z0.b, z0.b, z1.b178; CHECK-NEXT: ret179 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.x.nxv16i8(<vscale x 16 x i8> %a,180 <vscale x 16 x i8> %b)181 ret <vscale x 16 x i8> %out182}183 184define <vscale x 8 x i16> @sqadd_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {185; CHECK-LABEL: sqadd_i16:186; CHECK: // %bb.0:187; CHECK-NEXT: sqadd z0.h, z0.h, z1.h188; CHECK-NEXT: ret189 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16> %a,190 <vscale x 8 x i16> %b)191 ret <vscale x 8 x i16> %out192}193 194define <vscale x 4 x i32> @sqadd_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {195; CHECK-LABEL: sqadd_i32:196; CHECK: // %bb.0:197; CHECK-NEXT: sqadd z0.s, z0.s, z1.s198; CHECK-NEXT: ret199 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32> %a,200 <vscale x 4 x i32> %b)201 ret <vscale x 4 x i32> %out202}203 204define <vscale x 2 x i64> @sqadd_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {205; CHECK-LABEL: sqadd_i64:206; CHECK: // %bb.0:207; CHECK-NEXT: sqadd z0.d, z0.d, z1.d208; CHECK-NEXT: ret209 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.x.nxv2i64(<vscale x 2 x i64> %a,210 <vscale x 2 x i64> %b)211 ret <vscale x 2 x i64> %out212}213 214; SQSUB215 216define <vscale x 16 x i8> @sqsub_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {217; CHECK-LABEL: sqsub_i8:218; CHECK: // %bb.0:219; CHECK-NEXT: sqsub z0.b, z0.b, z1.b220; CHECK-NEXT: ret221 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.x.nxv16i8(<vscale x 16 x i8> %a,222 <vscale x 16 x i8> %b)223 ret <vscale x 16 x i8> %out224}225 226define <vscale x 8 x i16> @sqsub_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {227; CHECK-LABEL: sqsub_i16:228; CHECK: // %bb.0:229; CHECK-NEXT: sqsub z0.h, z0.h, z1.h230; CHECK-NEXT: ret231 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.x.nxv8i16(<vscale x 8 x i16> %a,232 <vscale x 8 x i16> %b)233 ret <vscale x 8 x i16> %out234}235 236define <vscale x 4 x i32> @sqsub_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {237; CHECK-LABEL: sqsub_i32:238; CHECK: // %bb.0:239; CHECK-NEXT: sqsub z0.s, z0.s, z1.s240; CHECK-NEXT: ret241 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.x.nxv4i32(<vscale x 4 x i32> %a,242 <vscale x 4 x i32> %b)243 ret <vscale x 4 x i32> %out244}245 246define <vscale x 2 x i64> @sqsub_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {247; CHECK-LABEL: sqsub_i64:248; CHECK: // %bb.0:249; CHECK-NEXT: sqsub z0.d, z0.d, z1.d250; CHECK-NEXT: ret251 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.x.nxv2i64(<vscale x 2 x i64> %a,252 <vscale x 2 x i64> %b)253 ret <vscale x 2 x i64> %out254}255 256; UDOT257 258define <vscale x 4 x i32> @udot_i32(<vscale x 4 x i32> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {259; CHECK-LABEL: udot_i32:260; CHECK: // %bb.0:261; CHECK-NEXT: udot z0.s, z1.b, z2.b262; CHECK-NEXT: ret263 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.nxv4i32(<vscale x 4 x i32> %a,264 <vscale x 16 x i8> %b,265 <vscale x 16 x i8> %c)266 ret <vscale x 4 x i32> %out267}268 269define <vscale x 2 x i64> @udot_i64(<vscale x 2 x i64> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {270; CHECK-LABEL: udot_i64:271; CHECK: // %bb.0:272; CHECK-NEXT: udot z0.d, z1.h, z2.h273; CHECK-NEXT: ret274 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.udot.nxv2i64(<vscale x 2 x i64> %a,275 <vscale x 8 x i16> %b,276 <vscale x 8 x i16> %c)277 ret <vscale x 2 x i64> %out278}279 280define <vscale x 2 x i64> @test_udot_i64_zero(<vscale x 2 x i64> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {281; CHECK-LABEL: test_udot_i64_zero:282; CHECK: // %bb.0: // %entry283; CHECK-NEXT: udot z0.d, z1.h, z2.h284; CHECK-NEXT: ret285entry:286 %vdot1.i = call <vscale x 2 x i64> @llvm.aarch64.sve.udot.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c)287 %ret = add <vscale x 2 x i64> %vdot1.i, %a288 ret <vscale x 2 x i64> %ret289}290 291define <vscale x 4 x i32> @test_udot_i32_zero(<vscale x 4 x i32> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {292; CHECK-LABEL: test_udot_i32_zero:293; CHECK: // %bb.0: // %entry294; CHECK-NEXT: udot z0.s, z1.b, z2.b295; CHECK-NEXT: ret296entry:297 %vdot1.i = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)298 %ret = add <vscale x 4 x i32> %vdot1.i, %a299 ret <vscale x 4 x i32> %ret300}301 302; UDOT (Indexed)303 304define <vscale x 4 x i32> @udot_lane_i32(<vscale x 4 x i32> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {305; CHECK-LABEL: udot_lane_i32:306; CHECK: // %bb.0:307; CHECK-NEXT: udot z0.s, z1.b, z2.b[2]308; CHECK-NEXT: ret309 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.nxv4i32(<vscale x 4 x i32> %a,310 <vscale x 16 x i8> %b,311 <vscale x 16 x i8> %c,312 i32 2)313 ret <vscale x 4 x i32> %out314}315 316; UQADD317 318define <vscale x 16 x i8> @uqadd_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {319; CHECK-LABEL: uqadd_i8:320; CHECK: // %bb.0:321; CHECK-NEXT: uqadd z0.b, z0.b, z1.b322; CHECK-NEXT: ret323 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqadd.x.nxv16i8(<vscale x 16 x i8> %a,324 <vscale x 16 x i8> %b)325 ret <vscale x 16 x i8> %out326}327 328define <vscale x 8 x i16> @uqadd_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {329; CHECK-LABEL: uqadd_i16:330; CHECK: // %bb.0:331; CHECK-NEXT: uqadd z0.h, z0.h, z1.h332; CHECK-NEXT: ret333 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.x.nxv8i16(<vscale x 8 x i16> %a,334 <vscale x 8 x i16> %b)335 ret <vscale x 8 x i16> %out336}337 338define <vscale x 4 x i32> @uqadd_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {339; CHECK-LABEL: uqadd_i32:340; CHECK: // %bb.0:341; CHECK-NEXT: uqadd z0.s, z0.s, z1.s342; CHECK-NEXT: ret343 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.x.nxv4i32(<vscale x 4 x i32> %a,344 <vscale x 4 x i32> %b)345 ret <vscale x 4 x i32> %out346}347 348define <vscale x 2 x i64> @uqadd_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {349; CHECK-LABEL: uqadd_i64:350; CHECK: // %bb.0:351; CHECK-NEXT: uqadd z0.d, z0.d, z1.d352; CHECK-NEXT: ret353 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.x.nxv2i64(<vscale x 2 x i64> %a,354 <vscale x 2 x i64> %b)355 ret <vscale x 2 x i64> %out356}357 358; UQSUB359 360define <vscale x 16 x i8> @uqsub_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {361; CHECK-LABEL: uqsub_i8:362; CHECK: // %bb.0:363; CHECK-NEXT: uqsub z0.b, z0.b, z1.b364; CHECK-NEXT: ret365 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.x.nxv16i8(<vscale x 16 x i8> %a,366 <vscale x 16 x i8> %b)367 ret <vscale x 16 x i8> %out368}369 370define <vscale x 8 x i16> @uqsub_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {371; CHECK-LABEL: uqsub_i16:372; CHECK: // %bb.0:373; CHECK-NEXT: uqsub z0.h, z0.h, z1.h374; CHECK-NEXT: ret375 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.x.nxv8i16(<vscale x 8 x i16> %a,376 <vscale x 8 x i16> %b)377 ret <vscale x 8 x i16> %out378}379 380define <vscale x 4 x i32> @uqsub_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {381; CHECK-LABEL: uqsub_i32:382; CHECK: // %bb.0:383; CHECK-NEXT: uqsub z0.s, z0.s, z1.s384; CHECK-NEXT: ret385 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.x.nxv4i32(<vscale x 4 x i32> %a,386 <vscale x 4 x i32> %b)387 ret <vscale x 4 x i32> %out388}389 390define <vscale x 2 x i64> @uqsub_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {391; CHECK-LABEL: uqsub_i64:392; CHECK: // %bb.0:393; CHECK-NEXT: uqsub z0.d, z0.d, z1.d394; CHECK-NEXT: ret395 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.x.nxv2i64(<vscale x 2 x i64> %a,396 <vscale x 2 x i64> %b)397 ret <vscale x 2 x i64> %out398}399 400declare <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>)401declare <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>)402declare <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)403declare <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)404 405declare <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>)406declare <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>)407declare <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)408declare <vscale x 2 x i64> @llvm.aarch64.sve.neg.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)409 410declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>)411declare <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>)412 413declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32)414declare <vscale x 2 x i64> @llvm.aarch64.sve.sdot.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)415 416declare <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)417declare <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)418declare <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)419declare <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)420 421declare <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)422declare <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)423declare <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)424declare <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)425 426declare <vscale x 4 x i32> @llvm.aarch64.sve.udot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>)427declare <vscale x 2 x i64> @llvm.aarch64.sve.udot.nxv2i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>)428 429declare <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32)430declare <vscale x 2 x i64> @llvm.aarch64.sve.udot.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)431 432declare <vscale x 16 x i8> @llvm.aarch64.sve.uqadd.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)433declare <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)434declare <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)435declare <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)436 437declare <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)438declare <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)439declare <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)440declare <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)441 442