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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64 -mattr=+sve -mattr=+use-experimental-zeroing-pseudos -run-pass=aarch64-expand-pseudo %s -o - | FileCheck %s3 4# Should create an additional LSL to zero the lanes as the DstReg is not unique5 6--- |7 define <vscale x 4 x float> @fsub_s_zero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a){8 %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer9 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1> %pg,10 <vscale x 4 x float> %a_z,11 <vscale x 4 x float> %a_z)12 ret <vscale x 4 x float> %out13 }14 15 declare <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)16...17---18name: fsub_s_zero19alignment: 420tracksRegLiveness: true21tracksDebugUserValues: true22registers: []23liveins:24 - { reg: '$p0', virtual-reg: '' }25 - { reg: '$z0', virtual-reg: '' }26body: |27 bb.0 (%ir-block.0):28 liveins: $p0, $z029 30 ; CHECK-LABEL: name: fsub_s_zero31 ; CHECK: liveins: $p0, $z032 ; CHECK-NEXT: {{ $}}33 ; CHECK-NEXT: BUNDLE implicit-def $z0, implicit $p0, implicit $z0 {34 ; CHECK-NEXT: $z0 = MOVPRFX_ZPzZ_S $p0, $z035 ; CHECK-NEXT: $z0 = LSL_ZPmI_S renamable $p0, internal $z0, 036 ; CHECK-NEXT: $z0 = FSUBR_ZPmZ_S renamable $p0, internal killed $z0, internal killed renamable $z037 ; CHECK-NEXT: }38 ; CHECK-NEXT: RET undef $lr, implicit $z039 renamable $z0 = nnan ninf nsz arcp contract afn reassoc FSUB_ZPZZ_S_ZERO renamable $p0, killed renamable $z0, renamable $z040 RET_ReallyLR implicit $z041...42