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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;5;; Signed Comparisons ;;6;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;7 8;9; CMPEQ10;11 12define <vscale x 16 x i1> @ir_cmpeq_b(<vscale x 16 x i8> %a) {13; CHECK-LABEL: ir_cmpeq_b:14; CHECK: // %bb.0:15; CHECK-NEXT: ptrue p0.b16; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #417; CHECK-NEXT: ret18 %out = icmp eq <vscale x 16 x i8> %a, splat(i8 4)19 ret <vscale x 16 x i1> %out20}21 22define <vscale x 16 x i1> @int_cmpeq_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {23; CHECK-LABEL: int_cmpeq_b:24; CHECK: // %bb.0:25; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #426; CHECK-NEXT: ret27 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %pg,28 <vscale x 16 x i8> %a,29 <vscale x 16 x i8> splat(i8 4))30 ret <vscale x 16 x i1> %out31}32 33define <vscale x 16 x i1> @wide_cmpeq_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {34; CHECK-LABEL: wide_cmpeq_b:35; CHECK: // %bb.0:36; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #437; CHECK-NEXT: ret38 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.wide.nxv16i8(<vscale x 16 x i1> %pg,39 <vscale x 16 x i8> %a,40 <vscale x 2 x i64> splat(i64 4))41 ret <vscale x 16 x i1> %out42}43 44define <vscale x 8 x i1> @ir_cmpeq_h(<vscale x 8 x i16> %a) {45; CHECK-LABEL: ir_cmpeq_h:46; CHECK: // %bb.0:47; CHECK-NEXT: ptrue p0.h48; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #-1649; CHECK-NEXT: ret50 %out = icmp eq <vscale x 8 x i16> %a, splat(i16 -16)51 ret <vscale x 8 x i1> %out52}53 54define <vscale x 8 x i1> @int_cmpeq_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {55; CHECK-LABEL: int_cmpeq_h:56; CHECK: // %bb.0:57; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #-1658; CHECK-NEXT: ret59 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1> %pg,60 <vscale x 8 x i16> %a,61 <vscale x 8 x i16> splat(i16 -16))62 ret <vscale x 8 x i1> %out63}64 65define <vscale x 8 x i1> @wide_cmpeq_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {66; CHECK-LABEL: wide_cmpeq_h:67; CHECK: // %bb.0:68; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, #-1669; CHECK-NEXT: ret70 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.wide.nxv8i16(<vscale x 8 x i1> %pg,71 <vscale x 8 x i16> %a,72 <vscale x 2 x i64> splat(i64 -16))73 ret <vscale x 8 x i1> %out74}75 76define <vscale x 4 x i1> @ir_cmpeq_s(<vscale x 4 x i32> %a) {77; CHECK-LABEL: ir_cmpeq_s:78; CHECK: // %bb.0:79; CHECK-NEXT: ptrue p0.s80; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #1581; CHECK-NEXT: ret82 %out = icmp eq <vscale x 4 x i32> %a, splat(i32 15)83 ret <vscale x 4 x i1> %out84}85 86define <vscale x 4 x i1> @int_cmpeq_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {87; CHECK-LABEL: int_cmpeq_s:88; CHECK: // %bb.0:89; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #1590; CHECK-NEXT: ret91 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.nxv4i32(<vscale x 4 x i1> %pg,92 <vscale x 4 x i32> %a,93 <vscale x 4 x i32> splat(i32 15))94 ret <vscale x 4 x i1> %out95}96 97define <vscale x 4 x i1> @wide_cmpeq_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {98; CHECK-LABEL: wide_cmpeq_s:99; CHECK: // %bb.0:100; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #15101; CHECK-NEXT: ret102 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.wide.nxv4i32(<vscale x 4 x i1> %pg,103 <vscale x 4 x i32> %a,104 <vscale x 2 x i64> splat(i64 15))105 ret <vscale x 4 x i1> %out106}107 108define <vscale x 2 x i1> @ir_cmpeq_d(<vscale x 2 x i64> %a) {109; CHECK-LABEL: ir_cmpeq_d:110; CHECK: // %bb.0:111; CHECK-NEXT: ptrue p0.d112; CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, #0113; CHECK-NEXT: ret114 %out = icmp eq <vscale x 2 x i64> %a, zeroinitializer115 ret <vscale x 2 x i1> %out116}117 118define <vscale x 2 x i1> @int_cmpeq_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {119; CHECK-LABEL: int_cmpeq_d:120; CHECK: // %bb.0:121; CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, #0122; CHECK-NEXT: ret123 %out = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpeq.nxv2i64(<vscale x 2 x i1> %pg,124 <vscale x 2 x i64> %a,125 <vscale x 2 x i64> zeroinitializer)126 ret <vscale x 2 x i1> %out127}128 129;130; CMPGE131;132 133define <vscale x 16 x i1> @ir_cmpge_b(<vscale x 16 x i8> %a) {134; CHECK-LABEL: ir_cmpge_b:135; CHECK: // %bb.0:136; CHECK-NEXT: ptrue p0.b137; CHECK-NEXT: cmpge p0.b, p0/z, z0.b, #4138; CHECK-NEXT: ret139 %out = icmp sge <vscale x 16 x i8> %a, splat(i8 4)140 ret <vscale x 16 x i1> %out141}142 143define <vscale x 16 x i1> @int_cmpge_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {144; CHECK-LABEL: int_cmpge_b:145; CHECK: // %bb.0:146; CHECK-NEXT: cmpge p0.b, p0/z, z0.b, #4147; CHECK-NEXT: ret148 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1> %pg,149 <vscale x 16 x i8> %a,150 <vscale x 16 x i8> splat(i8 4))151 ret <vscale x 16 x i1> %out152}153 154define <vscale x 16 x i1> @wide_cmpge_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {155; CHECK-LABEL: wide_cmpge_b:156; CHECK: // %bb.0:157; CHECK-NEXT: cmpge p0.b, p0/z, z0.b, #4158; CHECK-NEXT: ret159 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.wide.nxv16i8(<vscale x 16 x i1> %pg,160 <vscale x 16 x i8> %a,161 <vscale x 2 x i64> splat(i64 4))162 ret <vscale x 16 x i1> %out163}164 165define <vscale x 8 x i1> @ir_cmpge_h(<vscale x 8 x i16> %a) {166; CHECK-LABEL: ir_cmpge_h:167; CHECK: // %bb.0:168; CHECK-NEXT: ptrue p0.h169; CHECK-NEXT: cmpge p0.h, p0/z, z0.h, #-16170; CHECK-NEXT: ret171 %out = icmp sge <vscale x 8 x i16> %a, splat(i16 -16)172 ret <vscale x 8 x i1> %out173}174 175define <vscale x 8 x i1> @int_cmpge_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {176; CHECK-LABEL: int_cmpge_h:177; CHECK: // %bb.0:178; CHECK-NEXT: cmpge p0.h, p0/z, z0.h, #-16179; CHECK-NEXT: ret180 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1> %pg,181 <vscale x 8 x i16> %a,182 <vscale x 8 x i16> splat(i16 -16))183 ret <vscale x 8 x i1> %out184}185 186define <vscale x 8 x i1> @wide_cmpge_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {187; CHECK-LABEL: wide_cmpge_h:188; CHECK: // %bb.0:189; CHECK-NEXT: cmpge p0.h, p0/z, z0.h, #-16190; CHECK-NEXT: ret191 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.wide.nxv8i16(<vscale x 8 x i1> %pg,192 <vscale x 8 x i16> %a,193 <vscale x 2 x i64> splat(i64 -16))194 ret <vscale x 8 x i1> %out195}196 197define <vscale x 4 x i1> @ir_cmpge_s(<vscale x 4 x i32> %a) {198; CHECK-LABEL: ir_cmpge_s:199; CHECK: // %bb.0:200; CHECK-NEXT: ptrue p0.s201; CHECK-NEXT: cmpge p0.s, p0/z, z0.s, #15202; CHECK-NEXT: ret203 %out = icmp sge <vscale x 4 x i32> %a, splat(i32 15)204 ret <vscale x 4 x i1> %out205}206 207define <vscale x 4 x i1> @int_cmpge_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {208; CHECK-LABEL: int_cmpge_s:209; CHECK: // %bb.0:210; CHECK-NEXT: cmpge p0.s, p0/z, z0.s, #15211; CHECK-NEXT: ret212 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1> %pg,213 <vscale x 4 x i32> %a,214 <vscale x 4 x i32> splat(i32 15))215 ret <vscale x 4 x i1> %out216}217 218define <vscale x 4 x i1> @wide_cmpge_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {219; CHECK-LABEL: wide_cmpge_s:220; CHECK: // %bb.0:221; CHECK-NEXT: cmpge p0.s, p0/z, z0.s, #15222; CHECK-NEXT: ret223 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.wide.nxv4i32(<vscale x 4 x i1> %pg,224 <vscale x 4 x i32> %a,225 <vscale x 2 x i64> splat(i64 15))226 ret <vscale x 4 x i1> %out227}228 229define <vscale x 2 x i1> @ir_cmpge_d(<vscale x 2 x i64> %a) {230; CHECK-LABEL: ir_cmpge_d:231; CHECK: // %bb.0:232; CHECK-NEXT: ptrue p0.d233; CHECK-NEXT: cmpge p0.d, p0/z, z0.d, #0234; CHECK-NEXT: ret235 %out = icmp sge <vscale x 2 x i64> %a, zeroinitializer236 ret <vscale x 2 x i1> %out237}238 239define <vscale x 2 x i1> @int_cmpge_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {240; CHECK-LABEL: int_cmpge_d:241; CHECK: // %bb.0:242; CHECK-NEXT: cmpge p0.d, p0/z, z0.d, #0243; CHECK-NEXT: ret244 %out = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1> %pg,245 <vscale x 2 x i64> %a,246 <vscale x 2 x i64> zeroinitializer)247 ret <vscale x 2 x i1> %out248}249 250;251; CMPGT252;253 254define <vscale x 16 x i1> @ir_cmpgt_b(<vscale x 16 x i8> %a) {255; CHECK-LABEL: ir_cmpgt_b:256; CHECK: // %bb.0:257; CHECK-NEXT: ptrue p0.b258; CHECK-NEXT: cmpgt p0.b, p0/z, z0.b, #4259; CHECK-NEXT: ret260 %out = icmp sgt <vscale x 16 x i8> %a, splat(i8 4)261 ret <vscale x 16 x i1> %out262}263 264define <vscale x 16 x i1> @int_cmpgt_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {265; CHECK-LABEL: int_cmpgt_b:266; CHECK: // %bb.0:267; CHECK-NEXT: cmpgt p0.b, p0/z, z0.b, #4268; CHECK-NEXT: ret269 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1> %pg,270 <vscale x 16 x i8> %a,271 <vscale x 16 x i8> splat(i8 4))272 ret <vscale x 16 x i1> %out273}274 275define <vscale x 16 x i1> @wide_cmpgt_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {276; CHECK-LABEL: wide_cmpgt_b:277; CHECK: // %bb.0:278; CHECK-NEXT: cmpgt p0.b, p0/z, z0.b, #4279; CHECK-NEXT: ret280 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv16i8(<vscale x 16 x i1> %pg,281 <vscale x 16 x i8> %a,282 <vscale x 2 x i64> splat(i64 4))283 ret <vscale x 16 x i1> %out284}285 286define <vscale x 8 x i1> @ir_cmpgt_h(<vscale x 8 x i16> %a) {287; CHECK-LABEL: ir_cmpgt_h:288; CHECK: // %bb.0:289; CHECK-NEXT: ptrue p0.h290; CHECK-NEXT: cmpgt p0.h, p0/z, z0.h, #-16291; CHECK-NEXT: ret292 %out = icmp sgt <vscale x 8 x i16> %a, splat(i16 -16)293 ret <vscale x 8 x i1> %out294}295 296define <vscale x 8 x i1> @int_cmpgt_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {297; CHECK-LABEL: int_cmpgt_h:298; CHECK: // %bb.0:299; CHECK-NEXT: cmpgt p0.h, p0/z, z0.h, #-16300; CHECK-NEXT: ret301 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1> %pg,302 <vscale x 8 x i16> %a,303 <vscale x 8 x i16> splat(i16 -16))304 ret <vscale x 8 x i1> %out305}306 307define <vscale x 8 x i1> @wide_cmpgt_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {308; CHECK-LABEL: wide_cmpgt_h:309; CHECK: // %bb.0:310; CHECK-NEXT: cmpgt p0.h, p0/z, z0.h, #-16311; CHECK-NEXT: ret312 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv8i16(<vscale x 8 x i1> %pg,313 <vscale x 8 x i16> %a,314 <vscale x 2 x i64> splat(i64 -16))315 ret <vscale x 8 x i1> %out316}317 318define <vscale x 4 x i1> @ir_cmpgt_s(<vscale x 4 x i32> %a) {319; CHECK-LABEL: ir_cmpgt_s:320; CHECK: // %bb.0:321; CHECK-NEXT: ptrue p0.s322; CHECK-NEXT: cmpgt p0.s, p0/z, z0.s, #15323; CHECK-NEXT: ret324 %out = icmp sgt <vscale x 4 x i32> %a, splat(i32 15)325 ret <vscale x 4 x i1> %out326}327 328define <vscale x 4 x i1> @int_cmpgt_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {329; CHECK-LABEL: int_cmpgt_s:330; CHECK: // %bb.0:331; CHECK-NEXT: cmpgt p0.s, p0/z, z0.s, #15332; CHECK-NEXT: ret333 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1> %pg,334 <vscale x 4 x i32> %a,335 <vscale x 4 x i32> splat(i32 15))336 ret <vscale x 4 x i1> %out337}338 339define <vscale x 4 x i1> @wide_cmpgt_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {340; CHECK-LABEL: wide_cmpgt_s:341; CHECK: // %bb.0:342; CHECK-NEXT: cmpgt p0.s, p0/z, z0.s, #15343; CHECK-NEXT: ret344 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv4i32(<vscale x 4 x i1> %pg,345 <vscale x 4 x i32> %a,346 <vscale x 2 x i64> splat(i64 15))347 ret <vscale x 4 x i1> %out348}349 350define <vscale x 2 x i1> @ir_cmpgt_d(<vscale x 2 x i64> %a) {351; CHECK-LABEL: ir_cmpgt_d:352; CHECK: // %bb.0:353; CHECK-NEXT: ptrue p0.d354; CHECK-NEXT: cmpgt p0.d, p0/z, z0.d, #0355; CHECK-NEXT: ret356 %out = icmp sgt <vscale x 2 x i64> %a, zeroinitializer357 ret <vscale x 2 x i1> %out358}359 360define <vscale x 2 x i1> @int_cmpgt_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {361; CHECK-LABEL: int_cmpgt_d:362; CHECK: // %bb.0:363; CHECK-NEXT: cmpgt p0.d, p0/z, z0.d, #0364; CHECK-NEXT: ret365 %out = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1> %pg,366 <vscale x 2 x i64> %a,367 <vscale x 2 x i64> zeroinitializer)368 ret <vscale x 2 x i1> %out369}370 371;372; CMPLE373;374 375define <vscale x 16 x i1> @ir_cmple_b(<vscale x 16 x i8> %a) {376; CHECK-LABEL: ir_cmple_b:377; CHECK: // %bb.0:378; CHECK-NEXT: ptrue p0.b379; CHECK-NEXT: cmple p0.b, p0/z, z0.b, #4380; CHECK-NEXT: ret381 %out = icmp sle <vscale x 16 x i8> %a, splat(i8 4)382 ret <vscale x 16 x i1> %out383}384 385define <vscale x 16 x i1> @int_cmple_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {386; CHECK-LABEL: int_cmple_b:387; CHECK: // %bb.0:388; CHECK-NEXT: cmple p0.b, p0/z, z0.b, #4389; CHECK-NEXT: ret390 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1> %pg,391 <vscale x 16 x i8> splat(i8 4),392 <vscale x 16 x i8> %a)393 ret <vscale x 16 x i1> %out394}395 396define <vscale x 16 x i1> @wide_cmple_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {397; CHECK-LABEL: wide_cmple_b:398; CHECK: // %bb.0:399; CHECK-NEXT: cmple p0.b, p0/z, z0.b, #4400; CHECK-NEXT: ret401 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmple.wide.nxv16i8(<vscale x 16 x i1> %pg,402 <vscale x 16 x i8> %a,403 <vscale x 2 x i64> splat(i64 4))404 ret <vscale x 16 x i1> %out405}406 407define <vscale x 8 x i1> @ir_cmple_h(<vscale x 8 x i16> %a) {408; CHECK-LABEL: ir_cmple_h:409; CHECK: // %bb.0:410; CHECK-NEXT: ptrue p0.h411; CHECK-NEXT: cmple p0.h, p0/z, z0.h, #-16412; CHECK-NEXT: ret413 %out = icmp sle <vscale x 8 x i16> %a, splat(i16 -16)414 ret <vscale x 8 x i1> %out415}416 417define <vscale x 8 x i1> @int_cmple_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {418; CHECK-LABEL: int_cmple_h:419; CHECK: // %bb.0:420; CHECK-NEXT: cmple p0.h, p0/z, z0.h, #-16421; CHECK-NEXT: ret422 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1> %pg,423 <vscale x 8 x i16> splat(i16 -16),424 <vscale x 8 x i16> %a)425 ret <vscale x 8 x i1> %out426}427 428define <vscale x 8 x i1> @wide_cmple_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {429; CHECK-LABEL: wide_cmple_h:430; CHECK: // %bb.0:431; CHECK-NEXT: cmple p0.h, p0/z, z0.h, #-16432; CHECK-NEXT: ret433 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmple.wide.nxv8i16(<vscale x 8 x i1> %pg,434 <vscale x 8 x i16> %a,435 <vscale x 2 x i64> splat(i64 -16))436 ret <vscale x 8 x i1> %out437}438 439define <vscale x 4 x i1> @ir_cmple_s(<vscale x 4 x i32> %a) {440; CHECK-LABEL: ir_cmple_s:441; CHECK: // %bb.0:442; CHECK-NEXT: ptrue p0.s443; CHECK-NEXT: cmple p0.s, p0/z, z0.s, #15444; CHECK-NEXT: ret445 %out = icmp sle <vscale x 4 x i32> %a, splat(i32 15)446 ret <vscale x 4 x i1> %out447}448 449define <vscale x 4 x i1> @int_cmple_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {450; CHECK-LABEL: int_cmple_s:451; CHECK: // %bb.0:452; CHECK-NEXT: cmple p0.s, p0/z, z0.s, #15453; CHECK-NEXT: ret454 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1> %pg,455 <vscale x 4 x i32> splat(i32 15),456 <vscale x 4 x i32> %a)457 ret <vscale x 4 x i1> %out458}459 460define <vscale x 4 x i1> @wide_cmple_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {461; CHECK-LABEL: wide_cmple_s:462; CHECK: // %bb.0:463; CHECK-NEXT: cmple p0.s, p0/z, z0.s, #15464; CHECK-NEXT: ret465 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmple.wide.nxv4i32(<vscale x 4 x i1> %pg,466 <vscale x 4 x i32> %a,467 <vscale x 2 x i64> splat(i64 15))468 ret <vscale x 4 x i1> %out469}470 471define <vscale x 2 x i1> @ir_cmple_d(<vscale x 2 x i64> %a) {472; CHECK-LABEL: ir_cmple_d:473; CHECK: // %bb.0:474; CHECK-NEXT: ptrue p0.d475; CHECK-NEXT: cmple p0.d, p0/z, z0.d, #0476; CHECK-NEXT: ret477 %out = icmp sle <vscale x 2 x i64> %a, zeroinitializer478 ret <vscale x 2 x i1> %out479}480 481define <vscale x 2 x i1> @int_cmple_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {482; CHECK-LABEL: int_cmple_d:483; CHECK: // %bb.0:484; CHECK-NEXT: cmple p0.d, p0/z, z0.d, #0485; CHECK-NEXT: ret486 %out = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1> %pg,487 <vscale x 2 x i64> zeroinitializer,488 <vscale x 2 x i64> %a)489 ret <vscale x 2 x i1> %out490}491 492;493; CMPLT494;495 496define <vscale x 16 x i1> @ir_cmplt_b(<vscale x 16 x i8> %a) {497; CHECK-LABEL: ir_cmplt_b:498; CHECK: // %bb.0:499; CHECK-NEXT: ptrue p0.b500; CHECK-NEXT: cmplt p0.b, p0/z, z0.b, #4501; CHECK-NEXT: ret502 %out = icmp slt <vscale x 16 x i8> %a, splat(i8 4)503 ret <vscale x 16 x i1> %out504}505 506define <vscale x 16 x i1> @int_cmplt_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {507; CHECK-LABEL: int_cmplt_b:508; CHECK: // %bb.0:509; CHECK-NEXT: cmplt p0.b, p0/z, z0.b, #4510; CHECK-NEXT: ret511 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1> %pg,512 <vscale x 16 x i8> splat(i8 4),513 <vscale x 16 x i8> %a)514 ret <vscale x 16 x i1> %out515}516 517define <vscale x 16 x i1> @wide_cmplt_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {518; CHECK-LABEL: wide_cmplt_b:519; CHECK: // %bb.0:520; CHECK-NEXT: cmplt p0.b, p0/z, z0.b, #4521; CHECK-NEXT: ret522 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmplt.wide.nxv16i8(<vscale x 16 x i1> %pg,523 <vscale x 16 x i8> %a,524 <vscale x 2 x i64> splat(i64 4))525 ret <vscale x 16 x i1> %out526}527 528define <vscale x 8 x i1> @ir_cmplt_h(<vscale x 8 x i16> %a) {529; CHECK-LABEL: ir_cmplt_h:530; CHECK: // %bb.0:531; CHECK-NEXT: ptrue p0.h532; CHECK-NEXT: cmplt p0.h, p0/z, z0.h, #-16533; CHECK-NEXT: ret534 %out = icmp slt <vscale x 8 x i16> %a, splat(i16 -16)535 ret <vscale x 8 x i1> %out536}537 538define <vscale x 8 x i1> @int_cmplt_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {539; CHECK-LABEL: int_cmplt_h:540; CHECK: // %bb.0:541; CHECK-NEXT: cmplt p0.h, p0/z, z0.h, #-16542; CHECK-NEXT: ret543 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1> %pg,544 <vscale x 8 x i16> splat(i16 -16),545 <vscale x 8 x i16> %a)546 ret <vscale x 8 x i1> %out547}548 549define <vscale x 8 x i1> @wide_cmplt_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {550; CHECK-LABEL: wide_cmplt_h:551; CHECK: // %bb.0:552; CHECK-NEXT: cmplt p0.h, p0/z, z0.h, #-16553; CHECK-NEXT: ret554 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmplt.wide.nxv8i16(<vscale x 8 x i1> %pg,555 <vscale x 8 x i16> %a,556 <vscale x 2 x i64> splat(i64 -16))557 ret <vscale x 8 x i1> %out558}559 560define <vscale x 4 x i1> @ir_cmplt_s(<vscale x 4 x i32> %a) {561; CHECK-LABEL: ir_cmplt_s:562; CHECK: // %bb.0:563; CHECK-NEXT: ptrue p0.s564; CHECK-NEXT: cmplt p0.s, p0/z, z0.s, #15565; CHECK-NEXT: ret566 %out = icmp slt <vscale x 4 x i32> %a, splat(i32 15)567 ret <vscale x 4 x i1> %out568}569 570define <vscale x 4 x i1> @int_cmplt_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {571; CHECK-LABEL: int_cmplt_s:572; CHECK: // %bb.0:573; CHECK-NEXT: cmplt p0.s, p0/z, z0.s, #15574; CHECK-NEXT: ret575 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1> %pg,576 <vscale x 4 x i32> splat(i32 15),577 <vscale x 4 x i32> %a)578 ret <vscale x 4 x i1> %out579}580 581define <vscale x 4 x i1> @wide_cmplt_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {582; CHECK-LABEL: wide_cmplt_s:583; CHECK: // %bb.0:584; CHECK-NEXT: cmplt p0.s, p0/z, z0.s, #15585; CHECK-NEXT: ret586 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmplt.wide.nxv4i32(<vscale x 4 x i1> %pg,587 <vscale x 4 x i32> %a,588 <vscale x 2 x i64> splat(i64 15))589 ret <vscale x 4 x i1> %out590}591 592define <vscale x 2 x i1> @ir_cmplt_d(<vscale x 2 x i64> %a) {593; CHECK-LABEL: ir_cmplt_d:594; CHECK: // %bb.0:595; CHECK-NEXT: ptrue p0.d596; CHECK-NEXT: cmplt p0.d, p0/z, z0.d, #0597; CHECK-NEXT: ret598 %out = icmp slt <vscale x 2 x i64> %a, zeroinitializer599 ret <vscale x 2 x i1> %out600}601 602define <vscale x 2 x i1> @int_cmplt_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {603; CHECK-LABEL: int_cmplt_d:604; CHECK: // %bb.0:605; CHECK-NEXT: cmplt p0.d, p0/z, z0.d, #0606; CHECK-NEXT: ret607 %out = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1> %pg,608 <vscale x 2 x i64> zeroinitializer,609 <vscale x 2 x i64> %a)610 ret <vscale x 2 x i1> %out611}612 613;614; CMPNE615;616 617define <vscale x 16 x i1> @ir_cmpne_b(<vscale x 16 x i8> %a) {618; CHECK-LABEL: ir_cmpne_b:619; CHECK: // %bb.0:620; CHECK-NEXT: ptrue p0.b621; CHECK-NEXT: cmpne p0.b, p0/z, z0.b, #4622; CHECK-NEXT: ret623 %out = icmp ne <vscale x 16 x i8> %a, splat(i8 4)624 ret <vscale x 16 x i1> %out625}626 627define <vscale x 16 x i1> @int_cmpne_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {628; CHECK-LABEL: int_cmpne_b:629; CHECK: // %bb.0:630; CHECK-NEXT: cmpne p0.b, p0/z, z0.b, #4631; CHECK-NEXT: ret632 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1> %pg,633 <vscale x 16 x i8> %a,634 <vscale x 16 x i8> splat(i8 4))635 ret <vscale x 16 x i1> %out636}637 638define <vscale x 16 x i1> @wide_cmpne_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {639; CHECK-LABEL: wide_cmpne_b:640; CHECK: // %bb.0:641; CHECK-NEXT: cmpne p0.b, p0/z, z0.b, #4642; CHECK-NEXT: ret643 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1> %pg,644 <vscale x 16 x i8> %a,645 <vscale x 2 x i64> splat(i64 4))646 ret <vscale x 16 x i1> %out647}648 649define <vscale x 8 x i1> @ir_cmpne_h(<vscale x 8 x i16> %a) {650; CHECK-LABEL: ir_cmpne_h:651; CHECK: // %bb.0:652; CHECK-NEXT: ptrue p0.h653; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, #-16654; CHECK-NEXT: ret655 %out = icmp ne <vscale x 8 x i16> %a, splat(i16 -16)656 ret <vscale x 8 x i1> %out657}658 659define <vscale x 8 x i1> @int_cmpne_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {660; CHECK-LABEL: int_cmpne_h:661; CHECK: // %bb.0:662; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, #-16663; CHECK-NEXT: ret664 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %pg,665 <vscale x 8 x i16> %a,666 <vscale x 8 x i16> splat(i16 -16))667 ret <vscale x 8 x i1> %out668}669 670define <vscale x 8 x i1> @wide_cmpne_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {671; CHECK-LABEL: wide_cmpne_h:672; CHECK: // %bb.0:673; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, #-16674; CHECK-NEXT: ret675 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.wide.nxv8i16(<vscale x 8 x i1> %pg,676 <vscale x 8 x i16> %a,677 <vscale x 2 x i64> splat(i64 -16))678 ret <vscale x 8 x i1> %out679}680 681define <vscale x 4 x i1> @ir_cmpne_s(<vscale x 4 x i32> %a) {682; CHECK-LABEL: ir_cmpne_s:683; CHECK: // %bb.0:684; CHECK-NEXT: ptrue p0.s685; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #15686; CHECK-NEXT: ret687 %out = icmp ne <vscale x 4 x i32> %a, splat(i32 15)688 ret <vscale x 4 x i1> %out689}690 691define <vscale x 4 x i1> @int_cmpne_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {692; CHECK-LABEL: int_cmpne_s:693; CHECK: // %bb.0:694; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #15695; CHECK-NEXT: ret696 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %pg,697 <vscale x 4 x i32> %a,698 <vscale x 4 x i32> splat(i32 15))699 ret <vscale x 4 x i1> %out700}701 702define <vscale x 4 x i1> @wide_cmpne_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {703; CHECK-LABEL: wide_cmpne_s:704; CHECK: // %bb.0:705; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #15706; CHECK-NEXT: ret707 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1> %pg,708 <vscale x 4 x i32> %a,709 <vscale x 2 x i64> splat(i64 15))710 ret <vscale x 4 x i1> %out711}712 713define <vscale x 2 x i1> @ir_cmpne_d(<vscale x 2 x i64> %a) {714; CHECK-LABEL: ir_cmpne_d:715; CHECK: // %bb.0:716; CHECK-NEXT: ptrue p0.d717; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #0718; CHECK-NEXT: ret719 %out = icmp ne <vscale x 2 x i64> %a, zeroinitializer720 ret <vscale x 2 x i1> %out721}722 723define <vscale x 2 x i1> @int_cmpne_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {724; CHECK-LABEL: int_cmpne_d:725; CHECK: // %bb.0:726; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #0727; CHECK-NEXT: ret728 %out = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %pg,729 <vscale x 2 x i64> %a,730 <vscale x 2 x i64> zeroinitializer)731 ret <vscale x 2 x i1> %out732}733 734;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;735;; Unsigned Comparisons ;;736;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;737 738;739; CMPHI740;741 742define <vscale x 16 x i1> @ir_cmphi_b(<vscale x 16 x i8> %a) {743; CHECK-LABEL: ir_cmphi_b:744; CHECK: // %bb.0:745; CHECK-NEXT: ptrue p0.b746; CHECK-NEXT: cmphi p0.b, p0/z, z0.b, #4747; CHECK-NEXT: ret748 %out = icmp ugt <vscale x 16 x i8> %a, splat(i8 4)749 ret <vscale x 16 x i1> %out750}751 752define <vscale x 16 x i1> @int_cmphi_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {753; CHECK-LABEL: int_cmphi_b:754; CHECK: // %bb.0:755; CHECK-NEXT: cmphi p0.b, p0/z, z0.b, #4756; CHECK-NEXT: ret757 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1> %pg,758 <vscale x 16 x i8> %a,759 <vscale x 16 x i8> splat(i8 4))760 ret <vscale x 16 x i1> %out761}762 763define <vscale x 16 x i1> @wide_cmphi_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {764; CHECK-LABEL: wide_cmphi_b:765; CHECK: // %bb.0:766; CHECK-NEXT: cmphi p0.b, p0/z, z0.b, #4767; CHECK-NEXT: ret768 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.wide.nxv16i8(<vscale x 16 x i1> %pg,769 <vscale x 16 x i8> %a,770 <vscale x 2 x i64> splat(i64 4))771 ret <vscale x 16 x i1> %out772}773 774define <vscale x 8 x i1> @ir_cmphi_h(<vscale x 8 x i16> %a) {775; CHECK-LABEL: ir_cmphi_h:776; CHECK: // %bb.0:777; CHECK-NEXT: ptrue p0.h778; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, #0779; CHECK-NEXT: ret780 %out = icmp ugt <vscale x 8 x i16> %a, zeroinitializer781 ret <vscale x 8 x i1> %out782}783 784define <vscale x 8 x i1> @int_cmphi_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {785; CHECK-LABEL: int_cmphi_h:786; CHECK: // %bb.0:787; CHECK-NEXT: cmphi p0.h, p0/z, z0.h, #0788; CHECK-NEXT: ret789 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1> %pg,790 <vscale x 8 x i16> %a,791 <vscale x 8 x i16> zeroinitializer)792 ret <vscale x 8 x i1> %out793}794 795define <vscale x 8 x i1> @wide_cmphi_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {796; CHECK-LABEL: wide_cmphi_h:797; CHECK: // %bb.0:798; CHECK-NEXT: cmphi p0.h, p0/z, z0.h, #0799; CHECK-NEXT: ret800 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.wide.nxv8i16(<vscale x 8 x i1> %pg,801 <vscale x 8 x i16> %a,802 <vscale x 2 x i64> zeroinitializer)803 ret <vscale x 8 x i1> %out804}805 806define <vscale x 4 x i1> @ir_cmphi_s(<vscale x 4 x i32> %a) {807; CHECK-LABEL: ir_cmphi_s:808; CHECK: // %bb.0:809; CHECK-NEXT: ptrue p0.s810; CHECK-NEXT: cmphi p0.s, p0/z, z0.s, #68811; CHECK-NEXT: ret812 %out = icmp ugt <vscale x 4 x i32> %a, splat(i32 68)813 ret <vscale x 4 x i1> %out814}815 816define <vscale x 4 x i1> @int_cmphi_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {817; CHECK-LABEL: int_cmphi_s:818; CHECK: // %bb.0:819; CHECK-NEXT: cmphi p0.s, p0/z, z0.s, #68820; CHECK-NEXT: ret821 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1> %pg,822 <vscale x 4 x i32> %a,823 <vscale x 4 x i32> splat(i32 68))824 ret <vscale x 4 x i1> %out825}826 827define <vscale x 4 x i1> @wide_cmphi_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {828; CHECK-LABEL: wide_cmphi_s:829; CHECK: // %bb.0:830; CHECK-NEXT: cmphi p0.s, p0/z, z0.s, #68831; CHECK-NEXT: ret832 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.wide.nxv4i32(<vscale x 4 x i1> %pg,833 <vscale x 4 x i32> %a,834 <vscale x 2 x i64> splat(i64 68))835 ret <vscale x 4 x i1> %out836}837 838define <vscale x 2 x i1> @ir_cmphi_d(<vscale x 2 x i64> %a) {839; CHECK-LABEL: ir_cmphi_d:840; CHECK: // %bb.0:841; CHECK-NEXT: ptrue p0.d842; CHECK-NEXT: cmphi p0.d, p0/z, z0.d, #127843; CHECK-NEXT: ret844 %out = icmp ugt <vscale x 2 x i64> %a, splat(i64 127)845 ret <vscale x 2 x i1> %out846}847 848define <vscale x 2 x i1> @int_cmphi_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {849; CHECK-LABEL: int_cmphi_d:850; CHECK: // %bb.0:851; CHECK-NEXT: cmphi p0.d, p0/z, z0.d, #127852; CHECK-NEXT: ret853 %out = call <vscale x 2 x i1> @llvm.aarch64.sve.cmphi.nxv2i64(<vscale x 2 x i1> %pg,854 <vscale x 2 x i64> %a,855 <vscale x 2 x i64> splat(i64 127))856 ret <vscale x 2 x i1> %out857}858 859;860; CMPHS861;862 863define <vscale x 16 x i1> @ir_cmphs_b(<vscale x 16 x i8> %a) {864; CHECK-LABEL: ir_cmphs_b:865; CHECK: // %bb.0:866; CHECK-NEXT: ptrue p0.b867; CHECK-NEXT: cmphs p0.b, p0/z, z0.b, #4868; CHECK-NEXT: ret869 %out = icmp uge <vscale x 16 x i8> %a, splat(i8 4)870 ret <vscale x 16 x i1> %out871}872 873define <vscale x 16 x i1> @int_cmphs_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {874; CHECK-LABEL: int_cmphs_b:875; CHECK: // %bb.0:876; CHECK-NEXT: cmphs p0.b, p0/z, z0.b, #4877; CHECK-NEXT: ret878 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1> %pg,879 <vscale x 16 x i8> %a,880 <vscale x 16 x i8> splat(i8 4))881 ret <vscale x 16 x i1> %out882}883 884define <vscale x 16 x i1> @wide_cmphs_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {885; CHECK-LABEL: wide_cmphs_b:886; CHECK: // %bb.0:887; CHECK-NEXT: cmphs p0.b, p0/z, z0.b, #4888; CHECK-NEXT: ret889 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.wide.nxv16i8(<vscale x 16 x i1> %pg,890 <vscale x 16 x i8> %a,891 <vscale x 2 x i64> splat(i64 4))892 ret <vscale x 16 x i1> %out893}894 895define <vscale x 8 x i1> @ir_cmphs_h(<vscale x 8 x i16> %a) {896; CHECK-LABEL: ir_cmphs_h:897; CHECK: // %bb.0:898; CHECK-NEXT: ptrue p0.h899; CHECK-NEXT: ret900 %out = icmp uge <vscale x 8 x i16> %a, zeroinitializer901 ret <vscale x 8 x i1> %out902}903 904define <vscale x 8 x i1> @int_cmphs_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {905; CHECK-LABEL: int_cmphs_h:906; CHECK: // %bb.0:907; CHECK-NEXT: cmphs p0.h, p0/z, z0.h, #0908; CHECK-NEXT: ret909 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1> %pg,910 <vscale x 8 x i16> %a,911 <vscale x 8 x i16> zeroinitializer)912 ret <vscale x 8 x i1> %out913}914 915define <vscale x 8 x i1> @wide_cmphs_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {916; CHECK-LABEL: wide_cmphs_h:917; CHECK: // %bb.0:918; CHECK-NEXT: cmphs p0.h, p0/z, z0.h, #0919; CHECK-NEXT: ret920 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.wide.nxv8i16(<vscale x 8 x i1> %pg,921 <vscale x 8 x i16> %a,922 <vscale x 2 x i64> zeroinitializer)923 ret <vscale x 8 x i1> %out924}925 926define <vscale x 4 x i1> @ir_cmphs_s(<vscale x 4 x i32> %a) {927; CHECK-LABEL: ir_cmphs_s:928; CHECK: // %bb.0:929; CHECK-NEXT: ptrue p0.s930; CHECK-NEXT: cmphs p0.s, p0/z, z0.s, #68931; CHECK-NEXT: ret932 %out = icmp uge <vscale x 4 x i32> %a, splat(i32 68)933 ret <vscale x 4 x i1> %out934}935 936define <vscale x 4 x i1> @int_cmphs_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {937; CHECK-LABEL: int_cmphs_s:938; CHECK: // %bb.0:939; CHECK-NEXT: cmphs p0.s, p0/z, z0.s, #68940; CHECK-NEXT: ret941 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1> %pg,942 <vscale x 4 x i32> %a,943 <vscale x 4 x i32> splat(i32 68))944 ret <vscale x 4 x i1> %out945}946 947define <vscale x 4 x i1> @wide_cmphs_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {948; CHECK-LABEL: wide_cmphs_s:949; CHECK: // %bb.0:950; CHECK-NEXT: cmphs p0.s, p0/z, z0.s, #68951; CHECK-NEXT: ret952 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.wide.nxv4i32(<vscale x 4 x i1> %pg,953 <vscale x 4 x i32> %a,954 <vscale x 2 x i64> splat(i64 68))955 ret <vscale x 4 x i1> %out956}957 958define <vscale x 2 x i1> @ir_cmphs_d(<vscale x 2 x i64> %a) {959; CHECK-LABEL: ir_cmphs_d:960; CHECK: // %bb.0:961; CHECK-NEXT: ptrue p0.d962; CHECK-NEXT: cmphs p0.d, p0/z, z0.d, #127963; CHECK-NEXT: ret964 %out = icmp uge <vscale x 2 x i64> %a, splat(i64 127)965 ret <vscale x 2 x i1> %out966}967 968define <vscale x 2 x i1> @int_cmphs_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {969; CHECK-LABEL: int_cmphs_d:970; CHECK: // %bb.0:971; CHECK-NEXT: cmphs p0.d, p0/z, z0.d, #127972; CHECK-NEXT: ret973 %out = call <vscale x 2 x i1> @llvm.aarch64.sve.cmphs.nxv2i64(<vscale x 2 x i1> %pg,974 <vscale x 2 x i64> %a,975 <vscale x 2 x i64> splat(i64 127))976 ret <vscale x 2 x i1> %out977}978 979;980; CMPLO981;982 983define <vscale x 16 x i1> @ir_cmplo_b(<vscale x 16 x i8> %a) {984; CHECK-LABEL: ir_cmplo_b:985; CHECK: // %bb.0:986; CHECK-NEXT: ptrue p0.b987; CHECK-NEXT: cmplo p0.b, p0/z, z0.b, #4988; CHECK-NEXT: ret989 %out = icmp ult <vscale x 16 x i8> %a, splat(i8 4)990 ret <vscale x 16 x i1> %out991}992 993define <vscale x 16 x i1> @int_cmplo_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {994; CHECK-LABEL: int_cmplo_b:995; CHECK: // %bb.0:996; CHECK-NEXT: cmplo p0.b, p0/z, z0.b, #4997; CHECK-NEXT: ret998 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1> %pg,999 <vscale x 16 x i8> splat(i8 4),1000 <vscale x 16 x i8> %a)1001 ret <vscale x 16 x i1> %out1002}1003 1004define <vscale x 16 x i1> @wide_cmplo_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {1005; CHECK-LABEL: wide_cmplo_b:1006; CHECK: // %bb.0:1007; CHECK-NEXT: cmplo p0.b, p0/z, z0.b, #41008; CHECK-NEXT: ret1009 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmplo.wide.nxv16i8(<vscale x 16 x i1> %pg,1010 <vscale x 16 x i8> %a,1011 <vscale x 2 x i64> splat(i64 4))1012 ret <vscale x 16 x i1> %out1013}1014 1015define <vscale x 8 x i1> @ir_cmplo_h(<vscale x 8 x i16> %a) {1016; CHECK-LABEL: ir_cmplo_h:1017; CHECK: // %bb.0:1018; CHECK-NEXT: ptrue p0.h1019; CHECK-NEXT: cmplo p0.h, p0/z, z0.h, #21020; CHECK-NEXT: ret1021 %out = icmp ult <vscale x 8 x i16> %a, splat(i16 2)1022 ret <vscale x 8 x i1> %out1023}1024 1025define <vscale x 8 x i1> @int_cmplo_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {1026; CHECK-LABEL: int_cmplo_h:1027; CHECK: // %bb.0:1028; CHECK-NEXT: cmplo p0.h, p0/z, z0.h, #31029; CHECK-NEXT: ret1030 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1> %pg,1031 <vscale x 8 x i16> splat(i16 3),1032 <vscale x 8 x i16> %a)1033 ret <vscale x 8 x i1> %out1034}1035 1036define <vscale x 8 x i1> @wide_cmplo_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {1037; CHECK-LABEL: wide_cmplo_h:1038; CHECK: // %bb.0:1039; CHECK-NEXT: cmplo p0.h, p0/z, z0.h, #41040; CHECK-NEXT: ret1041 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmplo.wide.nxv8i16(<vscale x 8 x i1> %pg,1042 <vscale x 8 x i16> %a,1043 <vscale x 2 x i64> splat(i64 4))1044 ret <vscale x 8 x i1> %out1045}1046 1047define <vscale x 4 x i1> @ir_cmplo_s(<vscale x 4 x i32> %a) {1048; CHECK-LABEL: ir_cmplo_s:1049; CHECK: // %bb.0:1050; CHECK-NEXT: ptrue p0.s1051; CHECK-NEXT: cmplo p0.s, p0/z, z0.s, #681052; CHECK-NEXT: ret1053 %out = icmp ult <vscale x 4 x i32> %a, splat(i32 68)1054 ret <vscale x 4 x i1> %out1055}1056 1057define <vscale x 4 x i1> @int_cmplo_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {1058; CHECK-LABEL: int_cmplo_s:1059; CHECK: // %bb.0:1060; CHECK-NEXT: cmplo p0.s, p0/z, z0.s, #681061; CHECK-NEXT: ret1062 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1> %pg,1063 <vscale x 4 x i32> splat(i32 68),1064 <vscale x 4 x i32> %a)1065 ret <vscale x 4 x i1> %out1066}1067 1068define <vscale x 4 x i1> @wide_cmplo_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {1069; CHECK-LABEL: wide_cmplo_s:1070; CHECK: // %bb.0:1071; CHECK-NEXT: cmplo p0.s, p0/z, z0.s, #681072; CHECK-NEXT: ret1073 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmplo.wide.nxv4i32(<vscale x 4 x i1> %pg,1074 <vscale x 4 x i32> %a,1075 <vscale x 2 x i64> splat(i64 68))1076 ret <vscale x 4 x i1> %out1077}1078 1079define <vscale x 2 x i1> @ir_cmplo_d(<vscale x 2 x i64> %a) {1080; CHECK-LABEL: ir_cmplo_d:1081; CHECK: // %bb.0:1082; CHECK-NEXT: ptrue p0.d1083; CHECK-NEXT: cmplo p0.d, p0/z, z0.d, #1271084; CHECK-NEXT: ret1085 %out = icmp ult <vscale x 2 x i64> %a, splat(i64 127)1086 ret <vscale x 2 x i1> %out1087}1088 1089define <vscale x 2 x i1> @int_cmplo_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {1090; CHECK-LABEL: int_cmplo_d:1091; CHECK: // %bb.0:1092; CHECK-NEXT: cmplo p0.d, p0/z, z0.d, #1271093; CHECK-NEXT: ret1094 %out = call <vscale x 2 x i1> @llvm.aarch64.sve.cmphi.nxv2i64(<vscale x 2 x i1> %pg,1095 <vscale x 2 x i64> splat(i64 127),1096 <vscale x 2 x i64> %a)1097 ret <vscale x 2 x i1> %out1098}1099 1100;1101; CMPLS1102;1103 1104define <vscale x 16 x i1> @ir_cmpls_b(<vscale x 16 x i8> %a) {1105; CHECK-LABEL: ir_cmpls_b:1106; CHECK: // %bb.0:1107; CHECK-NEXT: ptrue p0.b1108; CHECK-NEXT: cmpls p0.b, p0/z, z0.b, #41109; CHECK-NEXT: ret1110 %out = icmp ule <vscale x 16 x i8> %a, splat(i8 4)1111 ret <vscale x 16 x i1> %out1112}1113 1114define <vscale x 16 x i1> @int_cmpls_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {1115; CHECK-LABEL: int_cmpls_b:1116; CHECK: // %bb.0:1117; CHECK-NEXT: cmpls p0.b, p0/z, z0.b, #41118; CHECK-NEXT: ret1119 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1> %pg,1120 <vscale x 16 x i8> splat(i8 4),1121 <vscale x 16 x i8> %a)1122 ret <vscale x 16 x i1> %out1123}1124 1125define <vscale x 16 x i1> @wide_cmpls_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {1126; CHECK-LABEL: wide_cmpls_b:1127; CHECK: // %bb.0:1128; CHECK-NEXT: cmpls p0.b, p0/z, z0.b, #41129; CHECK-NEXT: ret1130 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpls.wide.nxv16i8(<vscale x 16 x i1> %pg,1131 <vscale x 16 x i8> %a,1132 <vscale x 2 x i64> splat(i64 4))1133 ret <vscale x 16 x i1> %out1134}1135 1136define <vscale x 8 x i1> @ir_cmpls_h(<vscale x 8 x i16> %a) {1137; CHECK-LABEL: ir_cmpls_h:1138; CHECK: // %bb.0:1139; CHECK-NEXT: ptrue p0.h1140; CHECK-NEXT: cmpls p0.h, p0/z, z0.h, #01141; CHECK-NEXT: ret1142 %out = icmp ule <vscale x 8 x i16> %a, zeroinitializer1143 ret <vscale x 8 x i1> %out1144}1145 1146define <vscale x 8 x i1> @int_cmpls_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {1147; CHECK-LABEL: int_cmpls_h:1148; CHECK: // %bb.0:1149; CHECK-NEXT: cmpls p0.h, p0/z, z0.h, #01150; CHECK-NEXT: ret1151 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1> %pg,1152 <vscale x 8 x i16> zeroinitializer,1153 <vscale x 8 x i16> %a)1154 ret <vscale x 8 x i1> %out1155}1156 1157define <vscale x 8 x i1> @wide_cmpls_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {1158; CHECK-LABEL: wide_cmpls_h:1159; CHECK: // %bb.0:1160; CHECK-NEXT: cmpls p0.h, p0/z, z0.h, #01161; CHECK-NEXT: ret1162 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpls.wide.nxv8i16(<vscale x 8 x i1> %pg,1163 <vscale x 8 x i16> %a,1164 <vscale x 2 x i64> zeroinitializer)1165 ret <vscale x 8 x i1> %out1166}1167 1168define <vscale x 4 x i1> @ir_cmpls_s(<vscale x 4 x i32> %a) {1169; CHECK-LABEL: ir_cmpls_s:1170; CHECK: // %bb.0:1171; CHECK-NEXT: ptrue p0.s1172; CHECK-NEXT: cmpls p0.s, p0/z, z0.s, #681173; CHECK-NEXT: ret1174 %out = icmp ule <vscale x 4 x i32> %a, splat(i32 68)1175 ret <vscale x 4 x i1> %out1176}1177 1178define <vscale x 4 x i1> @int_cmpls_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {1179; CHECK-LABEL: int_cmpls_s:1180; CHECK: // %bb.0:1181; CHECK-NEXT: cmpls p0.s, p0/z, z0.s, #681182; CHECK-NEXT: ret1183 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1> %pg,1184 <vscale x 4 x i32> splat(i32 68),1185 <vscale x 4 x i32> %a)1186 ret <vscale x 4 x i1> %out1187}1188 1189define <vscale x 4 x i1> @wide_cmpls_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {1190; CHECK-LABEL: wide_cmpls_s:1191; CHECK: // %bb.0:1192; CHECK-NEXT: cmpls p0.s, p0/z, z0.s, #681193; CHECK-NEXT: ret1194 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpls.wide.nxv4i32(<vscale x 4 x i1> %pg,1195 <vscale x 4 x i32> %a,1196 <vscale x 2 x i64> splat(i64 68))1197 ret <vscale x 4 x i1> %out1198}1199 1200define <vscale x 2 x i1> @ir_cmpls_d(<vscale x 2 x i64> %a) {1201; CHECK-LABEL: ir_cmpls_d:1202; CHECK: // %bb.0:1203; CHECK-NEXT: ptrue p0.d1204; CHECK-NEXT: cmpls p0.d, p0/z, z0.d, #1271205; CHECK-NEXT: ret1206 %out = icmp ule <vscale x 2 x i64> %a, splat(i64 127)1207 ret <vscale x 2 x i1> %out1208}1209 1210define <vscale x 2 x i1> @int_cmpls_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {1211; CHECK-LABEL: int_cmpls_d:1212; CHECK: // %bb.0:1213; CHECK-NEXT: cmpls p0.d, p0/z, z0.d, #1271214; CHECK-NEXT: ret1215 %out = call <vscale x 2 x i1> @llvm.aarch64.sve.cmphs.nxv2i64(<vscale x 2 x i1> %pg,1216 <vscale x 2 x i64> splat(i64 127),1217 <vscale x 2 x i64> %a)1218 ret <vscale x 2 x i1> %out1219}1220 1221declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1222declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1223declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1224declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpeq.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1225declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)1226declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)1227declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)1228 1229declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1230declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1231declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1232declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1233declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)1234declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)1235declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)1236 1237declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1238declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1239declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1240declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1241declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)1242declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)1243declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)1244 1245declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1246declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1247declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1248declare <vscale x 2 x i1> @llvm.aarch64.sve.cmphi.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1249declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)1250declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)1251declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)1252 1253declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1254declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1255declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1256declare <vscale x 2 x i1> @llvm.aarch64.sve.cmphs.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1257declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)1258declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)1259declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)1260 1261declare <vscale x 16 x i1> @llvm.aarch64.sve.cmple.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)1262declare <vscale x 8 x i1> @llvm.aarch64.sve.cmple.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)1263declare <vscale x 4 x i1> @llvm.aarch64.sve.cmple.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)1264 1265declare <vscale x 16 x i1> @llvm.aarch64.sve.cmplo.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)1266declare <vscale x 8 x i1> @llvm.aarch64.sve.cmplo.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)1267declare <vscale x 4 x i1> @llvm.aarch64.sve.cmplo.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)1268 1269declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpls.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)1270declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpls.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)1271declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpls.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)1272 1273declare <vscale x 16 x i1> @llvm.aarch64.sve.cmplt.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)1274declare <vscale x 8 x i1> @llvm.aarch64.sve.cmplt.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)1275declare <vscale x 4 x i1> @llvm.aarch64.sve.cmplt.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)1276 1277declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1278declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1279declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1280declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1281declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)1282declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)1283declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)1284