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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4;5; CMPEQ6;7 8define <vscale x 16 x i1> @cmpeq_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {9; CHECK-LABEL: cmpeq_b:10; CHECK: // %bb.0:11; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, z1.b12; CHECK-NEXT: ret13 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %pg,14 <vscale x 16 x i8> %a,15 <vscale x 16 x i8> %b)16 ret <vscale x 16 x i1> %out17}18 19define <vscale x 8 x i1> @cmpeq_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {20; CHECK-LABEL: cmpeq_h:21; CHECK: // %bb.0:22; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, z1.h23; CHECK-NEXT: ret24 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1> %pg,25 <vscale x 8 x i16> %a,26 <vscale x 8 x i16> %b)27 ret <vscale x 8 x i1> %out28}29 30define <vscale x 4 x i1> @cmpeq_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {31; CHECK-LABEL: cmpeq_s:32; CHECK: // %bb.0:33; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, z1.s34; CHECK-NEXT: ret35 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.nxv4i32(<vscale x 4 x i1> %pg,36 <vscale x 4 x i32> %a,37 <vscale x 4 x i32> %b)38 ret <vscale x 4 x i1> %out39}40 41define <vscale x 2 x i1> @cmpeq_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {42; CHECK-LABEL: cmpeq_d:43; CHECK: // %bb.0:44; CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d45; CHECK-NEXT: ret46 %out = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpeq.nxv2i64(<vscale x 2 x i1> %pg,47 <vscale x 2 x i64> %a,48 <vscale x 2 x i64> %b)49 ret <vscale x 2 x i1> %out50}51 52define <vscale x 16 x i1> @cmpeq_wide_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {53; CHECK-LABEL: cmpeq_wide_b:54; CHECK: // %bb.0:55; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, z1.d56; CHECK-NEXT: ret57 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.wide.nxv16i8(<vscale x 16 x i1> %pg,58 <vscale x 16 x i8> %a,59 <vscale x 2 x i64> %b)60 ret <vscale x 16 x i1> %out61}62 63define <vscale x 8 x i1> @cmpeq_wide_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {64; CHECK-LABEL: cmpeq_wide_h:65; CHECK: // %bb.0:66; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, z1.d67; CHECK-NEXT: ret68 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.wide.nxv8i16(<vscale x 8 x i1> %pg,69 <vscale x 8 x i16> %a,70 <vscale x 2 x i64> %b)71 ret <vscale x 8 x i1> %out72}73 74define <vscale x 4 x i1> @cmpeq_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {75; CHECK-LABEL: cmpeq_wide_s:76; CHECK: // %bb.0:77; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, z1.d78; CHECK-NEXT: ret79 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.wide.nxv4i32(<vscale x 4 x i1> %pg,80 <vscale x 4 x i32> %a,81 <vscale x 2 x i64> %b)82 ret <vscale x 4 x i1> %out83}84 85define <vscale x 16 x i1> @cmpeq_ir_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {86; CHECK-LABEL: cmpeq_ir_b:87; CHECK: // %bb.0:88; CHECK-NEXT: ptrue p0.b89; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, z1.b90; CHECK-NEXT: ret91 %out = icmp eq <vscale x 16 x i8> %a, %b92 ret <vscale x 16 x i1> %out93}94 95define <vscale x 8 x i1> @cmpeq_ir_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {96; CHECK-LABEL: cmpeq_ir_h:97; CHECK: // %bb.0:98; CHECK-NEXT: ptrue p0.h99; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, z1.h100; CHECK-NEXT: ret101 %out = icmp eq <vscale x 8 x i16> %a, %b102 ret <vscale x 8 x i1> %out103}104 105define <vscale x 4 x i1> @cmpeq_ir_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {106; CHECK-LABEL: cmpeq_ir_s:107; CHECK: // %bb.0:108; CHECK-NEXT: ptrue p0.s109; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, z1.s110; CHECK-NEXT: ret111 %out = icmp eq <vscale x 4 x i32> %a, %b112 ret <vscale x 4 x i1> %out113}114 115define <vscale x 2 x i1> @cmpeq_ir_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {116; CHECK-LABEL: cmpeq_ir_d:117; CHECK: // %bb.0:118; CHECK-NEXT: ptrue p0.d119; CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d120; CHECK-NEXT: ret121 %out = icmp eq <vscale x 2 x i64> %a, %b122 ret <vscale x 2 x i1> %out123}124 125;126; CMPGE127;128 129define <vscale x 16 x i1> @cmpge_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {130; CHECK-LABEL: cmpge_b:131; CHECK: // %bb.0:132; CHECK-NEXT: cmpge p0.b, p0/z, z0.b, z1.b133; CHECK-NEXT: ret134 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1> %pg,135 <vscale x 16 x i8> %a,136 <vscale x 16 x i8> %b)137 ret <vscale x 16 x i1> %out138}139 140define <vscale x 8 x i1> @cmpge_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {141; CHECK-LABEL: cmpge_h:142; CHECK: // %bb.0:143; CHECK-NEXT: cmpge p0.h, p0/z, z0.h, z1.h144; CHECK-NEXT: ret145 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1> %pg,146 <vscale x 8 x i16> %a,147 <vscale x 8 x i16> %b)148 ret <vscale x 8 x i1> %out149}150 151define <vscale x 4 x i1> @cmpge_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {152; CHECK-LABEL: cmpge_s:153; CHECK: // %bb.0:154; CHECK-NEXT: cmpge p0.s, p0/z, z0.s, z1.s155; CHECK-NEXT: ret156 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1> %pg,157 <vscale x 4 x i32> %a,158 <vscale x 4 x i32> %b)159 ret <vscale x 4 x i1> %out160}161 162define <vscale x 2 x i1> @cmpge_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {163; CHECK-LABEL: cmpge_d:164; CHECK: // %bb.0:165; CHECK-NEXT: cmpge p0.d, p0/z, z0.d, z1.d166; CHECK-NEXT: ret167 %out = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1> %pg,168 <vscale x 2 x i64> %a,169 <vscale x 2 x i64> %b)170 ret <vscale x 2 x i1> %out171}172 173define <vscale x 16 x i1> @cmpge_wide_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {174; CHECK-LABEL: cmpge_wide_b:175; CHECK: // %bb.0:176; CHECK-NEXT: cmpge p0.b, p0/z, z0.b, z1.d177; CHECK-NEXT: ret178 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.wide.nxv16i8(<vscale x 16 x i1> %pg,179 <vscale x 16 x i8> %a,180 <vscale x 2 x i64> %b)181 ret <vscale x 16 x i1> %out182}183 184define <vscale x 8 x i1> @cmpge_wide_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {185; CHECK-LABEL: cmpge_wide_h:186; CHECK: // %bb.0:187; CHECK-NEXT: cmpge p0.h, p0/z, z0.h, z1.d188; CHECK-NEXT: ret189 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.wide.nxv8i16(<vscale x 8 x i1> %pg,190 <vscale x 8 x i16> %a,191 <vscale x 2 x i64> %b)192 ret <vscale x 8 x i1> %out193}194 195define <vscale x 4 x i1> @cmpge_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {196; CHECK-LABEL: cmpge_wide_s:197; CHECK: // %bb.0:198; CHECK-NEXT: cmpge p0.s, p0/z, z0.s, z1.d199; CHECK-NEXT: ret200 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.wide.nxv4i32(<vscale x 4 x i1> %pg,201 <vscale x 4 x i32> %a,202 <vscale x 2 x i64> %b)203 ret <vscale x 4 x i1> %out204}205 206define <vscale x 16 x i1> @cmpge_ir_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {207; CHECK-LABEL: cmpge_ir_b:208; CHECK: // %bb.0:209; CHECK-NEXT: ptrue p0.b210; CHECK-NEXT: cmpge p0.b, p0/z, z0.b, z1.b211; CHECK-NEXT: ret212 %out = icmp sge <vscale x 16 x i8> %a, %b213 ret <vscale x 16 x i1> %out214}215 216define <vscale x 8 x i1> @cmpge_ir_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {217; CHECK-LABEL: cmpge_ir_h:218; CHECK: // %bb.0:219; CHECK-NEXT: ptrue p0.h220; CHECK-NEXT: cmpge p0.h, p0/z, z0.h, z1.h221; CHECK-NEXT: ret222 %out = icmp sge <vscale x 8 x i16> %a, %b223 ret <vscale x 8 x i1> %out224}225 226define <vscale x 4 x i1> @cmpge_ir_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {227; CHECK-LABEL: cmpge_ir_s:228; CHECK: // %bb.0:229; CHECK-NEXT: ptrue p0.s230; CHECK-NEXT: cmpge p0.s, p0/z, z0.s, z1.s231; CHECK-NEXT: ret232 %out = icmp sge <vscale x 4 x i32> %a, %b233 ret <vscale x 4 x i1> %out234}235 236define <vscale x 2 x i1> @cmpge_ir_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {237; CHECK-LABEL: cmpge_ir_d:238; CHECK: // %bb.0:239; CHECK-NEXT: ptrue p0.d240; CHECK-NEXT: cmpge p0.d, p0/z, z0.d, z1.d241; CHECK-NEXT: ret242 %out = icmp sge <vscale x 2 x i64> %a, %b243 ret <vscale x 2 x i1> %out244}245 246define <vscale x 16 x i1> @cmpge_ir_comm_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {247; CHECK-LABEL: cmpge_ir_comm_b:248; CHECK: // %bb.0:249; CHECK-NEXT: ptrue p0.b250; CHECK-NEXT: cmpge p0.b, p0/z, z1.b, z0.b251; CHECK-NEXT: ret252 %out = icmp sle <vscale x 16 x i8> %a, %b253 ret <vscale x 16 x i1> %out254}255 256define <vscale x 8 x i1> @cmpge_ir_comm_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {257; CHECK-LABEL: cmpge_ir_comm_h:258; CHECK: // %bb.0:259; CHECK-NEXT: ptrue p0.h260; CHECK-NEXT: cmpge p0.h, p0/z, z1.h, z0.h261; CHECK-NEXT: ret262 %out = icmp sle <vscale x 8 x i16> %a, %b263 ret <vscale x 8 x i1> %out264}265 266define <vscale x 4 x i1> @cmpge_ir_comm_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {267; CHECK-LABEL: cmpge_ir_comm_s:268; CHECK: // %bb.0:269; CHECK-NEXT: ptrue p0.s270; CHECK-NEXT: cmpge p0.s, p0/z, z1.s, z0.s271; CHECK-NEXT: ret272 %out = icmp sle <vscale x 4 x i32> %a, %b273 ret <vscale x 4 x i1> %out274}275 276define <vscale x 2 x i1> @cmpge_ir_comm_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {277; CHECK-LABEL: cmpge_ir_comm_d:278; CHECK: // %bb.0:279; CHECK-NEXT: ptrue p0.d280; CHECK-NEXT: cmpge p0.d, p0/z, z1.d, z0.d281; CHECK-NEXT: ret282 %out = icmp sle <vscale x 2 x i64> %a, %b283 ret <vscale x 2 x i1> %out284}285 286;287; CMPGT288;289 290define <vscale x 16 x i1> @cmpgt_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {291; CHECK-LABEL: cmpgt_b:292; CHECK: // %bb.0:293; CHECK-NEXT: cmpgt p0.b, p0/z, z0.b, z1.b294; CHECK-NEXT: ret295 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1> %pg,296 <vscale x 16 x i8> %a,297 <vscale x 16 x i8> %b)298 ret <vscale x 16 x i1> %out299}300 301define <vscale x 8 x i1> @cmpgt_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {302; CHECK-LABEL: cmpgt_h:303; CHECK: // %bb.0:304; CHECK-NEXT: cmpgt p0.h, p0/z, z0.h, z1.h305; CHECK-NEXT: ret306 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1> %pg,307 <vscale x 8 x i16> %a,308 <vscale x 8 x i16> %b)309 ret <vscale x 8 x i1> %out310}311 312define <vscale x 4 x i1> @cmpgt_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {313; CHECK-LABEL: cmpgt_s:314; CHECK: // %bb.0:315; CHECK-NEXT: cmpgt p0.s, p0/z, z0.s, z1.s316; CHECK-NEXT: ret317 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1> %pg,318 <vscale x 4 x i32> %a,319 <vscale x 4 x i32> %b)320 ret <vscale x 4 x i1> %out321}322 323define <vscale x 2 x i1> @cmpgt_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {324; CHECK-LABEL: cmpgt_d:325; CHECK: // %bb.0:326; CHECK-NEXT: cmpgt p0.d, p0/z, z0.d, z1.d327; CHECK-NEXT: ret328 %out = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1> %pg,329 <vscale x 2 x i64> %a,330 <vscale x 2 x i64> %b)331 ret <vscale x 2 x i1> %out332}333 334define <vscale x 16 x i1> @cmpgt_wide_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {335; CHECK-LABEL: cmpgt_wide_b:336; CHECK: // %bb.0:337; CHECK-NEXT: cmpgt p0.b, p0/z, z0.b, z1.d338; CHECK-NEXT: ret339 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv16i8(<vscale x 16 x i1> %pg,340 <vscale x 16 x i8> %a,341 <vscale x 2 x i64> %b)342 ret <vscale x 16 x i1> %out343}344 345define <vscale x 8 x i1> @cmpgt_wide_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {346; CHECK-LABEL: cmpgt_wide_h:347; CHECK: // %bb.0:348; CHECK-NEXT: cmpgt p0.h, p0/z, z0.h, z1.d349; CHECK-NEXT: ret350 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv8i16(<vscale x 8 x i1> %pg,351 <vscale x 8 x i16> %a,352 <vscale x 2 x i64> %b)353 ret <vscale x 8 x i1> %out354}355 356define <vscale x 4 x i1> @cmpgt_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {357; CHECK-LABEL: cmpgt_wide_s:358; CHECK: // %bb.0:359; CHECK-NEXT: cmpgt p0.s, p0/z, z0.s, z1.d360; CHECK-NEXT: ret361 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv4i32(<vscale x 4 x i1> %pg,362 <vscale x 4 x i32> %a,363 <vscale x 2 x i64> %b)364 ret <vscale x 4 x i1> %out365}366 367define <vscale x 16 x i1> @cmpgt_ir_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {368; CHECK-LABEL: cmpgt_ir_b:369; CHECK: // %bb.0:370; CHECK-NEXT: ptrue p0.b371; CHECK-NEXT: cmpgt p0.b, p0/z, z0.b, z1.b372; CHECK-NEXT: ret373 %out = icmp sgt <vscale x 16 x i8> %a, %b374 ret <vscale x 16 x i1> %out375}376 377define <vscale x 8 x i1> @cmpgt_ir_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {378; CHECK-LABEL: cmpgt_ir_h:379; CHECK: // %bb.0:380; CHECK-NEXT: ptrue p0.h381; CHECK-NEXT: cmpgt p0.h, p0/z, z0.h, z1.h382; CHECK-NEXT: ret383 %out = icmp sgt <vscale x 8 x i16> %a, %b384 ret <vscale x 8 x i1> %out385}386 387define <vscale x 4 x i1> @cmpgt_ir_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {388; CHECK-LABEL: cmpgt_ir_s:389; CHECK: // %bb.0:390; CHECK-NEXT: ptrue p0.s391; CHECK-NEXT: cmpgt p0.s, p0/z, z0.s, z1.s392; CHECK-NEXT: ret393 %out = icmp sgt <vscale x 4 x i32> %a, %b394 ret <vscale x 4 x i1> %out395}396 397define <vscale x 2 x i1> @cmpgt_ir_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {398; CHECK-LABEL: cmpgt_ir_d:399; CHECK: // %bb.0:400; CHECK-NEXT: ptrue p0.d401; CHECK-NEXT: cmpgt p0.d, p0/z, z0.d, z1.d402; CHECK-NEXT: ret403 %out = icmp sgt <vscale x 2 x i64> %a, %b404 ret <vscale x 2 x i1> %out405}406 407define <vscale x 16 x i1> @cmpgt_ir_comm_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {408; CHECK-LABEL: cmpgt_ir_comm_b:409; CHECK: // %bb.0:410; CHECK-NEXT: ptrue p0.b411; CHECK-NEXT: cmpgt p0.b, p0/z, z1.b, z0.b412; CHECK-NEXT: ret413 %out = icmp slt <vscale x 16 x i8> %a, %b414 ret <vscale x 16 x i1> %out415}416 417define <vscale x 8 x i1> @cmpgt_ir_comm_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {418; CHECK-LABEL: cmpgt_ir_comm_h:419; CHECK: // %bb.0:420; CHECK-NEXT: ptrue p0.h421; CHECK-NEXT: cmpgt p0.h, p0/z, z1.h, z0.h422; CHECK-NEXT: ret423 %out = icmp slt <vscale x 8 x i16> %a, %b424 ret <vscale x 8 x i1> %out425}426 427define <vscale x 4 x i1> @cmpgt_ir_comm_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {428; CHECK-LABEL: cmpgt_ir_comm_s:429; CHECK: // %bb.0:430; CHECK-NEXT: ptrue p0.s431; CHECK-NEXT: cmpgt p0.s, p0/z, z1.s, z0.s432; CHECK-NEXT: ret433 %out = icmp slt <vscale x 4 x i32> %a, %b434 ret <vscale x 4 x i1> %out435}436 437define <vscale x 2 x i1> @cmpgt_ir_comm_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {438; CHECK-LABEL: cmpgt_ir_comm_d:439; CHECK: // %bb.0:440; CHECK-NEXT: ptrue p0.d441; CHECK-NEXT: cmpgt p0.d, p0/z, z1.d, z0.d442; CHECK-NEXT: ret443 %out = icmp slt <vscale x 2 x i64> %a, %b444 ret <vscale x 2 x i1> %out445}446 447;448; CMPHI449;450 451define <vscale x 16 x i1> @cmphi_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {452; CHECK-LABEL: cmphi_b:453; CHECK: // %bb.0:454; CHECK-NEXT: cmphi p0.b, p0/z, z0.b, z1.b455; CHECK-NEXT: ret456 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1> %pg,457 <vscale x 16 x i8> %a,458 <vscale x 16 x i8> %b)459 ret <vscale x 16 x i1> %out460}461 462define <vscale x 8 x i1> @cmphi_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {463; CHECK-LABEL: cmphi_h:464; CHECK: // %bb.0:465; CHECK-NEXT: cmphi p0.h, p0/z, z0.h, z1.h466; CHECK-NEXT: ret467 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1> %pg,468 <vscale x 8 x i16> %a,469 <vscale x 8 x i16> %b)470 ret <vscale x 8 x i1> %out471}472 473define <vscale x 4 x i1> @cmphi_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {474; CHECK-LABEL: cmphi_s:475; CHECK: // %bb.0:476; CHECK-NEXT: cmphi p0.s, p0/z, z0.s, z1.s477; CHECK-NEXT: ret478 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1> %pg,479 <vscale x 4 x i32> %a,480 <vscale x 4 x i32> %b)481 ret <vscale x 4 x i1> %out482}483 484define <vscale x 2 x i1> @cmphi_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {485; CHECK-LABEL: cmphi_d:486; CHECK: // %bb.0:487; CHECK-NEXT: cmphi p0.d, p0/z, z0.d, z1.d488; CHECK-NEXT: ret489 %out = call <vscale x 2 x i1> @llvm.aarch64.sve.cmphi.nxv2i64(<vscale x 2 x i1> %pg,490 <vscale x 2 x i64> %a,491 <vscale x 2 x i64> %b)492 ret <vscale x 2 x i1> %out493}494 495define <vscale x 16 x i1> @cmphi_wide_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {496; CHECK-LABEL: cmphi_wide_b:497; CHECK: // %bb.0:498; CHECK-NEXT: cmphi p0.b, p0/z, z0.b, z1.d499; CHECK-NEXT: ret500 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.wide.nxv16i8(<vscale x 16 x i1> %pg,501 <vscale x 16 x i8> %a,502 <vscale x 2 x i64> %b)503 ret <vscale x 16 x i1> %out504}505 506define <vscale x 8 x i1> @cmphi_wide_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {507; CHECK-LABEL: cmphi_wide_h:508; CHECK: // %bb.0:509; CHECK-NEXT: cmphi p0.h, p0/z, z0.h, z1.d510; CHECK-NEXT: ret511 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.wide.nxv8i16(<vscale x 8 x i1> %pg,512 <vscale x 8 x i16> %a,513 <vscale x 2 x i64> %b)514 ret <vscale x 8 x i1> %out515}516 517define <vscale x 4 x i1> @cmphi_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {518; CHECK-LABEL: cmphi_wide_s:519; CHECK: // %bb.0:520; CHECK-NEXT: cmphi p0.s, p0/z, z0.s, z1.d521; CHECK-NEXT: ret522 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.wide.nxv4i32(<vscale x 4 x i1> %pg,523 <vscale x 4 x i32> %a,524 <vscale x 2 x i64> %b)525 ret <vscale x 4 x i1> %out526}527 528define <vscale x 16 x i1> @cmphi_ir_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {529; CHECK-LABEL: cmphi_ir_b:530; CHECK: // %bb.0:531; CHECK-NEXT: ptrue p0.b532; CHECK-NEXT: cmphi p0.b, p0/z, z0.b, z1.b533; CHECK-NEXT: ret534 %out = icmp ugt <vscale x 16 x i8> %a, %b535 ret <vscale x 16 x i1> %out536}537 538define <vscale x 8 x i1> @cmphi_ir_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {539; CHECK-LABEL: cmphi_ir_h:540; CHECK: // %bb.0:541; CHECK-NEXT: ptrue p0.h542; CHECK-NEXT: cmphi p0.h, p0/z, z0.h, z1.h543; CHECK-NEXT: ret544 %out = icmp ugt <vscale x 8 x i16> %a, %b545 ret <vscale x 8 x i1> %out546}547 548define <vscale x 4 x i1> @cmphi_ir_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {549; CHECK-LABEL: cmphi_ir_s:550; CHECK: // %bb.0:551; CHECK-NEXT: ptrue p0.s552; CHECK-NEXT: cmphi p0.s, p0/z, z0.s, z1.s553; CHECK-NEXT: ret554 %out = icmp ugt <vscale x 4 x i32> %a, %b555 ret <vscale x 4 x i1> %out556}557 558define <vscale x 2 x i1> @cmphi_ir_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {559; CHECK-LABEL: cmphi_ir_d:560; CHECK: // %bb.0:561; CHECK-NEXT: ptrue p0.d562; CHECK-NEXT: cmphi p0.d, p0/z, z0.d, z1.d563; CHECK-NEXT: ret564 %out = icmp ugt <vscale x 2 x i64> %a, %b565 ret <vscale x 2 x i1> %out566}567 568define <vscale x 16 x i1> @cmphi_ir_comm_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {569; CHECK-LABEL: cmphi_ir_comm_b:570; CHECK: // %bb.0:571; CHECK-NEXT: ptrue p0.b572; CHECK-NEXT: cmphi p0.b, p0/z, z1.b, z0.b573; CHECK-NEXT: ret574 %out = icmp ult <vscale x 16 x i8> %a, %b575 ret <vscale x 16 x i1> %out576}577 578define <vscale x 8 x i1> @cmphi_ir_comm_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {579; CHECK-LABEL: cmphi_ir_comm_h:580; CHECK: // %bb.0:581; CHECK-NEXT: ptrue p0.h582; CHECK-NEXT: cmphi p0.h, p0/z, z1.h, z0.h583; CHECK-NEXT: ret584 %out = icmp ult <vscale x 8 x i16> %a, %b585 ret <vscale x 8 x i1> %out586}587 588define <vscale x 4 x i1> @cmphi_ir_comm_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {589; CHECK-LABEL: cmphi_ir_comm_s:590; CHECK: // %bb.0:591; CHECK-NEXT: ptrue p0.s592; CHECK-NEXT: cmphi p0.s, p0/z, z1.s, z0.s593; CHECK-NEXT: ret594 %out = icmp ult <vscale x 4 x i32> %a, %b595 ret <vscale x 4 x i1> %out596}597 598define <vscale x 2 x i1> @cmphi_ir_comm_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {599; CHECK-LABEL: cmphi_ir_comm_d:600; CHECK: // %bb.0:601; CHECK-NEXT: ptrue p0.d602; CHECK-NEXT: cmphi p0.d, p0/z, z1.d, z0.d603; CHECK-NEXT: ret604 %out = icmp ult <vscale x 2 x i64> %a, %b605 ret <vscale x 2 x i1> %out606}607 608;609; CMPHS610;611 612define <vscale x 16 x i1> @cmphs_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {613; CHECK-LABEL: cmphs_b:614; CHECK: // %bb.0:615; CHECK-NEXT: cmphs p0.b, p0/z, z0.b, z1.b616; CHECK-NEXT: ret617 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1> %pg,618 <vscale x 16 x i8> %a,619 <vscale x 16 x i8> %b)620 ret <vscale x 16 x i1> %out621}622 623define <vscale x 8 x i1> @cmphs_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {624; CHECK-LABEL: cmphs_h:625; CHECK: // %bb.0:626; CHECK-NEXT: cmphs p0.h, p0/z, z0.h, z1.h627; CHECK-NEXT: ret628 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1> %pg,629 <vscale x 8 x i16> %a,630 <vscale x 8 x i16> %b)631 ret <vscale x 8 x i1> %out632}633 634define <vscale x 4 x i1> @cmphs_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {635; CHECK-LABEL: cmphs_s:636; CHECK: // %bb.0:637; CHECK-NEXT: cmphs p0.s, p0/z, z0.s, z1.s638; CHECK-NEXT: ret639 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1> %pg,640 <vscale x 4 x i32> %a,641 <vscale x 4 x i32> %b)642 ret <vscale x 4 x i1> %out643}644 645define <vscale x 2 x i1> @cmphs_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {646; CHECK-LABEL: cmphs_d:647; CHECK: // %bb.0:648; CHECK-NEXT: cmphs p0.d, p0/z, z0.d, z1.d649; CHECK-NEXT: ret650 %out = call <vscale x 2 x i1> @llvm.aarch64.sve.cmphs.nxv2i64(<vscale x 2 x i1> %pg,651 <vscale x 2 x i64> %a,652 <vscale x 2 x i64> %b)653 ret <vscale x 2 x i1> %out654}655 656define <vscale x 16 x i1> @cmphs_wide_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {657; CHECK-LABEL: cmphs_wide_b:658; CHECK: // %bb.0:659; CHECK-NEXT: cmphs p0.b, p0/z, z0.b, z1.d660; CHECK-NEXT: ret661 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.wide.nxv16i8(<vscale x 16 x i1> %pg,662 <vscale x 16 x i8> %a,663 <vscale x 2 x i64> %b)664 ret <vscale x 16 x i1> %out665}666 667define <vscale x 8 x i1> @cmphs_wide_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {668; CHECK-LABEL: cmphs_wide_h:669; CHECK: // %bb.0:670; CHECK-NEXT: cmphs p0.h, p0/z, z0.h, z1.d671; CHECK-NEXT: ret672 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.wide.nxv8i16(<vscale x 8 x i1> %pg,673 <vscale x 8 x i16> %a,674 <vscale x 2 x i64> %b)675 ret <vscale x 8 x i1> %out676}677 678define <vscale x 4 x i1> @cmphs_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {679; CHECK-LABEL: cmphs_wide_s:680; CHECK: // %bb.0:681; CHECK-NEXT: cmphs p0.s, p0/z, z0.s, z1.d682; CHECK-NEXT: ret683 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.wide.nxv4i32(<vscale x 4 x i1> %pg,684 <vscale x 4 x i32> %a,685 <vscale x 2 x i64> %b)686 ret <vscale x 4 x i1> %out687}688 689define <vscale x 16 x i1> @cmphs_ir_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {690; CHECK-LABEL: cmphs_ir_b:691; CHECK: // %bb.0:692; CHECK-NEXT: ptrue p0.b693; CHECK-NEXT: cmphs p0.b, p0/z, z0.b, z1.b694; CHECK-NEXT: ret695 %out = icmp uge <vscale x 16 x i8> %a, %b696 ret <vscale x 16 x i1> %out697}698 699define <vscale x 8 x i1> @cmphs_ir_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {700; CHECK-LABEL: cmphs_ir_h:701; CHECK: // %bb.0:702; CHECK-NEXT: ptrue p0.h703; CHECK-NEXT: cmphs p0.h, p0/z, z0.h, z1.h704; CHECK-NEXT: ret705 %out = icmp uge <vscale x 8 x i16> %a, %b706 ret <vscale x 8 x i1> %out707}708 709define <vscale x 4 x i1> @cmphs_ir_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {710; CHECK-LABEL: cmphs_ir_s:711; CHECK: // %bb.0:712; CHECK-NEXT: ptrue p0.s713; CHECK-NEXT: cmphs p0.s, p0/z, z0.s, z1.s714; CHECK-NEXT: ret715 %out = icmp uge <vscale x 4 x i32> %a, %b716 ret <vscale x 4 x i1> %out717}718 719define <vscale x 2 x i1> @cmphs_ir_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {720; CHECK-LABEL: cmphs_ir_d:721; CHECK: // %bb.0:722; CHECK-NEXT: ptrue p0.d723; CHECK-NEXT: cmphs p0.d, p0/z, z0.d, z1.d724; CHECK-NEXT: ret725 %out = icmp uge <vscale x 2 x i64> %a, %b726 ret <vscale x 2 x i1> %out727}728 729define <vscale x 16 x i1> @cmphs_ir_comm_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {730; CHECK-LABEL: cmphs_ir_comm_b:731; CHECK: // %bb.0:732; CHECK-NEXT: ptrue p0.b733; CHECK-NEXT: cmphs p0.b, p0/z, z1.b, z0.b734; CHECK-NEXT: ret735 %out = icmp ule <vscale x 16 x i8> %a, %b736 ret <vscale x 16 x i1> %out737}738 739define <vscale x 8 x i1> @cmphs_ir_comm_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {740; CHECK-LABEL: cmphs_ir_comm_h:741; CHECK: // %bb.0:742; CHECK-NEXT: ptrue p0.h743; CHECK-NEXT: cmphs p0.h, p0/z, z1.h, z0.h744; CHECK-NEXT: ret745 %out = icmp ule <vscale x 8 x i16> %a, %b746 ret <vscale x 8 x i1> %out747}748 749define <vscale x 4 x i1> @cmphs_ir_comm_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {750; CHECK-LABEL: cmphs_ir_comm_s:751; CHECK: // %bb.0:752; CHECK-NEXT: ptrue p0.s753; CHECK-NEXT: cmphs p0.s, p0/z, z1.s, z0.s754; CHECK-NEXT: ret755 %out = icmp ule <vscale x 4 x i32> %a, %b756 ret <vscale x 4 x i1> %out757}758 759define <vscale x 2 x i1> @cmphs_ir_comm_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {760; CHECK-LABEL: cmphs_ir_comm_d:761; CHECK: // %bb.0:762; CHECK-NEXT: ptrue p0.d763; CHECK-NEXT: cmphs p0.d, p0/z, z1.d, z0.d764; CHECK-NEXT: ret765 %out = icmp ule <vscale x 2 x i64> %a, %b766 ret <vscale x 2 x i1> %out767}768 769;770; CMPLE771;772 773define <vscale x 16 x i1> @cmple_wide_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {774; CHECK-LABEL: cmple_wide_b:775; CHECK: // %bb.0:776; CHECK-NEXT: cmple p0.b, p0/z, z0.b, z1.d777; CHECK-NEXT: ret778 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmple.wide.nxv16i8(<vscale x 16 x i1> %pg,779 <vscale x 16 x i8> %a,780 <vscale x 2 x i64> %b)781 ret <vscale x 16 x i1> %out782}783 784define <vscale x 8 x i1> @cmple_wide_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {785; CHECK-LABEL: cmple_wide_h:786; CHECK: // %bb.0:787; CHECK-NEXT: cmple p0.h, p0/z, z0.h, z1.d788; CHECK-NEXT: ret789 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmple.wide.nxv8i16(<vscale x 8 x i1> %pg,790 <vscale x 8 x i16> %a,791 <vscale x 2 x i64> %b)792 ret <vscale x 8 x i1> %out793}794 795define <vscale x 4 x i1> @cmple_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {796; CHECK-LABEL: cmple_wide_s:797; CHECK: // %bb.0:798; CHECK-NEXT: cmple p0.s, p0/z, z0.s, z1.d799; CHECK-NEXT: ret800 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmple.wide.nxv4i32(<vscale x 4 x i1> %pg,801 <vscale x 4 x i32> %a,802 <vscale x 2 x i64> %b)803 ret <vscale x 4 x i1> %out804}805 806;807; CMPLO808;809 810define <vscale x 16 x i1> @cmplo_wide_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {811; CHECK-LABEL: cmplo_wide_b:812; CHECK: // %bb.0:813; CHECK-NEXT: cmplo p0.b, p0/z, z0.b, z1.d814; CHECK-NEXT: ret815 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmplo.wide.nxv16i8(<vscale x 16 x i1> %pg,816 <vscale x 16 x i8> %a,817 <vscale x 2 x i64> %b)818 ret <vscale x 16 x i1> %out819}820 821define <vscale x 8 x i1> @cmplo_wide_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {822; CHECK-LABEL: cmplo_wide_h:823; CHECK: // %bb.0:824; CHECK-NEXT: cmplo p0.h, p0/z, z0.h, z1.d825; CHECK-NEXT: ret826 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmplo.wide.nxv8i16(<vscale x 8 x i1> %pg,827 <vscale x 8 x i16> %a,828 <vscale x 2 x i64> %b)829 ret <vscale x 8 x i1> %out830}831 832define <vscale x 4 x i1> @cmplo_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {833; CHECK-LABEL: cmplo_wide_s:834; CHECK: // %bb.0:835; CHECK-NEXT: cmplo p0.s, p0/z, z0.s, z1.d836; CHECK-NEXT: ret837 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmplo.wide.nxv4i32(<vscale x 4 x i1> %pg,838 <vscale x 4 x i32> %a,839 <vscale x 2 x i64> %b)840 ret <vscale x 4 x i1> %out841}842 843;844; CMPLS845;846 847define <vscale x 16 x i1> @cmpls_wide_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {848; CHECK-LABEL: cmpls_wide_b:849; CHECK: // %bb.0:850; CHECK-NEXT: cmpls p0.b, p0/z, z0.b, z1.d851; CHECK-NEXT: ret852 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpls.wide.nxv16i8(<vscale x 16 x i1> %pg,853 <vscale x 16 x i8> %a,854 <vscale x 2 x i64> %b)855 ret <vscale x 16 x i1> %out856}857 858define <vscale x 8 x i1> @cmpls_wide_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {859; CHECK-LABEL: cmpls_wide_h:860; CHECK: // %bb.0:861; CHECK-NEXT: cmpls p0.h, p0/z, z0.h, z1.d862; CHECK-NEXT: ret863 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpls.wide.nxv8i16(<vscale x 8 x i1> %pg,864 <vscale x 8 x i16> %a,865 <vscale x 2 x i64> %b)866 ret <vscale x 8 x i1> %out867}868 869define <vscale x 4 x i1> @cmpls_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {870; CHECK-LABEL: cmpls_wide_s:871; CHECK: // %bb.0:872; CHECK-NEXT: cmpls p0.s, p0/z, z0.s, z1.d873; CHECK-NEXT: ret874 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpls.wide.nxv4i32(<vscale x 4 x i1> %pg,875 <vscale x 4 x i32> %a,876 <vscale x 2 x i64> %b)877 ret <vscale x 4 x i1> %out878}879 880;881; CMPLT882;883 884define <vscale x 16 x i1> @cmplt_wide_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {885; CHECK-LABEL: cmplt_wide_b:886; CHECK: // %bb.0:887; CHECK-NEXT: cmplt p0.b, p0/z, z0.b, z1.d888; CHECK-NEXT: ret889 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmplt.wide.nxv16i8(<vscale x 16 x i1> %pg,890 <vscale x 16 x i8> %a,891 <vscale x 2 x i64> %b)892 ret <vscale x 16 x i1> %out893}894 895define <vscale x 8 x i1> @cmplt_wide_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {896; CHECK-LABEL: cmplt_wide_h:897; CHECK: // %bb.0:898; CHECK-NEXT: cmplt p0.h, p0/z, z0.h, z1.d899; CHECK-NEXT: ret900 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmplt.wide.nxv8i16(<vscale x 8 x i1> %pg,901 <vscale x 8 x i16> %a,902 <vscale x 2 x i64> %b)903 ret <vscale x 8 x i1> %out904}905 906define <vscale x 4 x i1> @cmplt_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {907; CHECK-LABEL: cmplt_wide_s:908; CHECK: // %bb.0:909; CHECK-NEXT: cmplt p0.s, p0/z, z0.s, z1.d910; CHECK-NEXT: ret911 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmplt.wide.nxv4i32(<vscale x 4 x i1> %pg,912 <vscale x 4 x i32> %a,913 <vscale x 2 x i64> %b)914 ret <vscale x 4 x i1> %out915}916 917;918; CMPNE919;920 921define <vscale x 16 x i1> @cmpne_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {922; CHECK-LABEL: cmpne_b:923; CHECK: // %bb.0:924; CHECK-NEXT: cmpne p0.b, p0/z, z0.b, z1.b925; CHECK-NEXT: ret926 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1> %pg,927 <vscale x 16 x i8> %a,928 <vscale x 16 x i8> %b)929 ret <vscale x 16 x i1> %out930}931 932define <vscale x 8 x i1> @cmpne_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {933; CHECK-LABEL: cmpne_h:934; CHECK: // %bb.0:935; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, z1.h936; CHECK-NEXT: ret937 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %pg,938 <vscale x 8 x i16> %a,939 <vscale x 8 x i16> %b)940 ret <vscale x 8 x i1> %out941}942 943define <vscale x 4 x i1> @cmpne_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {944; CHECK-LABEL: cmpne_s:945; CHECK: // %bb.0:946; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, z1.s947; CHECK-NEXT: ret948 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %pg,949 <vscale x 4 x i32> %a,950 <vscale x 4 x i32> %b)951 ret <vscale x 4 x i1> %out952}953 954define <vscale x 2 x i1> @cmpne_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {955; CHECK-LABEL: cmpne_d:956; CHECK: // %bb.0:957; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, z1.d958; CHECK-NEXT: ret959 %out = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %pg,960 <vscale x 2 x i64> %a,961 <vscale x 2 x i64> %b)962 ret <vscale x 2 x i1> %out963}964 965define <vscale x 16 x i1> @cmpne_wide_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {966; CHECK-LABEL: cmpne_wide_b:967; CHECK: // %bb.0:968; CHECK-NEXT: cmpne p0.b, p0/z, z0.b, z1.d969; CHECK-NEXT: ret970 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1> %pg,971 <vscale x 16 x i8> %a,972 <vscale x 2 x i64> %b)973 ret <vscale x 16 x i1> %out974}975 976define <vscale x 8 x i1> @cmpne_wide_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {977; CHECK-LABEL: cmpne_wide_h:978; CHECK: // %bb.0:979; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, z1.d980; CHECK-NEXT: ret981 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.wide.nxv8i16(<vscale x 8 x i1> %pg,982 <vscale x 8 x i16> %a,983 <vscale x 2 x i64> %b)984 ret <vscale x 8 x i1> %out985}986 987define <vscale x 4 x i1> @cmpne_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {988; CHECK-LABEL: cmpne_wide_s:989; CHECK: // %bb.0:990; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, z1.d991; CHECK-NEXT: ret992 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1> %pg,993 <vscale x 4 x i32> %a,994 <vscale x 2 x i64> %b)995 ret <vscale x 4 x i1> %out996}997 998define <vscale x 16 x i1> @cmpne_ir_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {999; CHECK-LABEL: cmpne_ir_b:1000; CHECK: // %bb.0:1001; CHECK-NEXT: ptrue p0.b1002; CHECK-NEXT: cmpne p0.b, p0/z, z0.b, z1.b1003; CHECK-NEXT: ret1004 %out = icmp ne <vscale x 16 x i8> %a, %b1005 ret <vscale x 16 x i1> %out1006}1007 1008define <vscale x 8 x i1> @cmpne_ir_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {1009; CHECK-LABEL: cmpne_ir_h:1010; CHECK: // %bb.0:1011; CHECK-NEXT: ptrue p0.h1012; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, z1.h1013; CHECK-NEXT: ret1014 %out = icmp ne <vscale x 8 x i16> %a, %b1015 ret <vscale x 8 x i1> %out1016}1017 1018define <vscale x 4 x i1> @cmpne_ir_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {1019; CHECK-LABEL: cmpne_ir_s:1020; CHECK: // %bb.0:1021; CHECK-NEXT: ptrue p0.s1022; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, z1.s1023; CHECK-NEXT: ret1024 %out = icmp ne <vscale x 4 x i32> %a, %b1025 ret <vscale x 4 x i1> %out1026}1027 1028define <vscale x 2 x i1> @cmpne_ir_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {1029; CHECK-LABEL: cmpne_ir_d:1030; CHECK: // %bb.0:1031; CHECK-NEXT: ptrue p0.d1032; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, z1.d1033; CHECK-NEXT: ret1034 %out = icmp ne <vscale x 2 x i64> %a, %b1035 ret <vscale x 2 x i1> %out1036}1037 1038define <vscale x 1 x i1> @cmpne_ir_q(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) {1039; CHECK-LABEL: cmpne_ir_q:1040; CHECK: // %bb.0:1041; CHECK-NEXT: ptrue p0.d1042; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, z1.d1043; CHECK-NEXT: punpklo p0.h, p0.b1044; CHECK-NEXT: ret1045 %out = icmp ne <vscale x 1 x i64> %a, %b1046 ret <vscale x 1 x i1> %out1047}1048 1049 1050define <vscale x 16 x i1> @cmpgt_wide_splat_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, i64 %b) {1051; CHECK-LABEL: cmpgt_wide_splat_b:1052; CHECK: // %bb.0:1053; CHECK-NEXT: mov z1.d, x01054; CHECK-NEXT: cmpgt p0.b, p0/z, z0.b, z1.d1055; CHECK-NEXT: ret1056 %splat = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %b)1057 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv16i8(<vscale x 16 x i1> %pg,1058 <vscale x 16 x i8> %a,1059 <vscale x 2 x i64> %splat)1060 ret <vscale x 16 x i1> %out1061}1062 1063define <vscale x 4 x i1> @cmpls_wide_splat_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, i64 %b) {1064; CHECK-LABEL: cmpls_wide_splat_s:1065; CHECK: // %bb.0:1066; CHECK-NEXT: mov z1.d, x01067; CHECK-NEXT: cmpls p0.s, p0/z, z0.s, z1.d1068; CHECK-NEXT: ret1069 %splat = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %b)1070 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpls.wide.nxv4i32(<vscale x 4 x i1> %pg,1071 <vscale x 4 x i32> %a,1072 <vscale x 2 x i64> %splat)1073 ret <vscale x 4 x i1> %out1074}1075 1076; Verify general predicate is folded into the compare1077define <vscale x 4 x i1> @predicated_icmp(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {1078; CHECK-LABEL: predicated_icmp:1079; CHECK: // %bb.0:1080; CHECK-NEXT: ptrue p0.s1081; CHECK-NEXT: cmpgt p0.s, p0/z, z0.s, z1.s1082; CHECK-NEXT: cmpge p0.s, p0/z, z2.s, z1.s1083; CHECK-NEXT: ret1084 %icmp1 = icmp sgt <vscale x 4 x i32> %a, %b1085 %icmp2 = icmp sle <vscale x 4 x i32> %b, %c1086 %and = and <vscale x 4 x i1> %icmp1, %icmp21087 ret <vscale x 4 x i1> %and1088}1089 1090define <vscale x 4 x i1> @predicated_icmp_unknown_lhs(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {1091; CHECK-LABEL: predicated_icmp_unknown_lhs:1092; CHECK: // %bb.0:1093; CHECK-NEXT: cmpge p0.s, p0/z, z1.s, z0.s1094; CHECK-NEXT: ret1095 %icmp = icmp sle <vscale x 4 x i32> %b, %c1096 %and = and <vscale x 4 x i1> %a, %icmp1097 ret <vscale x 4 x i1> %and1098}1099 1100define <vscale x 4 x i1> @predicated_icmp_unknown_rhs(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {1101; CHECK-LABEL: predicated_icmp_unknown_rhs:1102; CHECK: // %bb.0:1103; CHECK-NEXT: cmpge p0.s, p0/z, z1.s, z0.s1104; CHECK-NEXT: ret1105 %icmp = icmp sle <vscale x 4 x i32> %b, %c1106 %and = and <vscale x 4 x i1> %icmp, %a1107 ret <vscale x 4 x i1> %and1108}1109 1110define <vscale x 16 x i1> @predicated_icmp_eq_imm(<vscale x 16 x i1> %a, <vscale x 16 x i8> %b) {1111; CHECK-LABEL: predicated_icmp_eq_imm:1112; CHECK: // %bb.0:1113; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, #01114; CHECK-NEXT: ret1115 %icmp = icmp eq <vscale x 16 x i8> %b, zeroinitializer1116 %and = and <vscale x 16 x i1> %a, %icmp1117 ret <vscale x 16 x i1> %and1118}1119 1120define <vscale x 8 x i1> @predicated_icmp_ne_imm(<vscale x 8 x i1> %a, <vscale x 8 x i16> %b) {1121; CHECK-LABEL: predicated_icmp_ne_imm:1122; CHECK: // %bb.0:1123; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, #-161124; CHECK-NEXT: ret1125 %icmp = icmp ne <vscale x 8 x i16> %b, splat (i16 -16)1126 %and = and <vscale x 8 x i1> %a, %icmp1127 ret <vscale x 8 x i1> %and1128}1129 1130define <vscale x 4 x i1> @predicated_icmp_sge_imm(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b) {1131; CHECK-LABEL: predicated_icmp_sge_imm:1132; CHECK: // %bb.0:1133; CHECK-NEXT: cmpge p0.s, p0/z, z0.s, #11134; CHECK-NEXT: ret1135 %icmp = icmp sge <vscale x 4 x i32> %b, splat (i32 1)1136 %and = and <vscale x 4 x i1> %a, %icmp1137 ret <vscale x 4 x i1> %and1138}1139 1140define <vscale x 2 x i1> @predicated_icmp_sgt_imm(<vscale x 2 x i1> %a, <vscale x 2 x i64> %b) {1141; CHECK-LABEL: predicated_icmp_sgt_imm:1142; CHECK: // %bb.0:1143; CHECK-NEXT: cmpgt p0.d, p0/z, z0.d, #21144; CHECK-NEXT: ret1145 %icmp = icmp sgt <vscale x 2 x i64> %b, splat (i64 2)1146 %and = and <vscale x 2 x i1> %a, %icmp1147 ret <vscale x 2 x i1> %and1148}1149 1150define <vscale x 16 x i1> @predicated_icmp_sle_imm(<vscale x 16 x i1> %a, <vscale x 16 x i8> %b) {1151; CHECK-LABEL: predicated_icmp_sle_imm:1152; CHECK: // %bb.0:1153; CHECK-NEXT: cmple p0.b, p0/z, z0.b, #-11154; CHECK-NEXT: ret1155 %icmp = icmp sle <vscale x 16 x i8> %b, splat (i8 -1)1156 %and = and <vscale x 16 x i1> %a, %icmp1157 ret <vscale x 16 x i1> %and1158}1159 1160define <vscale x 8 x i1> @predicated_icmp_slt_imm(<vscale x 8 x i1> %a, <vscale x 8 x i16> %b) {1161; CHECK-LABEL: predicated_icmp_slt_imm:1162; CHECK: // %bb.0:1163; CHECK-NEXT: cmplt p0.h, p0/z, z0.h, #-21164; CHECK-NEXT: ret1165 %icmp = icmp slt <vscale x 8 x i16> %b, splat (i16 -2)1166 %and = and <vscale x 8 x i1> %a, %icmp1167 ret <vscale x 8 x i1> %and1168}1169 1170define <vscale x 4 x i1> @predicated_icmp_uge_imm(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b) {1171; CHECK-LABEL: predicated_icmp_uge_imm:1172; CHECK: // %bb.0:1173; CHECK-NEXT: cmphs p0.s, p0/z, z0.s, #11174; CHECK-NEXT: ret1175 %icmp = icmp uge <vscale x 4 x i32> %b, splat (i32 1)1176 %and = and <vscale x 4 x i1> %a, %icmp1177 ret <vscale x 4 x i1> %and1178}1179 1180define <vscale x 2 x i1> @predicated_icmp_ugt_imm(<vscale x 2 x i1> %a, <vscale x 2 x i64> %b) {1181; CHECK-LABEL: predicated_icmp_ugt_imm:1182; CHECK: // %bb.0:1183; CHECK-NEXT: cmphi p0.d, p0/z, z0.d, #21184; CHECK-NEXT: ret1185 %icmp = icmp ugt <vscale x 2 x i64> %b, splat (i64 2)1186 %and = and <vscale x 2 x i1> %a, %icmp1187 ret <vscale x 2 x i1> %and1188}1189 1190define <vscale x 16 x i1> @predicated_icmp_ule_imm(<vscale x 16 x i1> %a, <vscale x 16 x i8> %b) {1191; CHECK-LABEL: predicated_icmp_ule_imm:1192; CHECK: // %bb.0:1193; CHECK-NEXT: cmpls p0.b, p0/z, z0.b, #31194; CHECK-NEXT: ret1195 %icmp = icmp ule <vscale x 16 x i8> %b, splat (i8 3)1196 %and = and <vscale x 16 x i1> %a, %icmp1197 ret <vscale x 16 x i1> %and1198}1199 1200define <vscale x 8 x i1> @predicated_icmp_ult_imm(<vscale x 8 x i1> %a, <vscale x 8 x i16> %b) {1201; CHECK-LABEL: predicated_icmp_ult_imm:1202; CHECK: // %bb.0:1203; CHECK-NEXT: cmplo p0.h, p0/z, z0.h, #1271204; CHECK-NEXT: ret1205 %icmp = icmp ult <vscale x 8 x i16> %b, splat (i16 127)1206 %and = and <vscale x 8 x i1> %a, %icmp1207 ret <vscale x 8 x i1> %and1208}1209 1210%svboolx2 = type { <vscale x 4 x i1>, <vscale x 4 x i1> }1211 1212define %svboolx2 @and_of_multiuse_icmp_sle(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {1213; CHECK-LABEL: and_of_multiuse_icmp_sle:1214; CHECK: // %bb.0:1215; CHECK-NEXT: ptrue p1.s1216; CHECK-NEXT: cmpge p1.s, p1/z, z1.s, z0.s1217; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b1218; CHECK-NEXT: ret1219 %cmp = icmp sle <vscale x 4 x i32> %b, %c1220 %and = and <vscale x 4 x i1> %a, %cmp1221 %ins.1 = insertvalue %svboolx2 poison, <vscale x 4 x i1> %and, 01222 %ins.2 = insertvalue %svboolx2 %ins.1, <vscale x 4 x i1> %cmp, 11223 ret %svboolx2 %ins.21224}1225 1226define %svboolx2 @and_of_multiuse_icmp_sle_imm(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b) {1227; CHECK-LABEL: and_of_multiuse_icmp_sle_imm:1228; CHECK: // %bb.0:1229; CHECK-NEXT: ptrue p1.s1230; CHECK-NEXT: cmple p1.s, p1/z, z0.s, #11231; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b1232; CHECK-NEXT: ret1233 %cmp = icmp sle <vscale x 4 x i32> %b, splat (i32 1)1234 %and = and <vscale x 4 x i1> %a, %cmp1235 %ins.1 = insertvalue %svboolx2 poison, <vscale x 4 x i1> %and, 01236 %ins.2 = insertvalue %svboolx2 %ins.1, <vscale x 4 x i1> %cmp, 11237 ret %svboolx2 %ins.21238}1239 1240define %svboolx2 @and_of_multiuse_icmp_ugt(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {1241; CHECK-LABEL: and_of_multiuse_icmp_ugt:1242; CHECK: // %bb.0:1243; CHECK-NEXT: ptrue p1.s1244; CHECK-NEXT: cmphi p1.s, p1/z, z0.s, z1.s1245; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b1246; CHECK-NEXT: ret1247 %cmp = icmp ugt <vscale x 4 x i32> %b, %c1248 %and = and <vscale x 4 x i1> %a, %cmp1249 %ins.1 = insertvalue %svboolx2 poison, <vscale x 4 x i1> %and, 01250 %ins.2 = insertvalue %svboolx2 %ins.1, <vscale x 4 x i1> %cmp, 11251 ret %svboolx2 %ins.21252}1253 1254define %svboolx2 @and_of_multiuse_icmp_ugt_imm(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b) {1255; CHECK-LABEL: and_of_multiuse_icmp_ugt_imm:1256; CHECK: // %bb.0:1257; CHECK-NEXT: ptrue p1.s1258; CHECK-NEXT: cmphi p1.s, p1/z, z0.s, #11259; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b1260; CHECK-NEXT: ret1261 %cmp = icmp ugt <vscale x 4 x i32> %b, splat (i32 1)1262 %and = and <vscale x 4 x i1> %a, %cmp1263 %ins.1 = insertvalue %svboolx2 poison, <vscale x 4 x i1> %and, 01264 %ins.2 = insertvalue %svboolx2 %ins.1, <vscale x 4 x i1> %cmp, 11265 ret %svboolx2 %ins.21266}1267 1268declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1269declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1270declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1271declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpeq.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1272declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)1273declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)1274declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)1275 1276declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1277declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1278declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1279declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1280declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)1281declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)1282declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)1283 1284declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1285declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1286declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1287declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1288declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)1289declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)1290declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)1291 1292declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1293declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1294declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1295declare <vscale x 2 x i1> @llvm.aarch64.sve.cmphi.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1296declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)1297declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)1298declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)1299 1300declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1301declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1302declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1303declare <vscale x 2 x i1> @llvm.aarch64.sve.cmphs.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1304declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)1305declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)1306declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)1307 1308declare <vscale x 16 x i1> @llvm.aarch64.sve.cmple.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)1309declare <vscale x 8 x i1> @llvm.aarch64.sve.cmple.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)1310declare <vscale x 4 x i1> @llvm.aarch64.sve.cmple.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)1311 1312declare <vscale x 16 x i1> @llvm.aarch64.sve.cmplo.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)1313declare <vscale x 8 x i1> @llvm.aarch64.sve.cmplo.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)1314declare <vscale x 4 x i1> @llvm.aarch64.sve.cmplo.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)1315 1316declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpls.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)1317declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpls.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)1318declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpls.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)1319 1320declare <vscale x 16 x i1> @llvm.aarch64.sve.cmplt.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)1321declare <vscale x 8 x i1> @llvm.aarch64.sve.cmplt.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)1322declare <vscale x 4 x i1> @llvm.aarch64.sve.cmplt.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)1323 1324declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)1325declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)1326declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1327declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)1328declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)1329declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)1330declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)1331 1332declare <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64)1333