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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4;5; LD1B6;7 8define <vscale x 16 x i8> @ld1b_i8(<vscale x 16 x i1> %pg, ptr %a, i64 %index) {9; CHECK-LABEL: ld1b_i8:10; CHECK: // %bb.0:11; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0, x1]12; CHECK-NEXT: ret13 %base = getelementptr i8, ptr %a, i64 %index14 %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8(<vscale x 16 x i1> %pg, ptr %base)15 ret <vscale x 16 x i8> %load16}17 18define <vscale x 8 x i16> @ld1b_h(<vscale x 8 x i1> %pred, ptr %a, i64 %index) {19; CHECK-LABEL: ld1b_h:20; CHECK: // %bb.0:21; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0, x1]22; CHECK-NEXT: ret23 %base = getelementptr i8, ptr %a, i64 %index24 %load = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8(<vscale x 8 x i1> %pred, ptr %base)25 %res = zext <vscale x 8 x i8> %load to <vscale x 8 x i16>26 ret <vscale x 8 x i16> %res27}28 29define <vscale x 8 x i16> @ld1sb_h(<vscale x 8 x i1> %pred, ptr %a, i64 %index) {30; CHECK-LABEL: ld1sb_h:31; CHECK: // %bb.0:32; CHECK-NEXT: ld1sb { z0.h }, p0/z, [x0, x1]33; CHECK-NEXT: ret34 %base = getelementptr i8, ptr %a, i64 %index35 %load = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8(<vscale x 8 x i1> %pred, ptr %base)36 %res = sext <vscale x 8 x i8> %load to <vscale x 8 x i16>37 ret <vscale x 8 x i16> %res38}39 40define <vscale x 4 x i32> @ld1b_s(<vscale x 4 x i1> %pred, ptr %a, i64 %index) {41; CHECK-LABEL: ld1b_s:42; CHECK: // %bb.0:43; CHECK-NEXT: ld1b { z0.s }, p0/z, [x0, x1]44; CHECK-NEXT: ret45 %base = getelementptr i8, ptr %a, i64 %index46 %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8(<vscale x 4 x i1> %pred, ptr %base)47 %res = zext <vscale x 4 x i8> %load to <vscale x 4 x i32>48 ret <vscale x 4 x i32> %res49}50 51define <vscale x 4 x i32> @ld1sb_s(<vscale x 4 x i1> %pred, ptr %a, i64 %index) {52; CHECK-LABEL: ld1sb_s:53; CHECK: // %bb.0:54; CHECK-NEXT: ld1sb { z0.s }, p0/z, [x0, x1]55; CHECK-NEXT: ret56 %base = getelementptr i8, ptr %a, i64 %index57 %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8(<vscale x 4 x i1> %pred, ptr %base)58 %res = sext <vscale x 4 x i8> %load to <vscale x 4 x i32>59 ret <vscale x 4 x i32> %res60}61 62define <vscale x 2 x i64> @ld1b_d(<vscale x 2 x i1> %pred, ptr %a, i64 %index) {63; CHECK-LABEL: ld1b_d:64; CHECK: // %bb.0:65; CHECK-NEXT: ld1b { z0.d }, p0/z, [x0, x1]66; CHECK-NEXT: ret67 %base = getelementptr i8, ptr %a, i64 %index68 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8(<vscale x 2 x i1> %pred, ptr %base)69 %res = zext <vscale x 2 x i8> %load to <vscale x 2 x i64>70 ret <vscale x 2 x i64> %res71}72 73define <vscale x 2 x i64> @ld1sb_d(<vscale x 2 x i1> %pred, ptr %a, i64 %index) {74; CHECK-LABEL: ld1sb_d:75; CHECK: // %bb.0:76; CHECK-NEXT: ld1sb { z0.d }, p0/z, [x0, x1]77; CHECK-NEXT: ret78 %base = getelementptr i8, ptr %a, i64 %index79 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8(<vscale x 2 x i1> %pred, ptr %base)80 %res = sext <vscale x 2 x i8> %load to <vscale x 2 x i64>81 ret <vscale x 2 x i64> %res82}83 84;85; LD1H86;87 88define <vscale x 8 x i16> @ld1h_i16(<vscale x 8 x i1> %pg, ptr %a, i64 %index) {89; CHECK-LABEL: ld1h_i16:90; CHECK: // %bb.0:91; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0, x1, lsl #1]92; CHECK-NEXT: ret93 %base = getelementptr i16, ptr %a, i64 %index94 %load = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16(<vscale x 8 x i1> %pg, ptr %base)95 ret <vscale x 8 x i16> %load96}97 98define <vscale x 8 x half> @ld1h_f16(<vscale x 8 x i1> %pg, ptr %a, i64 %index) {99; CHECK-LABEL: ld1h_f16:100; CHECK: // %bb.0:101; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0, x1, lsl #1]102; CHECK-NEXT: ret103 %base = getelementptr half, ptr %a, i64 %index104 %load = call <vscale x 8 x half> @llvm.aarch64.sve.ld1.nxv8f16(<vscale x 8 x i1> %pg, ptr %base)105 ret <vscale x 8 x half> %load106}107 108define <vscale x 8 x bfloat> @ld1h_bf16(<vscale x 8 x i1> %pg, ptr %a, i64 %index) #0 {109; CHECK-LABEL: ld1h_bf16:110; CHECK: // %bb.0:111; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0, x1, lsl #1]112; CHECK-NEXT: ret113 %base = getelementptr bfloat, ptr %a, i64 %index114 %load = call <vscale x 8 x bfloat> @llvm.aarch64.sve.ld1.nxv8bf16(<vscale x 8 x i1> %pg, ptr %base)115 ret <vscale x 8 x bfloat> %load116}117 118define <vscale x 4 x i32> @ld1h_s(<vscale x 4 x i1> %pred, ptr %a, i64 %index) {119; CHECK-LABEL: ld1h_s:120; CHECK: // %bb.0:121; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0, x1, lsl #1]122; CHECK-NEXT: ret123 %base = getelementptr i16, ptr %a, i64 %index124 %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16(<vscale x 4 x i1> %pred, ptr %base)125 %res = zext <vscale x 4 x i16> %load to <vscale x 4 x i32>126 ret <vscale x 4 x i32> %res127}128 129define <vscale x 4 x i32> @ld1sh_s(<vscale x 4 x i1> %pred, ptr %a, i64 %index) {130; CHECK-LABEL: ld1sh_s:131; CHECK: // %bb.0:132; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0, x1, lsl #1]133; CHECK-NEXT: ret134 %base = getelementptr i16, ptr %a, i64 %index135 %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16(<vscale x 4 x i1> %pred, ptr %base)136 %res = sext <vscale x 4 x i16> %load to <vscale x 4 x i32>137 ret <vscale x 4 x i32> %res138}139 140define <vscale x 2 x i64> @ld1h_d(<vscale x 2 x i1> %pred, ptr %a, i64 %index) {141; CHECK-LABEL: ld1h_d:142; CHECK: // %bb.0:143; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, x1, lsl #1]144; CHECK-NEXT: ret145 %base = getelementptr i16, ptr %a, i64 %index146 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16(<vscale x 2 x i1> %pred, ptr %base)147 %res = zext <vscale x 2 x i16> %load to <vscale x 2 x i64>148 ret <vscale x 2 x i64> %res149}150 151define <vscale x 2 x i64> @ld1sh_d(<vscale x 2 x i1> %pred, ptr %a, i64 %index) {152; CHECK-LABEL: ld1sh_d:153; CHECK: // %bb.0:154; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x0, x1, lsl #1]155; CHECK-NEXT: ret156 %base = getelementptr i16, ptr %a, i64 %index157 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16(<vscale x 2 x i1> %pred, ptr %base)158 %res = sext <vscale x 2 x i16> %load to <vscale x 2 x i64>159 ret <vscale x 2 x i64> %res160}161 162;163; LD1W164;165 166define<vscale x 4 x i32> @ld1w(<vscale x 4 x i1> %pg, ptr %a, i64 %index) {167; CHECK-LABEL: ld1w168; CHECK: ld1w { z0.s }, p0/z, [x0, x1, lsl #2]169; CHECK-NEXT: ret170 %base = getelementptr i32, ptr %a, i64 %index171 %load = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32(<vscale x 4 x i1> %pg, ptr %base)172 ret <vscale x 4 x i32> %load173}174 175define<vscale x 4 x float> @ld1w_f32(<vscale x 4 x i1> %pg, ptr %a, i64 %index) {176; CHECK-LABEL: ld1w_f32177; CHECK: ld1w { z0.s }, p0/z, [x0, x1, lsl #2]178; CHECK-NEXT: ret179 %base = getelementptr float, ptr %a, i64 %index180 %load = call <vscale x 4 x float> @llvm.aarch64.sve.ld1.nxv4f32(<vscale x 4 x i1> %pg, ptr %base)181 ret <vscale x 4 x float> %load182}183 184define <vscale x 2 x i64> @ld1w_d(<vscale x 2 x i1> %pred, ptr %a, i64 %index) {185; CHECK-LABEL: ld1w_d:186; CHECK: // %bb.0:187; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0, x1, lsl #2]188; CHECK-NEXT: ret189 %base = getelementptr i32, ptr %a, i64 %index190 %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32(<vscale x 2 x i1> %pred, ptr %base)191 %res = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>192 ret <vscale x 2 x i64> %res193}194 195define <vscale x 2 x i64> @ld1sw_d(<vscale x 2 x i1> %pred, ptr %a, i64 %index) {196; CHECK-LABEL: ld1sw_d:197; CHECK: // %bb.0:198; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0, x1, lsl #2]199; CHECK-NEXT: ret200 %base = getelementptr i32, ptr %a, i64 %index201 %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32(<vscale x 2 x i1> %pred, ptr %base)202 %res = sext <vscale x 2 x i32> %load to <vscale x 2 x i64>203 ret <vscale x 2 x i64> %res204}205 206;207; LD1D208;209 210define <vscale x 2 x i64> @ld1d(<vscale x 2 x i1> %pg, ptr %a, i64 %index) {211; CHECK-LABEL: ld1d:212; CHECK: // %bb.0:213; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, x1, lsl #3]214; CHECK-NEXT: ret215 %base = getelementptr i64, ptr %a, i64 %index216 %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.nxv2i64(<vscale x 2 x i1> %pg, ptr %base)217 ret <vscale x 2 x i64> %load218}219 220define <vscale x 2 x double> @ld1d_f64(<vscale x 2 x i1> %pg, ptr %a, i64 %index) {221; CHECK-LABEL: ld1d_f64:222; CHECK: // %bb.0:223; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, x1, lsl #3]224; CHECK-NEXT: ret225 %base = getelementptr double, ptr %a, i64 %index226 %load = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.nxv2f64(<vscale x 2 x i1> %pg, ptr %base)227 ret <vscale x 2 x double> %load228}229 230declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8(<vscale x 16 x i1>, ptr)231 232declare <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8(<vscale x 8 x i1>, ptr)233declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16(<vscale x 8 x i1>, ptr)234declare <vscale x 8 x half> @llvm.aarch64.sve.ld1.nxv8f16(<vscale x 8 x i1>, ptr)235declare <vscale x 8 x bfloat> @llvm.aarch64.sve.ld1.nxv8bf16(<vscale x 8 x i1>, ptr)236 237declare <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8(<vscale x 4 x i1>, ptr)238declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16(<vscale x 4 x i1>, ptr)239declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32(<vscale x 4 x i1>, ptr)240declare <vscale x 4 x float> @llvm.aarch64.sve.ld1.nxv4f32(<vscale x 4 x i1>, ptr)241 242declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8(<vscale x 2 x i1>, ptr)243declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16(<vscale x 2 x i1>, ptr)244declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32(<vscale x 2 x i1>, ptr)245declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1.nxv2i64(<vscale x 2 x i1>, ptr)246declare <vscale x 2 x double> @llvm.aarch64.sve.ld1.nxv2f64(<vscale x 2 x i1>, ptr)247 248; +bf16 is required for the bfloat version.249attributes #0 = { "target-features"="+sve,+bf16" }250