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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+f64mm < %s | FileCheck %s3 4;5; LD1ROB6;7 8define <vscale x 16 x i8> @ld1rob_i8(<vscale x 16 x i1> %pg, ptr %a) {9; CHECK-LABEL: ld1rob_i8:10; CHECK: // %bb.0:11; CHECK-NEXT: ld1rob { z0.b }, p0/z, [x0, #32]12; CHECK-NEXT: ret13 %base = getelementptr i8, ptr %a, i64 3214 %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1> %pg, ptr %base)15 ret <vscale x 16 x i8> %load16}17 18;19; LD1ROH20;21 22define <vscale x 8 x i16> @ld1roh_i16(<vscale x 8 x i1> %pg, ptr %a) {23; CHECK-LABEL: ld1roh_i16:24; CHECK: // %bb.0:25; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0, #64]26; CHECK-NEXT: ret27 %base = getelementptr i16, ptr %a, i64 3228 %load = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16(<vscale x 8 x i1> %pg, ptr %base)29 ret <vscale x 8 x i16> %load30}31 32define <vscale x 8 x half> @ld1roh_f16(<vscale x 8 x i1> %pg, ptr %a) {33; CHECK-LABEL: ld1roh_f16:34; CHECK: // %bb.0:35; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0, #64]36; CHECK-NEXT: ret37 %base = getelementptr half, ptr %a, i64 3238 %load = call <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16(<vscale x 8 x i1> %pg, ptr %base)39 ret <vscale x 8 x half> %load40}41 42define <vscale x 8 x bfloat> @ld1roh_bf16(<vscale x 8 x i1> %pg, ptr %a) #0 {43; CHECK-LABEL: ld1roh_bf16:44; CHECK: // %bb.0:45; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0, #64]46; CHECK-NEXT: ret47 %base = getelementptr bfloat, ptr %a, i64 3248 %load = call <vscale x 8 x bfloat> @llvm.aarch64.sve.ld1ro.nxv8bf16(<vscale x 8 x i1> %pg, ptr %base)49 ret <vscale x 8 x bfloat> %load50}51 52;53; LD1ROW54;55 56define <vscale x 4 x i32> @ld1row_i32(<vscale x 4 x i1> %pg, ptr %a) {57; CHECK-LABEL: ld1row_i32:58; CHECK: // %bb.0:59; CHECK-NEXT: ld1row { z0.s }, p0/z, [x0, #128]60; CHECK-NEXT: ret61 %base = getelementptr i32, ptr %a, i64 3262 %load = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32(<vscale x 4 x i1> %pg, ptr %base)63 ret <vscale x 4 x i32> %load64}65 66define <vscale x 4 x float> @ld1row_f32(<vscale x 4 x i1> %pg, ptr %a) {67; CHECK-LABEL: ld1row_f32:68; CHECK: // %bb.0:69; CHECK-NEXT: ld1row { z0.s }, p0/z, [x0, #128]70; CHECK-NEXT: ret71 %base = getelementptr float, ptr %a, i64 3272 %load = call <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32(<vscale x 4 x i1> %pg, ptr %base)73 ret <vscale x 4 x float> %load74}75 76;77; LD1ROD78;79 80define <vscale x 2 x i64> @ld1rod_i64(<vscale x 2 x i1> %pg, ptr %a) {81; CHECK-LABEL: ld1rod_i64:82; CHECK: // %bb.0:83; CHECK-NEXT: ld1rod { z0.d }, p0/z, [x0, #-64]84; CHECK-NEXT: ret85 %base = getelementptr i64, ptr %a, i64 -886 %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64(<vscale x 2 x i1> %pg, ptr %base)87 ret <vscale x 2 x i64> %load88}89 90define <vscale x 2 x double> @ld1rod_f64(<vscale x 2 x i1> %pg, ptr %a) {91; CHECK-LABEL: ld1rod_f64:92; CHECK: // %bb.0:93; CHECK-NEXT: ld1rod { z0.d }, p0/z, [x0, #-128]94; CHECK-NEXT: ret95 %base = getelementptr double, ptr %a, i64 -1696 %load = call <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64(<vscale x 2 x i1> %pg, ptr %base)97 ret <vscale x 2 x double> %load98}99 100 101;;;;;;;;;;;;;;102; range checks: immediate must be a multiple of 32 in the range -256, ..., 224103 104; lower bound105define <vscale x 16 x i8> @ld1rob_i8_lower_bound(<vscale x 16 x i1> %pg, ptr %a) {106; CHECK-LABEL: ld1rob_i8_lower_bound:107; CHECK: // %bb.0:108; CHECK-NEXT: ld1rob { z0.b }, p0/z, [x0, #-256]109; CHECK-NEXT: ret110 %base = getelementptr i8, ptr %a, i64 -256111 %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1> %pg, ptr %base)112 ret <vscale x 16 x i8> %load113}114 115; below lower bound116define <vscale x 8 x i16> @ld1roh_i16_below_lower_bound(<vscale x 8 x i1> %pg, ptr %a) {117; CHECK-LABEL: ld1roh_i16_below_lower_bound:118; CHECK: // %bb.0:119; CHECK-NEXT: mov x8, #-129120; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0, x8, lsl #1]121; CHECK-NEXT: ret122 %base = getelementptr i16, ptr %a, i64 -129123 %load = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16(<vscale x 8 x i1> %pg, ptr %base)124 ret <vscale x 8 x i16> %load125}126 127define <vscale x 16 x i8> @ld1rob_i8_below_lower_bound_01(<vscale x 16 x i1> %pg, ptr %a) {128; CHECK-LABEL: ld1rob_i8_below_lower_bound_01:129; CHECK: // %bb.0:130; CHECK-NEXT: mov x8, #-257131; CHECK-NEXT: ld1rob { z0.b }, p0/z, [x0, x8]132; CHECK-NEXT: ret133 %base = getelementptr i8, ptr %a, i64 -257134 %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1> %pg, ptr %base)135 ret <vscale x 16 x i8> %load136}137 138; not a multiple of 32139define <vscale x 4 x i32> @ld1row_i32_not_multiple(<vscale x 4 x i1> %pg, ptr %a) {140; CHECK-LABEL: ld1row_i32_not_multiple:141; CHECK: // %bb.0:142; CHECK-NEXT: mov x8, #3143; CHECK-NEXT: ld1row { z0.s }, p0/z, [x0, x8, lsl #2]144; CHECK-NEXT: ret145 %base = getelementptr i32, ptr %a, i64 3146 %load = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32(<vscale x 4 x i1> %pg, ptr %base)147 ret <vscale x 4 x i32> %load148}149 150; upper bound151define <vscale x 2 x i64> @ld1rod_i64_upper_bound(<vscale x 2 x i1> %pg, ptr %a) {152; CHECK-LABEL: ld1rod_i64_upper_bound:153; CHECK: // %bb.0:154; CHECK-NEXT: ld1rod { z0.d }, p0/z, [x0, #224]155; CHECK-NEXT: ret156 %base = getelementptr i64, ptr %a, i64 28157 %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64(<vscale x 2 x i1> %pg, ptr %base)158 ret <vscale x 2 x i64> %load159}160 161define <vscale x 16 x i8> @ld1rob_i8_beyond_upper_bound(<vscale x 16 x i1> %pg, ptr %a) {162; CHECK-LABEL: ld1rob_i8_beyond_upper_bound:163; CHECK: // %bb.0:164; CHECK-NEXT: mov w8, #225165; CHECK-NEXT: ld1rob { z0.b }, p0/z, [x0, x8]166; CHECK-NEXT: ret167 %base = getelementptr i8, ptr %a, i64 225168 %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1> %pg, ptr %base)169 ret <vscale x 16 x i8> %load170}171 172declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1>, ptr)173 174declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16(<vscale x 8 x i1>, ptr)175declare <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16(<vscale x 8 x i1>, ptr)176declare <vscale x 8 x bfloat> @llvm.aarch64.sve.ld1ro.nxv8bf16(<vscale x 8 x i1>, ptr)177 178declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32(<vscale x 4 x i1>, ptr)179declare <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32(<vscale x 4 x i1>, ptr)180 181declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64(<vscale x 2 x i1>, ptr)182declare <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64(<vscale x 2 x i1>, ptr)183 184 185; +bf16 is required for the bfloat version.186attributes #0 = { "target-features"="+sve,+f64mm,+bf16" }187