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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+f64mm < %s | FileCheck %s3 4;5; LD1ROB6;7 8define <vscale x 16 x i8> @ld1rob_i8(<vscale x 16 x i1> %pg, ptr %a, i64 %index) {9; CHECK-LABEL: ld1rob_i8:10; CHECK: // %bb.0:11; CHECK-NEXT: ld1rob { z0.b }, p0/z, [x0, x1]12; CHECK-NEXT: ret13 %base = getelementptr i8, ptr %a, i64 %index14 %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1> %pg, ptr %base)15 ret <vscale x 16 x i8> %load16}17 18;19; LD1ROH20;21 22define <vscale x 8 x i16> @ld1roh_i16(<vscale x 8 x i1> %pg, ptr %a, i64 %index) {23; CHECK-LABEL: ld1roh_i16:24; CHECK: // %bb.0:25; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0, x1, lsl #1]26; CHECK-NEXT: ret27 %base = getelementptr i16, ptr %a, i64 %index28 %load = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16(<vscale x 8 x i1> %pg, ptr %base)29 ret <vscale x 8 x i16> %load30}31 32define <vscale x 8 x half> @ld1roh_f16(<vscale x 8 x i1> %pg, ptr %a, i64 %index) {33; CHECK-LABEL: ld1roh_f16:34; CHECK: // %bb.0:35; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0, x1, lsl #1]36; CHECK-NEXT: ret37 %base = getelementptr half, ptr %a, i64 %index38 %load = call <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16(<vscale x 8 x i1> %pg, ptr %base)39 ret <vscale x 8 x half> %load40}41 42define <vscale x 8 x bfloat> @ld1roh_bf16(<vscale x 8 x i1> %pg, ptr %a, i64 %index) #0 {43; CHECK-LABEL: ld1roh_bf16:44; CHECK: // %bb.0:45; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0, x1, lsl #1]46; CHECK-NEXT: ret47 %base = getelementptr bfloat, ptr %a, i64 %index48 %load = call <vscale x 8 x bfloat> @llvm.aarch64.sve.ld1ro.nxv8bf16(<vscale x 8 x i1> %pg, ptr %base)49 ret <vscale x 8 x bfloat> %load50}51 52;53; LD1ROW54;55 56define <vscale x 4 x i32> @ld1row_i32(<vscale x 4 x i1> %pg, ptr %a, i64 %index) {57; CHECK-LABEL: ld1row_i32:58; CHECK: // %bb.0:59; CHECK-NEXT: ld1row { z0.s }, p0/z, [x0, x1, lsl #2]60; CHECK-NEXT: ret61 %base = getelementptr i32, ptr %a, i64 %index62 %load = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32(<vscale x 4 x i1> %pg, ptr %base)63 ret <vscale x 4 x i32> %load64}65 66define <vscale x 4 x float> @ld1row_f32(<vscale x 4 x i1> %pg, ptr %a, i64 %index) {67; CHECK-LABEL: ld1row_f32:68; CHECK: // %bb.0:69; CHECK-NEXT: ld1row { z0.s }, p0/z, [x0, x1, lsl #2]70; CHECK-NEXT: ret71 %base = getelementptr float, ptr %a, i64 %index72 %load = call <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32(<vscale x 4 x i1> %pg, ptr %base)73 ret <vscale x 4 x float> %load74}75 76;77; LD1ROD78;79 80define <vscale x 2 x i64> @ld1rod_i64(<vscale x 2 x i1> %pg, ptr %a, i64 %index) {81; CHECK-LABEL: ld1rod_i64:82; CHECK: // %bb.0:83; CHECK-NEXT: ld1rod { z0.d }, p0/z, [x0, x1, lsl #3]84; CHECK-NEXT: ret85 %base = getelementptr i64, ptr %a, i64 %index86 %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64(<vscale x 2 x i1> %pg, ptr %base)87 ret <vscale x 2 x i64> %load88}89 90define <vscale x 2 x double> @ld1rod_f64(<vscale x 2 x i1> %pg, ptr %a, i64 %index) {91; CHECK-LABEL: ld1rod_f64:92; CHECK: // %bb.0:93; CHECK-NEXT: ld1rod { z0.d }, p0/z, [x0, x1, lsl #3]94; CHECK-NEXT: ret95 %base = getelementptr double, ptr %a, i64 %index96 %load = call <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64(<vscale x 2 x i1> %pg, ptr %base)97 ret <vscale x 2 x double> %load98}99 100declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1>, ptr)101 102declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16(<vscale x 8 x i1>, ptr)103declare <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16(<vscale x 8 x i1>, ptr)104declare <vscale x 8 x bfloat> @llvm.aarch64.sve.ld1ro.nxv8bf16(<vscale x 8 x i1>, ptr)105 106declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32(<vscale x 4 x i1>, ptr)107declare <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32(<vscale x 4 x i1>, ptr)108 109declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64(<vscale x 2 x i1>, ptr)110declare <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64(<vscale x 2 x i1>, ptr)111 112; +bf16 is required for the bfloat version.113attributes #0 = { "target-features"="+sve,+f64mm,+bf16" }114