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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64--linux-gnu -mattr=sve < %s | FileCheck %s3; RUN: llc -mtriple=aarch64--linux-gnu -mattr=sme -force-streaming < %s | FileCheck %s4 5; ld2b6define { <vscale x 16 x i8>, <vscale x 16 x i8> } @ld2.nxv32i8(<vscale x 16 x i1> %Pg, ptr %addr, i64 %a) {7; CHECK-LABEL: ld2.nxv32i8:8; CHECK: // %bb.0:9; CHECK-NEXT: ld2b { z0.b, z1.b }, p0/z, [x0, x1]10; CHECK-NEXT: ret11 %addr2 = getelementptr i8, ptr %addr, i64 %a12 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2.sret.nxv16i8(<vscale x 16 x i1> %Pg, ptr %addr2)13 ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %res14}15 16; ld2h17define { <vscale x 8 x i16>, <vscale x 8 x i16> } @ld2.nxv16i16(<vscale x 8 x i1> %Pg, ptr %addr, i64 %a) {18; CHECK-LABEL: ld2.nxv16i16:19; CHECK: // %bb.0:20; CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, x1, lsl #1]21; CHECK-NEXT: ret22 %addr2 = getelementptr i16, ptr %addr, i64 %a23 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2.sret.nxv8i16(<vscale x 8 x i1> %Pg, ptr %addr2)24 ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %res25}26 27define { <vscale x 8 x half>, <vscale x 8 x half> } @ld2.nxv16f16(<vscale x 8 x i1> %Pg, ptr %addr, i64 %a) {28; CHECK-LABEL: ld2.nxv16f16:29; CHECK: // %bb.0:30; CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, x1, lsl #1]31; CHECK-NEXT: ret32 %addr2 = getelementptr half, ptr %addr, i64 %a33 %res = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2.sret.nxv8f16(<vscale x 8 x i1> %Pg, ptr %addr2)34 ret { <vscale x 8 x half>, <vscale x 8 x half> } %res35}36 37define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @ld2.nxv16bf16(<vscale x 8 x i1> %Pg, ptr %addr, i64 %a) #0 {38; CHECK-LABEL: ld2.nxv16bf16:39; CHECK: // %bb.0:40; CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, x1, lsl #1]41; CHECK-NEXT: ret42 %addr2 = getelementptr bfloat, ptr %addr, i64 %a43 %res = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld2.sret.nxv8bf16(<vscale x 8 x i1> %Pg, ptr %addr2)44 ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %res45}46 47; ld2w48define { <vscale x 4 x i32>, <vscale x 4 x i32> } @ld2.nxv8i32(<vscale x 4 x i1> %Pg, ptr %addr, i64 %a) {49; CHECK-LABEL: ld2.nxv8i32:50; CHECK: // %bb.0:51; CHECK-NEXT: ld2w { z0.s, z1.s }, p0/z, [x0, x1, lsl #2]52; CHECK-NEXT: ret53 %addr2 = getelementptr i32, ptr %addr, i64 %a54 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2.sret.nxv4i32(<vscale x 4 x i1> %Pg, ptr %addr2)55 ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %res56}57 58define { <vscale x 4 x float>, <vscale x 4 x float> } @ld2.nxv8f32(<vscale x 4 x i1> %Pg, ptr %addr, i64 %a) {59; CHECK-LABEL: ld2.nxv8f32:60; CHECK: // %bb.0:61; CHECK-NEXT: ld2w { z0.s, z1.s }, p0/z, [x0, x1, lsl #2]62; CHECK-NEXT: ret63 %addr2 = getelementptr float, ptr %addr, i64 %a64 %res = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld2.sret.nxv4f32(<vscale x 4 x i1> %Pg, ptr %addr2)65 ret { <vscale x 4 x float>, <vscale x 4 x float> } %res66}67 68; ld2d69define { <vscale x 2 x i64>, <vscale x 2 x i64> } @ld2.nxv4i64(<vscale x 2 x i1> %Pg, ptr %addr, i64 %a) {70; CHECK-LABEL: ld2.nxv4i64:71; CHECK: // %bb.0:72; CHECK-NEXT: ld2d { z0.d, z1.d }, p0/z, [x0, x1, lsl #3]73; CHECK-NEXT: ret74 %addr2 = getelementptr i64, ptr %addr, i64 %a75 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2.sret.nxv2i64(<vscale x 2 x i1> %Pg, ptr %addr2)76 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res77}78 79define { <vscale x 2 x double>, <vscale x 2 x double> } @ld2.nxv4f64(<vscale x 2 x i1> %Pg, ptr %addr, i64 %a) {80; CHECK-LABEL: ld2.nxv4f64:81; CHECK: // %bb.0:82; CHECK-NEXT: ld2d { z0.d, z1.d }, p0/z, [x0, x1, lsl #3]83; CHECK-NEXT: ret84 %addr2 = getelementptr double, ptr %addr, i64 %a85 %res = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld2.sret.nxv2f64(<vscale x 2 x i1> %Pg, ptr %addr2)86 ret { <vscale x 2 x double>, <vscale x 2 x double> } %res87}88 89; ld3b90define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @ld3.nxv48i8(<vscale x 16 x i1> %Pg, ptr %addr, i64 %a) {91; CHECK-LABEL: ld3.nxv48i8:92; CHECK: // %bb.0:93; CHECK-NEXT: ld3b { z0.b - z2.b }, p0/z, [x0, x1]94; CHECK-NEXT: ret95 %addr2 = getelementptr i8, ptr %addr, i64 %a96 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8(<vscale x 16 x i1> %Pg, ptr %addr2)97 ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res98}99 100; ld3h101define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @ld3.nxv24i16(<vscale x 8 x i1> %Pg, ptr %addr, i64 %a) {102; CHECK-LABEL: ld3.nxv24i16:103; CHECK: // %bb.0:104; CHECK-NEXT: ld3h { z0.h - z2.h }, p0/z, [x0, x1, lsl #1]105; CHECK-NEXT: ret106 %addr2 = getelementptr i16, ptr %addr, i64 %a107 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld3.sret.nxv8i16(<vscale x 8 x i1> %Pg, ptr %addr2)108 ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %res109}110 111define { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @ld3.nxv24f16(<vscale x 8 x i1> %Pg, ptr %addr, i64 %a) {112; CHECK-LABEL: ld3.nxv24f16:113; CHECK: // %bb.0:114; CHECK-NEXT: ld3h { z0.h - z2.h }, p0/z, [x0, x1, lsl #1]115; CHECK-NEXT: ret116 %addr2 = getelementptr half, ptr %addr, i64 %a117 %res = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld3.sret.nxv8f16(<vscale x 8 x i1> %Pg, ptr %addr2)118 ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %res119}120 121define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @ld3.nxv24bf16(<vscale x 8 x i1> %Pg, ptr %addr, i64 %a) #0 {122; CHECK-LABEL: ld3.nxv24bf16:123; CHECK: // %bb.0:124; CHECK-NEXT: ld3h { z0.h - z2.h }, p0/z, [x0, x1, lsl #1]125; CHECK-NEXT: ret126 %addr2 = getelementptr bfloat, ptr %addr, i64 %a127 %res = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld3.sret.nxv8bf16(<vscale x 8 x i1> %Pg, ptr %addr2)128 ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %res129}130 131; ld3w132define { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @ld3.nxv12i32(<vscale x 4 x i1> %Pg, ptr %addr, i64 %a) {133; CHECK-LABEL: ld3.nxv12i32:134; CHECK: // %bb.0:135; CHECK-NEXT: ld3w { z0.s - z2.s }, p0/z, [x0, x1, lsl #2]136; CHECK-NEXT: ret137 %addr2 = getelementptr i32, ptr %addr, i64 %a138 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld3.sret.nxv4i32(<vscale x 4 x i1> %Pg, ptr %addr2)139 ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %res140}141 142define { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @ld3.nxv12f32(<vscale x 4 x i1> %Pg, ptr %addr, i64 %a) {143; CHECK-LABEL: ld3.nxv12f32:144; CHECK: // %bb.0:145; CHECK-NEXT: ld3w { z0.s - z2.s }, p0/z, [x0, x1, lsl #2]146; CHECK-NEXT: ret147 %addr2 = getelementptr float, ptr %addr, i64 %a148 %res = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld3.sret.nxv4f32(<vscale x 4 x i1> %Pg, ptr %addr2)149 ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %res150}151 152; ld3d153define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @ld3.nxv6i64(<vscale x 2 x i1> %Pg, ptr %addr, i64 %a) {154; CHECK-LABEL: ld3.nxv6i64:155; CHECK: // %bb.0:156; CHECK-NEXT: ld3d { z0.d - z2.d }, p0/z, [x0, x1, lsl #3]157; CHECK-NEXT: ret158 %addr2 = getelementptr i64, ptr %addr, i64 %a159 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld3.sret.nxv2i64(<vscale x 2 x i1> %Pg, ptr %addr2)160 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res161}162 163define { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @ld3.nxv6f64(<vscale x 2 x i1> %Pg, ptr %addr, i64 %a) {164; CHECK-LABEL: ld3.nxv6f64:165; CHECK: // %bb.0:166; CHECK-NEXT: ld3d { z0.d - z2.d }, p0/z, [x0, x1, lsl #3]167; CHECK-NEXT: ret168 %addr2 = getelementptr double, ptr %addr, i64 %a169 %res = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld3.sret.nxv2f64(<vscale x 2 x i1> %Pg, ptr %addr2)170 ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %res171}172 173; ld4b174define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @ld4.nxv64i8(<vscale x 16 x i1> %Pg, ptr %addr, i64 %a) {175; CHECK-LABEL: ld4.nxv64i8:176; CHECK: // %bb.0:177; CHECK-NEXT: ld4b { z0.b - z3.b }, p0/z, [x0, x1]178; CHECK-NEXT: ret179 %addr2 = getelementptr i8, ptr %addr, i64 %a180 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8(<vscale x 16 x i1> %Pg, ptr %addr2)181 ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res182}183 184; ld4h185define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @ld4.nxv32i16(<vscale x 8 x i1> %Pg, ptr %addr, i64 %a) {186; CHECK-LABEL: ld4.nxv32i16:187; CHECK: // %bb.0:188; CHECK-NEXT: ld4h { z0.h - z3.h }, p0/z, [x0, x1, lsl #1]189; CHECK-NEXT: ret190 %addr2 = getelementptr i16, ptr %addr, i64 %a191 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld4.sret.nxv8i16(<vscale x 8 x i1> %Pg, ptr %addr2)192 ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %res193}194 195define { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @ld4.nxv32f16(<vscale x 8 x i1> %Pg, ptr %addr, i64 %a) {196; CHECK-LABEL: ld4.nxv32f16:197; CHECK: // %bb.0:198; CHECK-NEXT: ld4h { z0.h - z3.h }, p0/z, [x0, x1, lsl #1]199; CHECK-NEXT: ret200 %addr2 = getelementptr half, ptr %addr, i64 %a201 %res = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld4.sret.nxv8f16(<vscale x 8 x i1> %Pg, ptr %addr2)202 ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %res203}204 205define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @ld4.nxv32bf16(<vscale x 8 x i1> %Pg, ptr %addr, i64 %a) #0 {206; CHECK-LABEL: ld4.nxv32bf16:207; CHECK: // %bb.0:208; CHECK-NEXT: ld4h { z0.h - z3.h }, p0/z, [x0, x1, lsl #1]209; CHECK-NEXT: ret210 %addr2 = getelementptr bfloat, ptr %addr, i64 %a211 %res = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld4.sret.nxv8bf16(<vscale x 8 x i1> %Pg, ptr %addr2)212 ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %res213}214 215; ld4w216define { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @ld4.nxv16i32(<vscale x 4 x i1> %Pg, ptr %addr, i64 %a) {217; CHECK-LABEL: ld4.nxv16i32:218; CHECK: // %bb.0:219; CHECK-NEXT: ld4w { z0.s - z3.s }, p0/z, [x0, x1, lsl #2]220; CHECK-NEXT: ret221 %addr2 = getelementptr i32, ptr %addr, i64 %a222 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld4.sret.nxv4i32(<vscale x 4 x i1> %Pg, ptr %addr2)223 ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %res224}225 226define { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @ld4.nxv16f32(<vscale x 4 x i1> %Pg, ptr %addr, i64 %a) {227; CHECK-LABEL: ld4.nxv16f32:228; CHECK: // %bb.0:229; CHECK-NEXT: ld4w { z0.s - z3.s }, p0/z, [x0, x1, lsl #2]230; CHECK-NEXT: ret231 %addr2 = getelementptr float, ptr %addr, i64 %a232 %res = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld4.sret.nxv4f32(<vscale x 4 x i1> %Pg, ptr %addr2)233 ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %res234}235 236; ld4d237define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @ld4.nxv8i64(<vscale x 2 x i1> %Pg, ptr %addr, i64 %a) {238; CHECK-LABEL: ld4.nxv8i64:239; CHECK: // %bb.0:240; CHECK-NEXT: ld4d { z0.d - z3.d }, p0/z, [x0, x1, lsl #3]241; CHECK-NEXT: ret242 %addr2 = getelementptr i64, ptr %addr, i64 %a243 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld4.sret.nxv2i64(<vscale x 2 x i1> %Pg, ptr %addr2)244 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res245}246 247define { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @ld4.nxv8f64(<vscale x 2 x i1> %Pg, ptr %addr, i64 %a) {248; CHECK-LABEL: ld4.nxv8f64:249; CHECK: // %bb.0:250; CHECK-NEXT: ld4d { z0.d - z3.d }, p0/z, [x0, x1, lsl #3]251; CHECK-NEXT: ret252 %addr2 = getelementptr double, ptr %addr, i64 %a253 %res = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld4.sret.nxv2f64(<vscale x 2 x i1> %Pg, ptr %addr2)254 ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %res255}256 257declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2.sret.nxv16i8(<vscale x 16 x i1>, ptr)258declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2.sret.nxv8i16(<vscale x 8 x i1>, ptr)259declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2.sret.nxv4i32(<vscale x 4 x i1>, ptr)260declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2.sret.nxv2i64(<vscale x 2 x i1>, ptr)261declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2.sret.nxv8f16(<vscale x 8 x i1>, ptr)262declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld2.sret.nxv8bf16(<vscale x 8 x i1>, ptr)263declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld2.sret.nxv4f32(<vscale x 4 x i1>, ptr)264declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld2.sret.nxv2f64(<vscale x 2 x i1>, ptr)265 266declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8(<vscale x 16 x i1>, ptr)267declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld3.sret.nxv8i16(<vscale x 8 x i1>, ptr)268declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld3.sret.nxv4i32(<vscale x 4 x i1>, ptr)269declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld3.sret.nxv2i64(<vscale x 2 x i1>, ptr)270declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld3.sret.nxv8f16(<vscale x 8 x i1>, ptr)271declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld3.sret.nxv8bf16(<vscale x 8 x i1>, ptr)272declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld3.sret.nxv4f32(<vscale x 4 x i1>, ptr)273declare { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld3.sret.nxv2f64(<vscale x 2 x i1>, ptr)274 275declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8(<vscale x 16 x i1>, ptr)276declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld4.sret.nxv8i16(<vscale x 8 x i1>, ptr)277declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld4.sret.nxv4i32(<vscale x 4 x i1>, ptr)278declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld4.sret.nxv2i64(<vscale x 2 x i1>, ptr)279declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld4.sret.nxv8f16(<vscale x 8 x i1>, ptr)280declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld4.sret.nxv8bf16(<vscale x 8 x i1>, ptr)281declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld4.sret.nxv4f32(<vscale x 4 x i1>, ptr)282declare { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld4.sret.nxv2f64(<vscale x 2 x i1>, ptr)283 284; +bf16 is required for the bfloat version.285attributes #0 = { "target-features"="+bf16" }286