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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4;5; AND6;7 8define <vscale x 16 x i8> @and_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {9; CHECK-LABEL: and_i8:10; CHECK: // %bb.0:11; CHECK-NEXT: and z0.b, z0.b, #0x712; CHECK-NEXT: ret13 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.and.u.nxv16i8(<vscale x 16 x i1> %pg,14 <vscale x 16 x i8> %a,15 <vscale x 16 x i8> splat (i8 7))16 ret <vscale x 16 x i8> %out17}18 19define <vscale x 8 x i16> @and_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {20; CHECK-LABEL: and_i16:21; CHECK: // %bb.0:22; CHECK-NEXT: and z0.h, z0.h, #0xf023; CHECK-NEXT: ret24 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.and.u.nxv8i16(<vscale x 8 x i1> %pg,25 <vscale x 8 x i16> %a,26 <vscale x 8 x i16> splat (i16 240))27 ret <vscale x 8 x i16> %out28}29 30define <vscale x 4 x i32> @and_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {31; CHECK-LABEL: and_i32:32; CHECK: // %bb.0:33; CHECK-NEXT: and z0.s, z0.s, #0xffff0034; CHECK-NEXT: ret35 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.and.u.nxv4i32(<vscale x 4 x i1> %pg,36 <vscale x 4 x i32> %a,37 <vscale x 4 x i32> splat (i32 16776960))38 ret <vscale x 4 x i32> %out39}40 41define <vscale x 2 x i64> @and_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {42; CHECK-LABEL: and_i64:43; CHECK: // %bb.0:44; CHECK-NEXT: and z0.d, z0.d, #0xfffc00000000000045; CHECK-NEXT: ret46 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.and.u.nxv2i64(<vscale x 2 x i1> %pg,47 <vscale x 2 x i64> %a,48 <vscale x 2 x i64> splat (i64 18445618173802708992))49 ret <vscale x 2 x i64> %out50}51 52;53; BIC54;55 56define <vscale x 16 x i8> @bic_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {57; CHECK-LABEL: bic_i8:58; CHECK: // %bb.0:59; CHECK-NEXT: and z0.b, z0.b, #0x160; CHECK-NEXT: ret61 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.bic.u.nxv16i8(<vscale x 16 x i1> %pg,62 <vscale x 16 x i8> %a,63 <vscale x 16 x i8> splat (i8 254))64 ret <vscale x 16 x i8> %out65}66 67define <vscale x 8 x i16> @bic_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {68; CHECK-LABEL: bic_i16:69; CHECK: // %bb.0:70; CHECK-NEXT: and z0.h, z0.h, #0x171; CHECK-NEXT: ret72 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.bic.u.nxv8i16(<vscale x 8 x i1> %pg,73 <vscale x 8 x i16> %a,74 <vscale x 8 x i16> splat (i16 65534))75 ret <vscale x 8 x i16> %out76}77 78define <vscale x 4 x i32> @bic_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {79; CHECK-LABEL: bic_i32:80; CHECK: // %bb.0:81; CHECK-NEXT: and z0.s, z0.s, #0xff0000ff82; CHECK-NEXT: ret83 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.bic.u.nxv4i32(<vscale x 4 x i1> %pg,84 <vscale x 4 x i32> %a,85 <vscale x 4 x i32> splat (i32 16776960))86 ret <vscale x 4 x i32> %out87}88 89define <vscale x 2 x i64> @bic_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {90; CHECK-LABEL: bic_i64:91; CHECK: // %bb.0:92; CHECK-NEXT: and z0.d, z0.d, #0x3ffffffffffff93; CHECK-NEXT: ret94 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.bic.u.nxv2i64(<vscale x 2 x i1> %pg,95 <vscale x 2 x i64> %a,96 <vscale x 2 x i64> splat (i64 18445618173802708992))97 ret <vscale x 2 x i64> %out98}99 100;101; EOR102;103 104define <vscale x 16 x i8> @eor_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {105; CHECK-LABEL: eor_i8:106; CHECK: // %bb.0:107; CHECK-NEXT: eor z0.b, z0.b, #0xf108; CHECK-NEXT: ret109 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.eor.u.nxv16i8(<vscale x 16 x i1> %pg,110 <vscale x 16 x i8> %a,111 <vscale x 16 x i8> splat (i8 15))112 ret <vscale x 16 x i8> %out113}114 115define <vscale x 8 x i16> @eor_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {116; CHECK-LABEL: eor_i16:117; CHECK: // %bb.0:118; CHECK-NEXT: eor z0.h, z0.h, #0xfc07119; CHECK-NEXT: ret120 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.eor.u.nxv8i16(<vscale x 8 x i1> %pg,121 <vscale x 8 x i16> %a,122 <vscale x 8 x i16> splat (i16 64519))123 ret <vscale x 8 x i16> %out124}125 126define <vscale x 4 x i32> @eor_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {127; CHECK-LABEL: eor_i32:128; CHECK: // %bb.0:129; CHECK-NEXT: eor z0.s, z0.s, #0xffff00130; CHECK-NEXT: ret131 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.u.nxv4i32(<vscale x 4 x i1> %pg,132 <vscale x 4 x i32> %a,133 <vscale x 4 x i32> splat (i32 16776960))134 ret <vscale x 4 x i32> %out135}136 137define <vscale x 2 x i64> @eor_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {138; CHECK-LABEL: eor_i64:139; CHECK: // %bb.0:140; CHECK-NEXT: eor z0.d, z0.d, #0x1000000000000141; CHECK-NEXT: ret142 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.eor.u.nxv2i64(<vscale x 2 x i1> %pg,143 <vscale x 2 x i64> %a,144 <vscale x 2 x i64> splat (i64 281474976710656))145 ret <vscale x 2 x i64> %out146}147 148;149; ORR150;151 152define <vscale x 16 x i8> @orr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {153; CHECK-LABEL: orr_i8:154; CHECK: // %bb.0:155; CHECK-NEXT: orr z0.b, z0.b, #0x6156; CHECK-NEXT: ret157 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.orr.u.nxv16i8(<vscale x 16 x i1> %pg,158 <vscale x 16 x i8> %a,159 <vscale x 16 x i8> splat (i8 6))160 ret <vscale x 16 x i8> %out161}162 163define <vscale x 8 x i16> @orr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {164; CHECK-LABEL: orr_i16:165; CHECK: // %bb.0:166; CHECK-NEXT: orr z0.h, z0.h, #0x8001167; CHECK-NEXT: ret168 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.orr.u.nxv8i16(<vscale x 8 x i1> %pg,169 <vscale x 8 x i16> %a,170 <vscale x 8 x i16> splat (i16 32769))171 ret <vscale x 8 x i16> %out172}173 174define <vscale x 4 x i32> @orr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {175; CHECK-LABEL: orr_i32:176; CHECK: // %bb.0:177; CHECK-NEXT: orr z0.s, z0.s, #0xffff178; CHECK-NEXT: ret179 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.u.nxv4i32(<vscale x 4 x i1> %pg,180 <vscale x 4 x i32> %a,181 <vscale x 4 x i32> splat (i32 65535))182 ret <vscale x 4 x i32> %out183}184 185define <vscale x 2 x i64> @orr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {186; CHECK-LABEL: orr_i64:187; CHECK: // %bb.0:188; CHECK-NEXT: orr z0.d, z0.d, #0x7ffc000000000000189; CHECK-NEXT: ret190 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.orr.u.nxv2i64(<vscale x 2 x i1> %pg,191 <vscale x 2 x i64> %a,192 <vscale x 2 x i64> splat (i64 9222246136947933184))193 ret <vscale x 2 x i64> %out194}195 196; As orr_i32 but where pg is i8 based and thus compatible for i32.197define <vscale x 4 x i32> @orr_i32_ptrue_all_b(<vscale x 4 x i32> %a) {198; CHECK-LABEL: orr_i32_ptrue_all_b:199; CHECK: // %bb.0:200; CHECK-NEXT: orr z0.s, z0.s, #0xffff201; CHECK-NEXT: ret202 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)203 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)204 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 65535)205 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.u.nxv4i32(<vscale x 4 x i1> %pg.s,206 <vscale x 4 x i32> %a,207 <vscale x 4 x i32> %b)208 ret <vscale x 4 x i32> %out209}210 211; As orr_i32 but where pg is i16 based and thus compatible for i32.212define <vscale x 4 x i32> @orr_i32_ptrue_all_h(<vscale x 4 x i32> %a) {213; CHECK-LABEL: orr_i32_ptrue_all_h:214; CHECK: // %bb.0:215; CHECK-NEXT: orr z0.s, z0.s, #0xffff216; CHECK-NEXT: ret217 %pg.h = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)218 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %pg.h)219 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)220 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 65535)221 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.u.nxv4i32(<vscale x 4 x i1> %pg.s,222 <vscale x 4 x i32> %a,223 <vscale x 4 x i32> %b)224 ret <vscale x 4 x i32> %out225}226 227; As orr_i32 but where pg is i64 based, which is not compatibile for i32 and228; thus inactive lanes are important and the immediate form cannot be used.229define <vscale x 4 x i32> @orr_i32_ptrue_all_d(<vscale x 4 x i32> %a) {230; CHECK-LABEL: orr_i32_ptrue_all_d:231; CHECK: // %bb.0:232; CHECK-NEXT: mov z1.s, #65535 // =0xffff233; CHECK-NEXT: ptrue p0.d234; CHECK-NEXT: orr z0.s, p0/m, z0.s, z1.s235; CHECK-NEXT: ret236 %pg.d = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)237 %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg.d)238 %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b)239 %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 65535)240 %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> %pg.s,241 <vscale x 4 x i32> %a,242 <vscale x 4 x i32> %b)243 ret <vscale x 4 x i32> %out244}245 246declare <vscale x 16 x i8> @llvm.aarch64.sve.and.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)247declare <vscale x 8 x i16> @llvm.aarch64.sve.and.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)248declare <vscale x 4 x i32> @llvm.aarch64.sve.and.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)249declare <vscale x 2 x i64> @llvm.aarch64.sve.and.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)250 251declare <vscale x 16 x i8> @llvm.aarch64.sve.bic.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)252declare <vscale x 8 x i16> @llvm.aarch64.sve.bic.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)253declare <vscale x 4 x i32> @llvm.aarch64.sve.bic.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)254declare <vscale x 2 x i64> @llvm.aarch64.sve.bic.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)255 256declare <vscale x 16 x i8> @llvm.aarch64.sve.eor.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)257declare <vscale x 8 x i16> @llvm.aarch64.sve.eor.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)258declare <vscale x 4 x i32> @llvm.aarch64.sve.eor.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)259declare <vscale x 2 x i64> @llvm.aarch64.sve.eor.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)260 261declare <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)262 263declare <vscale x 16 x i8> @llvm.aarch64.sve.orr.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)264declare <vscale x 8 x i16> @llvm.aarch64.sve.orr.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)265declare <vscale x 4 x i32> @llvm.aarch64.sve.orr.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)266declare <vscale x 2 x i64> @llvm.aarch64.sve.orr.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)267 268declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>)269declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>)270declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>)271 272declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 16 x i1>)273declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>)274declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>)275 276declare <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32)277 278declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32)279declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32)280declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)281declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32)282