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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mattr=+sve < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6;7; AND8;9 10define <vscale x 16 x i8> @and_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {11; CHECK-LABEL: and_i8:12; CHECK: // %bb.0:13; CHECK-NEXT: and z0.d, z0.d, z1.d14; CHECK-NEXT: ret15 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.and.u.nxv16i8(<vscale x 16 x i1> %pg,16 <vscale x 16 x i8> %a,17 <vscale x 16 x i8> %b)18 ret <vscale x 16 x i8> %out19}20 21define <vscale x 8 x i16> @and_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {22; CHECK-LABEL: and_i16:23; CHECK: // %bb.0:24; CHECK-NEXT: and z0.d, z0.d, z1.d25; CHECK-NEXT: ret26 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.and.u.nxv8i16(<vscale x 8 x i1> %pg,27 <vscale x 8 x i16> %a,28 <vscale x 8 x i16> %b)29 ret <vscale x 8 x i16> %out30}31 32define <vscale x 4 x i32> @and_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {33; CHECK-LABEL: and_i32:34; CHECK: // %bb.0:35; CHECK-NEXT: and z0.d, z0.d, z1.d36; CHECK-NEXT: ret37 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.and.u.nxv4i32(<vscale x 4 x i1> %pg,38 <vscale x 4 x i32> %a,39 <vscale x 4 x i32> %b)40 ret <vscale x 4 x i32> %out41}42 43define <vscale x 2 x i64> @and_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {44; CHECK-LABEL: and_i64:45; CHECK: // %bb.0:46; CHECK-NEXT: and z0.d, z0.d, z1.d47; CHECK-NEXT: ret48 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.and.u.nxv2i64(<vscale x 2 x i1> %pg,49 <vscale x 2 x i64> %a,50 <vscale x 2 x i64> %b)51 ret <vscale x 2 x i64> %out52}53 54;55; AND (immediate)56;57 58define <vscale x 16 x i8> @and_imm_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {59; CHECK-LABEL: and_imm_i8:60; CHECK: // %bb.0:61; CHECK-NEXT: and z0.b, z0.b, #0x362; CHECK-NEXT: ret63 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.and.u.nxv16i8(<vscale x 16 x i1> %pg,64 <vscale x 16 x i8> %a,65 <vscale x 16 x i8> splat(i8 3))66 ret <vscale x 16 x i8> %out67}68 69define <vscale x 8 x i16> @and_imm_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {70; CHECK-LABEL: and_imm_i16:71; CHECK: // %bb.0:72; CHECK-NEXT: and z0.h, z0.h, #0x473; CHECK-NEXT: ret74 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.and.u.nxv8i16(<vscale x 8 x i1> %pg,75 <vscale x 8 x i16> %a,76 <vscale x 8 x i16> splat(i16 4))77 ret <vscale x 8 x i16> %out78}79 80define <vscale x 4 x i32> @and_imm_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {81; CHECK-LABEL: and_imm_i32:82; CHECK: // %bb.0:83; CHECK-NEXT: and z0.s, z0.s, #0x1084; CHECK-NEXT: ret85 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.and.u.nxv4i32(<vscale x 4 x i1> %pg,86 <vscale x 4 x i32> %a,87 <vscale x 4 x i32> splat(i32 16))88 ret <vscale x 4 x i32> %out89}90 91define <vscale x 2 x i64> @and_imm_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {92; CHECK-LABEL: and_imm_i64:93; CHECK: // %bb.0:94; CHECK-NEXT: and z0.d, z0.d, #0x2095; CHECK-NEXT: ret96 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.and.u.nxv2i64(<vscale x 2 x i1> %pg,97 <vscale x 2 x i64> %a,98 <vscale x 2 x i64> splat(i64 32))99 ret <vscale x 2 x i64> %out100}101 102;103; EOR104;105 106define <vscale x 16 x i8> @eor_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {107; CHECK-LABEL: eor_i8:108; CHECK: // %bb.0:109; CHECK-NEXT: eor z0.d, z0.d, z1.d110; CHECK-NEXT: ret111 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.eor.u.nxv16i8(<vscale x 16 x i1> %pg,112 <vscale x 16 x i8> %a,113 <vscale x 16 x i8> %b)114 ret <vscale x 16 x i8> %out115}116 117define <vscale x 8 x i16> @eor_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {118; CHECK-LABEL: eor_i16:119; CHECK: // %bb.0:120; CHECK-NEXT: eor z0.d, z0.d, z1.d121; CHECK-NEXT: ret122 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.eor.u.nxv8i16(<vscale x 8 x i1> %pg,123 <vscale x 8 x i16> %a,124 <vscale x 8 x i16> %b)125 ret <vscale x 8 x i16> %out126}127 128define <vscale x 4 x i32> @eor_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {129; CHECK-LABEL: eor_i32:130; CHECK: // %bb.0:131; CHECK-NEXT: eor z0.d, z0.d, z1.d132; CHECK-NEXT: ret133 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.u.nxv4i32(<vscale x 4 x i1> %pg,134 <vscale x 4 x i32> %a,135 <vscale x 4 x i32> %b)136 ret <vscale x 4 x i32> %out137}138 139define <vscale x 2 x i64> @eor_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {140; CHECK-LABEL: eor_i64:141; CHECK: // %bb.0:142; CHECK-NEXT: eor z0.d, z0.d, z1.d143; CHECK-NEXT: ret144 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.eor.u.nxv2i64(<vscale x 2 x i1> %pg,145 <vscale x 2 x i64> %a,146 <vscale x 2 x i64> %b)147 ret <vscale x 2 x i64> %out148}149 150;151; EOR (immediate)152;153 154define <vscale x 16 x i8> @eor_imm_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {155; CHECK-LABEL: eor_imm_i8:156; CHECK: // %bb.0:157; CHECK-NEXT: eor z0.b, z0.b, #0x7158; CHECK-NEXT: ret159 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.eor.u.nxv16i8(<vscale x 16 x i1> %pg,160 <vscale x 16 x i8> %a,161 <vscale x 16 x i8> splat(i8 7))162 ret <vscale x 16 x i8> %out163}164 165define <vscale x 8 x i16> @eor_imm_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {166; CHECK-LABEL: eor_imm_i16:167; CHECK: // %bb.0:168; CHECK-NEXT: eor z0.h, z0.h, #0x8169; CHECK-NEXT: ret170 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.eor.u.nxv8i16(<vscale x 8 x i1> %pg,171 <vscale x 8 x i16> %a,172 <vscale x 8 x i16> splat(i16 8))173 ret <vscale x 8 x i16> %out174}175 176define <vscale x 4 x i32> @eor_imm_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {177; CHECK-LABEL: eor_imm_i32:178; CHECK: // %bb.0:179; CHECK-NEXT: eor z0.s, z0.s, #0x10180; CHECK-NEXT: ret181 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.u.nxv4i32(<vscale x 4 x i1> %pg,182 <vscale x 4 x i32> %a,183 <vscale x 4 x i32> splat(i32 16))184 ret <vscale x 4 x i32> %out185}186 187define <vscale x 2 x i64> @eor_imm_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {188; CHECK-LABEL: eor_imm_i64:189; CHECK: // %bb.0:190; CHECK-NEXT: eor z0.d, z0.d, #0x20191; CHECK-NEXT: ret192 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.eor.u.nxv2i64(<vscale x 2 x i1> %pg,193 <vscale x 2 x i64> %a,194 <vscale x 2 x i64> splat(i64 32))195 ret <vscale x 2 x i64> %out196}197 198;199; ORR200;201 202define <vscale x 16 x i8> @orr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {203; CHECK-LABEL: orr_i8:204; CHECK: // %bb.0:205; CHECK-NEXT: orr z0.d, z0.d, z1.d206; CHECK-NEXT: ret207 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.orr.u.nxv16i8(<vscale x 16 x i1> %pg,208 <vscale x 16 x i8> %a,209 <vscale x 16 x i8> %b)210 ret <vscale x 16 x i8> %out211}212 213define <vscale x 8 x i16> @orr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {214; CHECK-LABEL: orr_i16:215; CHECK: // %bb.0:216; CHECK-NEXT: orr z0.d, z0.d, z1.d217; CHECK-NEXT: ret218 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.orr.u.nxv8i16(<vscale x 8 x i1> %pg,219 <vscale x 8 x i16> %a,220 <vscale x 8 x i16> %b)221 ret <vscale x 8 x i16> %out222}223 224define <vscale x 4 x i32> @orr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {225; CHECK-LABEL: orr_i32:226; CHECK: // %bb.0:227; CHECK-NEXT: orr z0.d, z0.d, z1.d228; CHECK-NEXT: ret229 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.u.nxv4i32(<vscale x 4 x i1> %pg,230 <vscale x 4 x i32> %a,231 <vscale x 4 x i32> %b)232 ret <vscale x 4 x i32> %out233}234 235define <vscale x 2 x i64> @orr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {236; CHECK-LABEL: orr_i64:237; CHECK: // %bb.0:238; CHECK-NEXT: orr z0.d, z0.d, z1.d239; CHECK-NEXT: ret240 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.orr.u.nxv2i64(<vscale x 2 x i1> %pg,241 <vscale x 2 x i64> %a,242 <vscale x 2 x i64> %b)243 ret <vscale x 2 x i64> %out244}245 246;247; ORR (immediate)248;249 250define <vscale x 16 x i8> @orr_imm_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {251; CHECK-LABEL: orr_imm_i8:252; CHECK: // %bb.0:253; CHECK-NEXT: orr z0.b, z0.b, #0x8254; CHECK-NEXT: ret255 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.orr.u.nxv16i8(<vscale x 16 x i1> %pg,256 <vscale x 16 x i8> %a,257 <vscale x 16 x i8> splat(i8 8))258 ret <vscale x 16 x i8> %out259}260 261define <vscale x 8 x i16> @orr_imm_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {262; CHECK-LABEL: orr_imm_i16:263; CHECK: // %bb.0:264; CHECK-NEXT: orr z0.h, z0.h, #0xc265; CHECK-NEXT: ret266 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.orr.u.nxv8i16(<vscale x 8 x i1> %pg,267 <vscale x 8 x i16> %a,268 <vscale x 8 x i16> splat(i16 12))269 ret <vscale x 8 x i16> %out270}271 272define <vscale x 4 x i32> @orr_imm_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {273; CHECK-LABEL: orr_imm_i32:274; CHECK: // %bb.0:275; CHECK-NEXT: orr z0.s, z0.s, #0x10276; CHECK-NEXT: ret277 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.u.nxv4i32(<vscale x 4 x i1> %pg,278 <vscale x 4 x i32> %a,279 <vscale x 4 x i32> splat(i32 16))280 ret <vscale x 4 x i32> %out281}282 283define <vscale x 2 x i64> @orr_imm_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {284; CHECK-LABEL: orr_imm_i64:285; CHECK: // %bb.0:286; CHECK-NEXT: orr z0.d, z0.d, #0x20287; CHECK-NEXT: ret288 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.orr.u.nxv2i64(<vscale x 2 x i1> %pg,289 <vscale x 2 x i64> %a,290 <vscale x 2 x i64> splat(i64 32))291 ret <vscale x 2 x i64> %out292}293 294;295; BIC296;297 298define <vscale x 16 x i8> @bic_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {299; CHECK-LABEL: bic_i8:300; CHECK: // %bb.0:301; CHECK-NEXT: bic z0.d, z0.d, z1.d302; CHECK-NEXT: ret303 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.bic.u.nxv16i8(<vscale x 16 x i1> %pg,304 <vscale x 16 x i8> %a,305 <vscale x 16 x i8> %b)306 ret <vscale x 16 x i8> %out307}308 309define <vscale x 8 x i16> @bic_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {310; CHECK-LABEL: bic_i16:311; CHECK: // %bb.0:312; CHECK-NEXT: bic z0.d, z0.d, z1.d313; CHECK-NEXT: ret314 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.bic.u.nxv8i16(<vscale x 8 x i1> %pg,315 <vscale x 8 x i16> %a,316 <vscale x 8 x i16> %b)317 ret <vscale x 8 x i16> %out318}319 320define <vscale x 4 x i32> @bic_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {321; CHECK-LABEL: bic_i32:322; CHECK: // %bb.0:323; CHECK-NEXT: bic z0.d, z0.d, z1.d324; CHECK-NEXT: ret325 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.bic.u.nxv4i32(<vscale x 4 x i1> %pg,326 <vscale x 4 x i32> %a,327 <vscale x 4 x i32> %b)328 ret <vscale x 4 x i32> %out329}330 331define <vscale x 2 x i64> @bic_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {332; CHECK-LABEL: bic_i64:333; CHECK: // %bb.0:334; CHECK-NEXT: bic z0.d, z0.d, z1.d335; CHECK-NEXT: ret336 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.bic.u.nxv2i64(<vscale x 2 x i1> %pg,337 <vscale x 2 x i64> %a,338 <vscale x 2 x i64> %b)339 ret <vscale x 2 x i64> %out340}341 342;343; BIC (immediate)344;345 346define <vscale x 16 x i8> @bic_imm_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {347; CHECK-LABEL: bic_imm_i8:348; CHECK: // %bb.0:349; CHECK-NEXT: and z0.b, z0.b, #0xf8350; CHECK-NEXT: ret351 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.bic.u.nxv16i8(<vscale x 16 x i1> %pg,352 <vscale x 16 x i8> %a,353 <vscale x 16 x i8> splat(i8 7))354 ret <vscale x 16 x i8> %out355}356 357define <vscale x 8 x i16> @bic_imm_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {358; CHECK-LABEL: bic_imm_i16:359; CHECK: // %bb.0:360; CHECK-NEXT: and z0.h, z0.h, #0xfff7361; CHECK-NEXT: ret362 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.bic.u.nxv8i16(<vscale x 8 x i1> %pg,363 <vscale x 8 x i16> %a,364 <vscale x 8 x i16> splat(i16 8))365 ret <vscale x 8 x i16> %out366}367 368define <vscale x 4 x i32> @bic_imm_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {369; CHECK-LABEL: bic_imm_i32:370; CHECK: // %bb.0:371; CHECK-NEXT: and z0.s, z0.s, #0xffffffef372; CHECK-NEXT: ret373 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.bic.u.nxv4i32(<vscale x 4 x i1> %pg,374 <vscale x 4 x i32> %a,375 <vscale x 4 x i32> splat(i32 16))376 ret <vscale x 4 x i32> %out377}378 379define <vscale x 2 x i64> @bic_imm_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {380; CHECK-LABEL: bic_imm_i64:381; CHECK: // %bb.0:382; CHECK-NEXT: and z0.d, z0.d, #0xffffffffffffffdf383; CHECK-NEXT: ret384 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.bic.u.nxv2i64(<vscale x 2 x i1> %pg,385 <vscale x 2 x i64> %a,386 <vscale x 2 x i64> splat(i64 32))387 ret <vscale x 2 x i64> %out388}389 390declare <vscale x 16 x i8> @llvm.aarch64.sve.and.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)391declare <vscale x 8 x i16> @llvm.aarch64.sve.and.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)392declare <vscale x 4 x i32> @llvm.aarch64.sve.and.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)393declare <vscale x 2 x i64> @llvm.aarch64.sve.and.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)394 395declare <vscale x 16 x i8> @llvm.aarch64.sve.eor.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)396declare <vscale x 8 x i16> @llvm.aarch64.sve.eor.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)397declare <vscale x 4 x i32> @llvm.aarch64.sve.eor.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)398declare <vscale x 2 x i64> @llvm.aarch64.sve.eor.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)399 400declare <vscale x 16 x i8> @llvm.aarch64.sve.orr.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)401declare <vscale x 8 x i16> @llvm.aarch64.sve.orr.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)402declare <vscale x 4 x i32> @llvm.aarch64.sve.orr.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)403declare <vscale x 2 x i64> @llvm.aarch64.sve.orr.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)404 405declare <vscale x 16 x i8> @llvm.aarch64.sve.bic.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)406declare <vscale x 8 x i16> @llvm.aarch64.sve.bic.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)407declare <vscale x 4 x i32> @llvm.aarch64.sve.bic.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)408declare <vscale x 2 x i64> @llvm.aarch64.sve.bic.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)409