230 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -asm-verbose=1 < %s | FileCheck %s3 4;5; LD1B6;7 8define <vscale x 16 x i32> @masked_ld1b_i8_sext_i32(ptr %base, <vscale x 16 x i1> %mask) {9; CHECK-LABEL: masked_ld1b_i8_sext_i32:10; CHECK: // %bb.0:11; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]12; CHECK-NEXT: sunpklo z1.h, z0.b13; CHECK-NEXT: sunpkhi z3.h, z0.b14; CHECK-NEXT: sunpklo z0.s, z1.h15; CHECK-NEXT: sunpkhi z1.s, z1.h16; CHECK-NEXT: sunpklo z2.s, z3.h17; CHECK-NEXT: sunpkhi z3.s, z3.h18; CHECK-NEXT: ret19 %wide.masked.load = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0(ptr %base, i32 2, <vscale x 16 x i1> %mask, <vscale x 16 x i8> poison)20 %res = sext <vscale x 16 x i8> %wide.masked.load to <vscale x 16 x i32>21 ret <vscale x 16 x i32> %res22}23 24define <vscale x 8 x i32> @masked_ld1b_nxv8i8_sext_i32(ptr %a, <vscale x 8 x i1> %mask) {25; CHECK-LABEL: masked_ld1b_nxv8i8_sext_i32:26; CHECK: // %bb.0:27; CHECK-NEXT: ld1sb { z1.h }, p0/z, [x0]28; CHECK-NEXT: sunpklo z0.s, z1.h29; CHECK-NEXT: sunpkhi z1.s, z1.h30; CHECK-NEXT: ret31 %wide.masked.load = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8.p0(ptr %a, i32 1, <vscale x 8 x i1> %mask, <vscale x 8 x i8> poison)32 %res = sext <vscale x 8 x i8> %wide.masked.load to <vscale x 8 x i32>33 ret <vscale x 8 x i32> %res34}35 36define <vscale x 16 x i32> @masked_ld1b_i8_zext_i32(ptr %base, <vscale x 16 x i1> %mask) {37; CHECK-LABEL: masked_ld1b_i8_zext_i32:38; CHECK: // %bb.0:39; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]40; CHECK-NEXT: uunpklo z1.h, z0.b41; CHECK-NEXT: uunpkhi z3.h, z0.b42; CHECK-NEXT: uunpklo z0.s, z1.h43; CHECK-NEXT: uunpkhi z1.s, z1.h44; CHECK-NEXT: uunpklo z2.s, z3.h45; CHECK-NEXT: uunpkhi z3.s, z3.h46; CHECK-NEXT: ret47 %wide.masked.load = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0(ptr %base, i32 2, <vscale x 16 x i1> %mask, <vscale x 16 x i8> poison)48 %res = zext <vscale x 16 x i8> %wide.masked.load to <vscale x 16 x i32>49 ret <vscale x 16 x i32> %res50}51 52define <vscale x 8 x i32> @masked_ld1b_nxv8i8_zext_i32(ptr %a, <vscale x 8 x i1> %mask) {53; CHECK-LABEL: masked_ld1b_nxv8i8_zext_i32:54; CHECK: // %bb.0:55; CHECK-NEXT: ld1b { z1.h }, p0/z, [x0]56; CHECK-NEXT: uunpklo z0.s, z1.h57; CHECK-NEXT: uunpkhi z1.s, z1.h58; CHECK-NEXT: ret59 %wide.masked.load = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8.p0(ptr %a, i32 1, <vscale x 8 x i1> %mask, <vscale x 8 x i8> poison)60 %res = zext <vscale x 8 x i8> %wide.masked.load to <vscale x 8 x i32>61 ret <vscale x 8 x i32> %res62}63 64define <vscale x 16 x i64> @masked_ld1b_i8_sext(ptr %base, <vscale x 16 x i1> %mask) {65; CHECK-LABEL: masked_ld1b_i8_sext:66; CHECK: // %bb.0:67; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]68; CHECK-NEXT: sunpklo z1.h, z0.b69; CHECK-NEXT: sunpkhi z0.h, z0.b70; CHECK-NEXT: sunpklo z2.s, z1.h71; CHECK-NEXT: sunpkhi z3.s, z1.h72; CHECK-NEXT: sunpklo z5.s, z0.h73; CHECK-NEXT: sunpkhi z7.s, z0.h74; CHECK-NEXT: sunpklo z0.d, z2.s75; CHECK-NEXT: sunpkhi z1.d, z2.s76; CHECK-NEXT: sunpklo z2.d, z3.s77; CHECK-NEXT: sunpkhi z3.d, z3.s78; CHECK-NEXT: sunpklo z4.d, z5.s79; CHECK-NEXT: sunpkhi z5.d, z5.s80; CHECK-NEXT: sunpklo z6.d, z7.s81; CHECK-NEXT: sunpkhi z7.d, z7.s82; CHECK-NEXT: ret83 %wide.masked.load = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0(ptr %base, i32 2, <vscale x 16 x i1> %mask, <vscale x 16 x i8> poison)84 %res = sext <vscale x 16 x i8> %wide.masked.load to <vscale x 16 x i64>85 ret <vscale x 16 x i64> %res86}87 88define <vscale x 4 x i64> @masked_ld1b_nxv4i8_sext_i64(ptr %a, <vscale x 4 x i1> %mask) {89; CHECK-LABEL: masked_ld1b_nxv4i8_sext_i64:90; CHECK: // %bb.0:91; CHECK-NEXT: ld1sb { z1.s }, p0/z, [x0]92; CHECK-NEXT: sunpklo z0.d, z1.s93; CHECK-NEXT: sunpkhi z1.d, z1.s94; CHECK-NEXT: ret95 %wide.masked.load = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8.p0(ptr %a, i32 1, <vscale x 4 x i1> %mask, <vscale x 4 x i8> poison)96 %res = sext <vscale x 4 x i8> %wide.masked.load to <vscale x 4 x i64>97 ret <vscale x 4 x i64> %res98}99 100define <vscale x 16 x i64> @masked_ld1b_i8_zext(ptr %base, <vscale x 16 x i1> %mask) {101; CHECK-LABEL: masked_ld1b_i8_zext:102; CHECK: // %bb.0:103; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]104; CHECK-NEXT: uunpklo z1.h, z0.b105; CHECK-NEXT: uunpkhi z0.h, z0.b106; CHECK-NEXT: uunpklo z2.s, z1.h107; CHECK-NEXT: uunpkhi z3.s, z1.h108; CHECK-NEXT: uunpklo z5.s, z0.h109; CHECK-NEXT: uunpkhi z7.s, z0.h110; CHECK-NEXT: uunpklo z0.d, z2.s111; CHECK-NEXT: uunpkhi z1.d, z2.s112; CHECK-NEXT: uunpklo z2.d, z3.s113; CHECK-NEXT: uunpkhi z3.d, z3.s114; CHECK-NEXT: uunpklo z4.d, z5.s115; CHECK-NEXT: uunpkhi z5.d, z5.s116; CHECK-NEXT: uunpklo z6.d, z7.s117; CHECK-NEXT: uunpkhi z7.d, z7.s118; CHECK-NEXT: ret119 %wide.masked.load = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0(ptr %base, i32 2, <vscale x 16 x i1> %mask, <vscale x 16 x i8> poison)120 %res = zext <vscale x 16 x i8> %wide.masked.load to <vscale x 16 x i64>121 ret <vscale x 16 x i64> %res122}123 124define <vscale x 4 x i64> @masked_ld1b_nxv4i8_zext_i64(ptr %a, <vscale x 4 x i1> %mask) {125; CHECK-LABEL: masked_ld1b_nxv4i8_zext_i64:126; CHECK: // %bb.0:127; CHECK-NEXT: ld1b { z1.s }, p0/z, [x0]128; CHECK-NEXT: uunpklo z0.d, z1.s129; CHECK-NEXT: uunpkhi z1.d, z1.s130; CHECK-NEXT: ret131 %wide.masked.load = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8.p0(ptr %a, i32 1, <vscale x 4 x i1> %mask, <vscale x 4 x i8> poison)132 %res = zext <vscale x 4 x i8> %wide.masked.load to <vscale x 4 x i64>133 ret <vscale x 4 x i64> %res134}135 136;137; LD1H138;139 140define <vscale x 8 x i64> @masked_ld1h_i16_sext(ptr %base, <vscale x 8 x i1> %mask) {141; CHECK-LABEL: masked_ld1h_i16_sext:142; CHECK: // %bb.0:143; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]144; CHECK-NEXT: sunpklo z1.s, z0.h145; CHECK-NEXT: sunpkhi z3.s, z0.h146; CHECK-NEXT: sunpklo z0.d, z1.s147; CHECK-NEXT: sunpkhi z1.d, z1.s148; CHECK-NEXT: sunpklo z2.d, z3.s149; CHECK-NEXT: sunpkhi z3.d, z3.s150; CHECK-NEXT: ret151 %wide.masked.load = call <vscale x 8 x i16> @llvm.masked.load.nxv8i16.p0(ptr %base, i32 2, <vscale x 8 x i1> %mask, <vscale x 8 x i16> poison)152 %res = sext <vscale x 8 x i16> %wide.masked.load to <vscale x 8 x i64>153 ret <vscale x 8 x i64> %res154}155 156define <vscale x 4 x i64> @masked_ld1h_nxv4i16_sext(ptr %a, <vscale x 4 x i1> %mask) {157; CHECK-LABEL: masked_ld1h_nxv4i16_sext:158; CHECK: // %bb.0:159; CHECK-NEXT: ld1sh { z1.s }, p0/z, [x0]160; CHECK-NEXT: sunpklo z0.d, z1.s161; CHECK-NEXT: sunpkhi z1.d, z1.s162; CHECK-NEXT: ret163 %wide.masked.load = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16.p0(ptr %a, i32 1, <vscale x 4 x i1> %mask, <vscale x 4 x i16> poison)164 %res = sext <vscale x 4 x i16> %wide.masked.load to <vscale x 4 x i64>165 ret <vscale x 4 x i64> %res166}167 168define <vscale x 8 x i64> @masked_ld1h_i16_zext(ptr %base, <vscale x 8 x i1> %mask) {169; CHECK-LABEL: masked_ld1h_i16_zext:170; CHECK: // %bb.0:171; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]172; CHECK-NEXT: uunpklo z1.s, z0.h173; CHECK-NEXT: uunpkhi z3.s, z0.h174; CHECK-NEXT: uunpklo z0.d, z1.s175; CHECK-NEXT: uunpkhi z1.d, z1.s176; CHECK-NEXT: uunpklo z2.d, z3.s177; CHECK-NEXT: uunpkhi z3.d, z3.s178; CHECK-NEXT: ret179 %wide.masked.load = call <vscale x 8 x i16> @llvm.masked.load.nxv8i16.p0(ptr %base, i32 2, <vscale x 8 x i1> %mask, <vscale x 8 x i16> poison)180 %res = zext <vscale x 8 x i16> %wide.masked.load to <vscale x 8 x i64>181 ret <vscale x 8 x i64> %res182}183 184define <vscale x 4 x i64> @masked_ld1h_nxv4i16_zext(ptr %a, <vscale x 4 x i1> %mask) {185; CHECK-LABEL: masked_ld1h_nxv4i16_zext:186; CHECK: // %bb.0:187; CHECK-NEXT: ld1h { z1.s }, p0/z, [x0]188; CHECK-NEXT: uunpklo z0.d, z1.s189; CHECK-NEXT: uunpkhi z1.d, z1.s190; CHECK-NEXT: ret191 %wide.masked.load = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16.p0(ptr %a, i32 1, <vscale x 4 x i1> %mask, <vscale x 4 x i16> poison)192 %res = zext <vscale x 4 x i16> %wide.masked.load to <vscale x 4 x i64>193 ret <vscale x 4 x i64> %res194}195 196;197; LD1W198;199 200define <vscale x 4 x i64> @masked_ld1w_i32_sext(ptr %base, <vscale x 4 x i1> %mask) {201; CHECK-LABEL: masked_ld1w_i32_sext:202; CHECK: // %bb.0:203; CHECK-NEXT: ld1w { z1.s }, p0/z, [x0]204; CHECK-NEXT: sunpklo z0.d, z1.s205; CHECK-NEXT: sunpkhi z1.d, z1.s206; CHECK-NEXT: ret207 %wide.masked.load = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0(ptr %base, i32 4, <vscale x 4 x i1> %mask, <vscale x 4 x i32> poison)208 %res = sext <vscale x 4 x i32> %wide.masked.load to <vscale x 4 x i64>209 ret <vscale x 4 x i64> %res210}211 212define <vscale x 4 x i64> @masked_ld1w_i32_zext(ptr %base, <vscale x 4 x i1> %mask) {213; CHECK-LABEL: masked_ld1w_i32_zext:214; CHECK: // %bb.0:215; CHECK-NEXT: ld1w { z1.s }, p0/z, [x0]216; CHECK-NEXT: uunpklo z0.d, z1.s217; CHECK-NEXT: uunpkhi z1.d, z1.s218; CHECK-NEXT: ret219 %wide.masked.load = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0(ptr %base, i32 4, <vscale x 4 x i1> %mask, <vscale x 4 x i32> poison)220 %res = zext <vscale x 4 x i32> %wide.masked.load to <vscale x 4 x i64>221 ret <vscale x 4 x i64> %res222}223 224declare <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0(ptr, i32 immarg, <vscale x 16 x i1>, <vscale x 16 x i8>)225declare <vscale x 8 x i8> @llvm.masked.load.nxv8i8.p0(ptr, i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i8>)226declare <vscale x 4 x i8> @llvm.masked.load.nxv4i8.p0(ptr, i32 immarg, <vscale x 4 x i1>, <vscale x 4 x i8>)227declare <vscale x 8 x i16> @llvm.masked.load.nxv8i16.p0(ptr, i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i16>)228declare <vscale x 4 x i16> @llvm.masked.load.nxv4i16.p0(ptr, i32 immarg, <vscale x 4 x i1>, <vscale x 4 x i16>)229declare <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0(ptr, i32 immarg, <vscale x 4 x i1>, <vscale x 4 x i32>)230