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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+sve,+i8mm < %s -o - | FileCheck %s3 4define <vscale x 4 x i32> @smmla(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) nounwind {5; CHECK-LABEL: smmla:6; CHECK: // %bb.0: // %entry7; CHECK-NEXT: smmla z0.s, z1.b, z2.b8; CHECK-NEXT: ret9entry:10 %val = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smmla.nxv4i32(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)11 ret <vscale x 4 x i32> %val12}13 14define <vscale x 4 x i32> @ummla(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) nounwind {15; CHECK-LABEL: ummla:16; CHECK: // %bb.0: // %entry17; CHECK-NEXT: ummla z0.s, z1.b, z2.b18; CHECK-NEXT: ret19entry:20 %val = tail call <vscale x 4 x i32> @llvm.aarch64.sve.ummla.nxv4i32(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)21 ret <vscale x 4 x i32> %val22}23 24define <vscale x 4 x i32> @usmmla(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) nounwind {25; CHECK-LABEL: usmmla:26; CHECK: // %bb.0: // %entry27; CHECK-NEXT: usmmla z0.s, z1.b, z2.b28; CHECK-NEXT: ret29entry:30 %val = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usmmla.nxv4i32(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)31 ret <vscale x 4 x i32> %val32}33 34define <vscale x 4 x i32> @usdot(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) nounwind {35; CHECK-LABEL: usdot:36; CHECK: // %bb.0: // %entry37; CHECK-NEXT: usdot z0.s, z1.b, z2.b38; CHECK-NEXT: ret39entry:40 %val = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)41 ret <vscale x 4 x i32> %val42}43 44define <vscale x 4 x i32> @usdot_lane_0(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) nounwind {45; CHECK-LABEL: usdot_lane_0:46; CHECK: // %bb.0: // %entry47; CHECK-NEXT: usdot z0.s, z1.b, z2.b[0]48; CHECK-NEXT: ret49entry:50 %val = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 0)51 ret <vscale x 4 x i32> %val52}53 54define <vscale x 4 x i32> @usdot_lane_1(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) nounwind {55; CHECK-LABEL: usdot_lane_1:56; CHECK: // %bb.0: // %entry57; CHECK-NEXT: usdot z0.s, z1.b, z2.b[1]58; CHECK-NEXT: ret59entry:60 %val = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 1)61 ret <vscale x 4 x i32> %val62}63 64define <vscale x 4 x i32> @usdot_lane_2(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) nounwind {65; CHECK-LABEL: usdot_lane_2:66; CHECK: // %bb.0: // %entry67; CHECK-NEXT: usdot z0.s, z1.b, z2.b[2]68; CHECK-NEXT: ret69entry:70 %val = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 2)71 ret <vscale x 4 x i32> %val72}73 74define <vscale x 4 x i32> @usdot_lane_3(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) nounwind {75; CHECK-LABEL: usdot_lane_3:76; CHECK: // %bb.0: // %entry77; CHECK-NEXT: usdot z0.s, z1.b, z2.b[3]78; CHECK-NEXT: ret79entry:80 %val = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 3)81 ret <vscale x 4 x i32> %val82}83 84define <vscale x 4 x i32> @sudot_lane_0(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) nounwind {85; CHECK-LABEL: sudot_lane_0:86; CHECK: // %bb.0: // %entry87; CHECK-NEXT: sudot z0.s, z1.b, z2.b[0]88; CHECK-NEXT: ret89entry:90 %val = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 0)91 ret <vscale x 4 x i32> %val92}93 94define <vscale x 4 x i32> @sudot_lane_1(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) nounwind {95; CHECK-LABEL: sudot_lane_1:96; CHECK: // %bb.0: // %entry97; CHECK-NEXT: sudot z0.s, z1.b, z2.b[1]98; CHECK-NEXT: ret99entry:100 %val = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 1)101 ret <vscale x 4 x i32> %val102}103 104define <vscale x 4 x i32> @sudot_lane_2(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) nounwind {105; CHECK-LABEL: sudot_lane_2:106; CHECK: // %bb.0: // %entry107; CHECK-NEXT: sudot z0.s, z1.b, z2.b[2]108; CHECK-NEXT: ret109entry:110 %val = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 2)111 ret <vscale x 4 x i32> %val112}113 114define <vscale x 4 x i32> @sudot_lane_3(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) nounwind {115; CHECK-LABEL: sudot_lane_3:116; CHECK: // %bb.0: // %entry117; CHECK-NEXT: sudot z0.s, z1.b, z2.b[3]118; CHECK-NEXT: ret119entry:120 %val = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 3)121 ret <vscale x 4 x i32> %val122}123 124 125declare <vscale x 4 x i32> @llvm.aarch64.sve.smmla.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>)126declare <vscale x 4 x i32> @llvm.aarch64.sve.ummla.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>)127declare <vscale x 4 x i32> @llvm.aarch64.sve.usmmla.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>)128 129declare <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>)130declare <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32)131declare <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32)132 133