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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s4 5;6; RBIT7;8 9define <vscale x 16 x i8> @rbit_i8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %b) {10; CHECK-LABEL: rbit_i8:11; CHECK: // %bb.0:12; CHECK-NEXT: rbit z0.b, p0/m, z1.b13; CHECK-NEXT: ret14 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8> %a,15 <vscale x 16 x i1> %pg,16 <vscale x 16 x i8> %b)17 ret <vscale x 16 x i8> %out18}19 20define <vscale x 8 x i16> @rbit_i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %b) {21; CHECK-LABEL: rbit_i16:22; CHECK: // %bb.0:23; CHECK-NEXT: rbit z0.h, p0/m, z1.h24; CHECK-NEXT: ret25 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16> %a,26 <vscale x 8 x i1> %pg,27 <vscale x 8 x i16> %b)28 ret <vscale x 8 x i16> %out29}30 31define <vscale x 4 x i32> @rbit_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b) {32; CHECK-LABEL: rbit_i32:33; CHECK: // %bb.0:34; CHECK-NEXT: rbit z0.s, p0/m, z1.s35; CHECK-NEXT: ret36 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32> %a,37 <vscale x 4 x i1> %pg,38 <vscale x 4 x i32> %b)39 ret <vscale x 4 x i32> %out40}41 42define <vscale x 2 x i64> @rbit_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b) {43; CHECK-LABEL: rbit_i64:44; CHECK: // %bb.0:45; CHECK-NEXT: rbit z0.d, p0/m, z1.d46; CHECK-NEXT: ret47 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.rbit.nxv2i64(<vscale x 2 x i64> %a,48 <vscale x 2 x i1> %pg,49 <vscale x 2 x i64> %b)50 ret <vscale x 2 x i64> %out51}52 53;54; REVB55;56 57define <vscale x 8 x i16> @revb_i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %b) {58; CHECK-LABEL: revb_i16:59; CHECK: // %bb.0:60; CHECK-NEXT: revb z0.h, p0/m, z1.h61; CHECK-NEXT: ret62 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> %a,63 <vscale x 8 x i1> %pg,64 <vscale x 8 x i16> %b)65 ret <vscale x 8 x i16> %out66}67 68define <vscale x 4 x i32> @revb_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b) {69; CHECK-LABEL: revb_i32:70; CHECK: // %bb.0:71; CHECK-NEXT: revb z0.s, p0/m, z1.s72; CHECK-NEXT: ret73 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> %a,74 <vscale x 4 x i1> %pg,75 <vscale x 4 x i32> %b)76 ret <vscale x 4 x i32> %out77}78 79define <vscale x 2 x i64> @revb_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b) {80; CHECK-LABEL: revb_i64:81; CHECK: // %bb.0:82; CHECK-NEXT: revb z0.d, p0/m, z1.d83; CHECK-NEXT: ret84 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64> %a,85 <vscale x 2 x i1> %pg,86 <vscale x 2 x i64> %b)87 ret <vscale x 2 x i64> %out88}89 90;91; REVH92;93 94define <vscale x 4 x i32> @revh_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b) {95; CHECK-LABEL: revh_i32:96; CHECK: // %bb.0:97; CHECK-NEXT: revh z0.s, p0/m, z1.s98; CHECK-NEXT: ret99 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> %a,100 <vscale x 4 x i1> %pg,101 <vscale x 4 x i32> %b)102 ret <vscale x 4 x i32> %out103}104 105define <vscale x 2 x i64> @revh_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b) {106; CHECK-LABEL: revh_i64:107; CHECK: // %bb.0:108; CHECK-NEXT: revh z0.d, p0/m, z1.d109; CHECK-NEXT: ret110 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> %a,111 <vscale x 2 x i1> %pg,112 <vscale x 2 x i64> %b)113 ret <vscale x 2 x i64> %out114}115 116;117; REVW118;119 120define <vscale x 2 x i64> @revw_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b) {121; CHECK-LABEL: revw_i64:122; CHECK: // %bb.0:123; CHECK-NEXT: revw z0.d, p0/m, z1.d124; CHECK-NEXT: ret125 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> %a,126 <vscale x 2 x i1> %pg,127 <vscale x 2 x i64> %b)128 ret <vscale x 2 x i64> %out129}130 131declare <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>)132declare <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>)133declare <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)134declare <vscale x 2 x i64> @llvm.aarch64.sve.rbit.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)135 136declare <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>)137declare <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)138declare <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)139 140declare <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)141declare <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)142 143declare <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)144