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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4;5; ST1B, ST1W, ST1H, ST1D: base + 32-bit unscaled offset, sign (sxtw) or zero6; (uxtw) extended to 64 bits.7; e.g. st1h { z0.d }, p0, [x0, z1.d, uxtw]8;9 10; ST1B11define void @sst1b_s_uxtw(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %offsets) {12; CHECK-LABEL: sst1b_s_uxtw:13; CHECK: // %bb.0:14; CHECK-NEXT: st1b { z0.s }, p0, [x0, z1.s, uxtw]15; CHECK-NEXT: ret16 %data_trunc = trunc <vscale x 4 x i32> %data to <vscale x 4 x i8>17 call void @llvm.aarch64.sve.st1.scatter.uxtw.nxv4i8(<vscale x 4 x i8> %data_trunc,18 <vscale x 4 x i1> %pg,19 ptr %base,20 <vscale x 4 x i32> %offsets)21 ret void22}23 24define void @sst1b_s_sxtw(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %offsets) {25; CHECK-LABEL: sst1b_s_sxtw:26; CHECK: // %bb.0:27; CHECK-NEXT: st1b { z0.s }, p0, [x0, z1.s, sxtw]28; CHECK-NEXT: ret29 %data_trunc = trunc <vscale x 4 x i32> %data to <vscale x 4 x i8>30 call void @llvm.aarch64.sve.st1.scatter.sxtw.nxv4i8(<vscale x 4 x i8> %data_trunc,31 <vscale x 4 x i1> %pg,32 ptr %base,33 <vscale x 4 x i32> %offsets)34 ret void35}36 37define void @sst1b_d_uxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %offsets) {38; CHECK-LABEL: sst1b_d_uxtw:39; CHECK: // %bb.0:40; CHECK-NEXT: st1b { z0.d }, p0, [x0, z1.d, uxtw]41; CHECK-NEXT: ret42 %data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i8>43 call void @llvm.aarch64.sve.st1.scatter.uxtw.nxv2i8(<vscale x 2 x i8> %data_trunc,44 <vscale x 2 x i1> %pg,45 ptr %base,46 <vscale x 2 x i32> %offsets)47 ret void48}49 50define void @sst1b_d_sxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %offsets) {51; CHECK-LABEL: sst1b_d_sxtw:52; CHECK: // %bb.0:53; CHECK-NEXT: st1b { z0.d }, p0, [x0, z1.d, sxtw]54; CHECK-NEXT: ret55 %data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i8>56 call void @llvm.aarch64.sve.st1.scatter.sxtw.nxv2i8(<vscale x 2 x i8> %data_trunc,57 <vscale x 2 x i1> %pg,58 ptr %base,59 <vscale x 2 x i32> %offsets)60 ret void61}62 63; ST1H64define void @sst1h_s_uxtw(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %offsets) {65; CHECK-LABEL: sst1h_s_uxtw:66; CHECK: // %bb.0:67; CHECK-NEXT: st1h { z0.s }, p0, [x0, z1.s, uxtw]68; CHECK-NEXT: ret69 %data_trunc = trunc <vscale x 4 x i32> %data to <vscale x 4 x i16>70 call void @llvm.aarch64.sve.st1.scatter.uxtw.nxv4i16(<vscale x 4 x i16> %data_trunc,71 <vscale x 4 x i1> %pg,72 ptr %base,73 <vscale x 4 x i32> %offsets)74 ret void75}76 77define void @sst1h_s_sxtw(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %offsets) {78; CHECK-LABEL: sst1h_s_sxtw:79; CHECK: // %bb.0:80; CHECK-NEXT: st1h { z0.s }, p0, [x0, z1.s, sxtw]81; CHECK-NEXT: ret82 %data_trunc = trunc <vscale x 4 x i32> %data to <vscale x 4 x i16>83 call void @llvm.aarch64.sve.st1.scatter.sxtw.nxv4i16(<vscale x 4 x i16> %data_trunc,84 <vscale x 4 x i1> %pg,85 ptr %base,86 <vscale x 4 x i32> %offsets)87 ret void88}89 90define void @sst1h_d_uxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %offsets) {91; CHECK-LABEL: sst1h_d_uxtw:92; CHECK: // %bb.0:93; CHECK-NEXT: st1h { z0.d }, p0, [x0, z1.d, uxtw]94; CHECK-NEXT: ret95 %data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16>96 call void @llvm.aarch64.sve.st1.scatter.uxtw.nxv2i16(<vscale x 2 x i16> %data_trunc,97 <vscale x 2 x i1> %pg,98 ptr %base,99 <vscale x 2 x i32> %offsets)100 ret void101}102 103define void @sst1h_d_sxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %offsets) {104; CHECK-LABEL: sst1h_d_sxtw:105; CHECK: // %bb.0:106; CHECK-NEXT: st1h { z0.d }, p0, [x0, z1.d, sxtw]107; CHECK-NEXT: ret108 %data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16>109 call void @llvm.aarch64.sve.st1.scatter.sxtw.nxv2i16(<vscale x 2 x i16> %data_trunc,110 <vscale x 2 x i1> %pg,111 ptr %base,112 <vscale x 2 x i32> %offsets)113 ret void114}115 116; ST1W117define void @sst1w_s_uxtw(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %offsets) {118; CHECK-LABEL: sst1w_s_uxtw:119; CHECK: // %bb.0:120; CHECK-NEXT: st1w { z0.s }, p0, [x0, z1.s, uxtw]121; CHECK-NEXT: ret122 call void @llvm.aarch64.sve.st1.scatter.uxtw.nxv4i32(<vscale x 4 x i32> %data,123 <vscale x 4 x i1> %pg,124 ptr %base,125 <vscale x 4 x i32> %offsets)126 ret void127}128 129define void @sst1w_s_sxtw(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %offsets) {130; CHECK-LABEL: sst1w_s_sxtw:131; CHECK: // %bb.0:132; CHECK-NEXT: st1w { z0.s }, p0, [x0, z1.s, sxtw]133; CHECK-NEXT: ret134 call void @llvm.aarch64.sve.st1.scatter.sxtw.nxv4i32(<vscale x 4 x i32> %data,135 <vscale x 4 x i1> %pg,136 ptr %base,137 <vscale x 4 x i32> %offsets)138 ret void139}140 141define void @sst1w_d_uxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %offsets) {142; CHECK-LABEL: sst1w_d_uxtw:143; CHECK: // %bb.0:144; CHECK-NEXT: st1w { z0.d }, p0, [x0, z1.d, uxtw]145; CHECK-NEXT: ret146 %data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32>147 call void @llvm.aarch64.sve.st1.scatter.uxtw.nxv2i32(<vscale x 2 x i32> %data_trunc,148 <vscale x 2 x i1> %pg,149 ptr %base,150 <vscale x 2 x i32> %offsets)151 ret void152}153 154define void @sst1w_d_sxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %offsets) {155; CHECK-LABEL: sst1w_d_sxtw:156; CHECK: // %bb.0:157; CHECK-NEXT: st1w { z0.d }, p0, [x0, z1.d, sxtw]158; CHECK-NEXT: ret159 %data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32>160 call void @llvm.aarch64.sve.st1.scatter.sxtw.nxv2i32(<vscale x 2 x i32> %data_trunc,161 <vscale x 2 x i1> %pg,162 ptr %base,163 <vscale x 2 x i32> %offsets)164 ret void165}166 167define void @sst1w_s_uxtw_float(<vscale x 4 x float> %data, <vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %offsets) {168; CHECK-LABEL: sst1w_s_uxtw_float:169; CHECK: // %bb.0:170; CHECK-NEXT: st1w { z0.s }, p0, [x0, z1.s, uxtw]171; CHECK-NEXT: ret172 call void @llvm.aarch64.sve.st1.scatter.uxtw.nxv4f32(<vscale x 4 x float> %data,173 <vscale x 4 x i1> %pg,174 ptr %base,175 <vscale x 4 x i32> %offsets)176 ret void177}178 179define void @sst1w_s_sxtw_float(<vscale x 4 x float> %data, <vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %offsets) {180; CHECK-LABEL: sst1w_s_sxtw_float:181; CHECK: // %bb.0:182; CHECK-NEXT: st1w { z0.s }, p0, [x0, z1.s, sxtw]183; CHECK-NEXT: ret184 call void @llvm.aarch64.sve.st1.scatter.sxtw.nxv4f32(<vscale x 4 x float> %data,185 <vscale x 4 x i1> %pg,186 ptr %base,187 <vscale x 4 x i32> %offsets)188 ret void189}190 191; ST1D192define void @sst1d_d_uxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %offsets) {193; CHECK-LABEL: sst1d_d_uxtw:194; CHECK: // %bb.0:195; CHECK-NEXT: st1d { z0.d }, p0, [x0, z1.d, uxtw]196; CHECK-NEXT: ret197 call void @llvm.aarch64.sve.st1.scatter.uxtw.nxv2i64(<vscale x 2 x i64> %data,198 <vscale x 2 x i1> %pg,199 ptr %base,200 <vscale x 2 x i32> %offsets)201 ret void202}203 204define void @sst1d_d_sxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %offsets) {205; CHECK-LABEL: sst1d_d_sxtw:206; CHECK: // %bb.0:207; CHECK-NEXT: st1d { z0.d }, p0, [x0, z1.d, sxtw]208; CHECK-NEXT: ret209 call void @llvm.aarch64.sve.st1.scatter.sxtw.nxv2i64(<vscale x 2 x i64> %data,210 <vscale x 2 x i1> %pg,211 ptr %base,212 <vscale x 2 x i32> %offsets)213 ret void214}215 216define void @sst1d_d_uxtw_double(<vscale x 2 x double> %data, <vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %offsets) {217; CHECK-LABEL: sst1d_d_uxtw_double:218; CHECK: // %bb.0:219; CHECK-NEXT: st1d { z0.d }, p0, [x0, z1.d, uxtw]220; CHECK-NEXT: ret221 call void @llvm.aarch64.sve.st1.scatter.uxtw.nxv2f64(<vscale x 2 x double> %data,222 <vscale x 2 x i1> %pg,223 ptr %base,224 <vscale x 2 x i32> %offsets)225 ret void226}227 228define void @sst1d_d_sxtw_double(<vscale x 2 x double> %data, <vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %offsets) {229; CHECK-LABEL: sst1d_d_sxtw_double:230; CHECK: // %bb.0:231; CHECK-NEXT: st1d { z0.d }, p0, [x0, z1.d, sxtw]232; CHECK-NEXT: ret233 call void @llvm.aarch64.sve.st1.scatter.sxtw.nxv2f64(<vscale x 2 x double> %data,234 <vscale x 2 x i1> %pg,235 ptr %base,236 <vscale x 2 x i32> %offsets)237 ret void238}239 240 241; ST1B242declare void @llvm.aarch64.sve.st1.scatter.uxtw.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i1>, ptr, <vscale x 4 x i32>)243declare void @llvm.aarch64.sve.st1.scatter.uxtw.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i1>, ptr, <vscale x 2 x i32>)244declare void @llvm.aarch64.sve.st1.scatter.sxtw.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i1>, ptr, <vscale x 4 x i32>)245declare void @llvm.aarch64.sve.st1.scatter.sxtw.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i1>, ptr, <vscale x 2 x i32>)246 247; ST1H248declare void @llvm.aarch64.sve.st1.scatter.sxtw.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i1>, ptr, <vscale x 4 x i32>)249declare void @llvm.aarch64.sve.st1.scatter.sxtw.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, ptr, <vscale x 2 x i32>)250declare void @llvm.aarch64.sve.st1.scatter.uxtw.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i1>, ptr, <vscale x 4 x i32>)251declare void @llvm.aarch64.sve.st1.scatter.uxtw.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, ptr, <vscale x 2 x i32>)252 253; ST1W254declare void @llvm.aarch64.sve.st1.scatter.sxtw.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, ptr, <vscale x 4 x i32>)255declare void @llvm.aarch64.sve.st1.scatter.sxtw.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, ptr, <vscale x 2 x i32>)256declare void @llvm.aarch64.sve.st1.scatter.uxtw.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, ptr, <vscale x 4 x i32>)257declare void @llvm.aarch64.sve.st1.scatter.uxtw.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, ptr, <vscale x 2 x i32>)258 259declare void @llvm.aarch64.sve.st1.scatter.sxtw.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, ptr, <vscale x 4 x i32>)260declare void @llvm.aarch64.sve.st1.scatter.uxtw.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, ptr, <vscale x 4 x i32>)261 262; ST1D263declare void @llvm.aarch64.sve.st1.scatter.sxtw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, ptr, <vscale x 2 x i32>)264declare void @llvm.aarch64.sve.st1.scatter.uxtw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, ptr, <vscale x 2 x i32>)265 266declare void @llvm.aarch64.sve.st1.scatter.sxtw.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, ptr, <vscale x 2 x i32>)267declare void @llvm.aarch64.sve.st1.scatter.uxtw.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, ptr, <vscale x 2 x i32>)268