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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s4 5;6; SEL (Vectors)7;8 9define <vscale x 16 x i1> @sel_i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {10; CHECK-LABEL: sel_i1:11; CHECK: // %bb.0:12; CHECK-NEXT: sel p0.b, p0, p1.b, p2.b13; CHECK-NEXT: ret14 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.sel.nxv16i1(<vscale x 16 x i1> %pg,15 <vscale x 16 x i1> %a,16 <vscale x 16 x i1> %b)17 ret <vscale x 16 x i1> %out18}19 20define <vscale x 16 x i8> @sel_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {21; CHECK-LABEL: sel_i8:22; CHECK: // %bb.0:23; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b24; CHECK-NEXT: ret25 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg,26 <vscale x 16 x i8> %a,27 <vscale x 16 x i8> %b)28 ret <vscale x 16 x i8> %out29}30 31define <vscale x 8 x i16> @sel_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {32; CHECK-LABEL: sel_i16:33; CHECK: // %bb.0:34; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h35; CHECK-NEXT: ret36 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %pg,37 <vscale x 8 x i16> %a,38 <vscale x 8 x i16> %b)39 ret <vscale x 8 x i16> %out40}41 42define <vscale x 4 x i32> @sel_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {43; CHECK-LABEL: sel_i32:44; CHECK: // %bb.0:45; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s46; CHECK-NEXT: ret47 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %pg,48 <vscale x 4 x i32> %a,49 <vscale x 4 x i32> %b)50 ret <vscale x 4 x i32> %out51}52 53define <vscale x 2 x i64> @sel_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {54; CHECK-LABEL: sel_i64:55; CHECK: // %bb.0:56; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d57; CHECK-NEXT: ret58 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %pg,59 <vscale x 2 x i64> %a,60 <vscale x 2 x i64> %b)61 ret <vscale x 2 x i64> %out62}63 64define <vscale x 8 x bfloat> @sel_bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) #0 {65; CHECK-LABEL: sel_bf16:66; CHECK: // %bb.0:67; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h68; CHECK-NEXT: ret69 %out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.sel.nxv8bf16(<vscale x 8 x i1> %pg,70 <vscale x 8 x bfloat> %a,71 <vscale x 8 x bfloat> %b)72 ret <vscale x 8 x bfloat> %out73}74 75define <vscale x 8 x half> @sel_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {76; CHECK-LABEL: sel_f16:77; CHECK: // %bb.0:78; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h79; CHECK-NEXT: ret80 %out = call <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1> %pg,81 <vscale x 8 x half> %a,82 <vscale x 8 x half> %b)83 ret <vscale x 8 x half> %out84}85 86define <vscale x 4 x float> @sel_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {87; CHECK-LABEL: sel_f32:88; CHECK: // %bb.0:89; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s90; CHECK-NEXT: ret91 %out = call <vscale x 4 x float> @llvm.aarch64.sve.sel.nxv4f32(<vscale x 4 x i1> %pg,92 <vscale x 4 x float> %a,93 <vscale x 4 x float> %b)94 ret <vscale x 4 x float> %out95}96 97define <vscale x 2 x double> @sel_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {98; CHECK-LABEL: sel_f64:99; CHECK: // %bb.0:100; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d101; CHECK-NEXT: ret102 %out = call <vscale x 2 x double> @llvm.aarch64.sve.sel.nxv2f64(<vscale x 2 x i1> %pg,103 <vscale x 2 x double> %a,104 <vscale x 2 x double> %b)105 ret <vscale x 2 x double> %out106}107 108declare <vscale x 16 x i1> @llvm.aarch64.sve.sel.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)109declare <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)110declare <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)111declare <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)112declare <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)113declare <vscale x 8 x bfloat> @llvm.aarch64.sve.sel.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)114declare <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)115declare <vscale x 4 x float> @llvm.aarch64.sve.sel.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)116declare <vscale x 2 x double> @llvm.aarch64.sve.sel.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)117 118; +bf16 is required for the bfloat version.119attributes #0 = { "target-features"="+bf16" }120