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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s4 5; Since SQDEC{B|H|W|D|P} and SQINC{B|H|W|D|P} have identical semantics, the tests for6; * @llvm.aarch64.sve.sqinc{b|h|w|d|p}, and7; * @llvm.aarch64.sve.sqdec{b|h|w|d|p}8; should also be identical (with the instruction name being adjusted). When9; updating this file remember to make similar changes in the file testing the10; other intrinsic.11 12;13; SQINCH (vector)14;15 16define <vscale x 8 x i16> @sqinch(<vscale x 8 x i16> %a) {17; CHECK-LABEL: sqinch:18; CHECK: // %bb.0:19; CHECK-NEXT: sqinch z0.h, pow220; CHECK-NEXT: ret21 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqinch.nxv8i16(<vscale x 8 x i16> %a,22 i32 0, i32 1)23 ret <vscale x 8 x i16> %out24}25 26;27; SQINCW (vector)28;29 30define <vscale x 4 x i32> @sqincw(<vscale x 4 x i32> %a) {31; CHECK-LABEL: sqincw:32; CHECK: // %bb.0:33; CHECK-NEXT: sqincw z0.s, vl1, mul #234; CHECK-NEXT: ret35 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqincw.nxv4i32(<vscale x 4 x i32> %a,36 i32 1, i32 2)37 ret <vscale x 4 x i32> %out38}39 40;41; SQINCD (vector)42;43 44define <vscale x 2 x i64> @sqincd(<vscale x 2 x i64> %a) {45; CHECK-LABEL: sqincd:46; CHECK: // %bb.0:47; CHECK-NEXT: sqincd z0.d, vl2, mul #348; CHECK-NEXT: ret49 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqincd.nxv2i64(<vscale x 2 x i64> %a,50 i32 2, i32 3)51 ret <vscale x 2 x i64> %out52}53 54;55; SQINCP (vector)56;57 58define <vscale x 8 x i16> @sqincp_b16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %b) {59; CHECK-LABEL: sqincp_b16:60; CHECK: // %bb.0:61; CHECK-NEXT: sqincp z0.h, p0.h62; CHECK-NEXT: ret63 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqincp.nxv8i16(<vscale x 8 x i16> %a,64 <vscale x 8 x i1> %b)65 ret <vscale x 8 x i16> %out66}67 68define <vscale x 4 x i32> @sqincp_b32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b) {69; CHECK-LABEL: sqincp_b32:70; CHECK: // %bb.0:71; CHECK-NEXT: sqincp z0.s, p0.s72; CHECK-NEXT: ret73 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqincp.nxv4i32(<vscale x 4 x i32> %a,74 <vscale x 4 x i1> %b)75 ret <vscale x 4 x i32> %out76}77 78define <vscale x 2 x i64> @sqincp_b64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %b) {79; CHECK-LABEL: sqincp_b64:80; CHECK: // %bb.0:81; CHECK-NEXT: sqincp z0.d, p0.d82; CHECK-NEXT: ret83 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqincp.nxv2i64(<vscale x 2 x i64> %a,84 <vscale x 2 x i1> %b)85 ret <vscale x 2 x i64> %out86}87 88;89; SQINCB (scalar)90;91 92define i32 @sqincb_n32_i32(i32 %a) {93; CHECK-LABEL: sqincb_n32_i32:94; CHECK: // %bb.0:95; CHECK-NEXT: // kill: def $w0 killed $w0 def $x096; CHECK-NEXT: sqincb x0, w0, vl3, mul #497; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x098; CHECK-NEXT: ret99 %out = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %a, i32 3, i32 4)100 ret i32 %out101}102 103define i64 @sqincb_n32_i64(i32 %a) {104; CHECK-LABEL: sqincb_n32_i64:105; CHECK: // %bb.0:106; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0107; CHECK-NEXT: sqincb x0, w0, vl3, mul #4108; CHECK-NEXT: ret109 %out = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %a, i32 3, i32 4)110 %out_sext = sext i32 %out to i64111 112 ret i64 %out_sext113}114 115define i64 @sqincb_n64(i64 %a) {116; CHECK-LABEL: sqincb_n64:117; CHECK: // %bb.0:118; CHECK-NEXT: sqincb x0, vl4, mul #5119; CHECK-NEXT: ret120 %out = call i64 @llvm.aarch64.sve.sqincb.n64(i64 %a, i32 4, i32 5)121 ret i64 %out122}123 124;125; SQINCH (scalar)126;127 128define i32 @sqinch_n32_i32(i32 %a) {129; CHECK-LABEL: sqinch_n32_i32:130; CHECK: // %bb.0:131; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0132; CHECK-NEXT: sqinch x0, w0, vl5, mul #6133; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0134; CHECK-NEXT: ret135 %out = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %a, i32 5, i32 6)136 ret i32 %out137}138 139define i64 @sqinch_n32_i64(i32 %a) {140; CHECK-LABEL: sqinch_n32_i64:141; CHECK: // %bb.0:142; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0143; CHECK-NEXT: sqinch x0, w0, vl3, mul #4144; CHECK-NEXT: ret145 %out = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %a, i32 3, i32 4)146 %out_sext = sext i32 %out to i64147 148 ret i64 %out_sext149}150 151define i64 @sqinch_n64(i64 %a) {152; CHECK-LABEL: sqinch_n64:153; CHECK: // %bb.0:154; CHECK-NEXT: sqinch x0, vl6, mul #7155; CHECK-NEXT: ret156 %out = call i64 @llvm.aarch64.sve.sqinch.n64(i64 %a, i32 6, i32 7)157 ret i64 %out158}159 160;161; SQINCW (scalar)162;163 164define i32 @sqincw_n32_i32(i32 %a) {165; CHECK-LABEL: sqincw_n32_i32:166; CHECK: // %bb.0:167; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0168; CHECK-NEXT: sqincw x0, w0, vl7, mul #8169; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0170; CHECK-NEXT: ret171 %out = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %a, i32 7, i32 8)172 ret i32 %out173}174 175define i64 @sqincw_n32_i64(i32 %a) {176; CHECK-LABEL: sqincw_n32_i64:177; CHECK: // %bb.0:178; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0179; CHECK-NEXT: sqincw x0, w0, vl3, mul #4180; CHECK-NEXT: ret181 %out = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %a, i32 3, i32 4)182 %out_sext = sext i32 %out to i64183 184 ret i64 %out_sext185}186 187define i64 @sqincw_n64(i64 %a) {188; CHECK-LABEL: sqincw_n64:189; CHECK: // %bb.0:190; CHECK-NEXT: sqincw x0, vl8, mul #9191; CHECK-NEXT: ret192 %out = call i64 @llvm.aarch64.sve.sqincw.n64(i64 %a, i32 8, i32 9)193 ret i64 %out194}195 196;197; SQINCD (scalar)198;199 200define i32 @sqincd_n32_i32(i32 %a) {201; CHECK-LABEL: sqincd_n32_i32:202; CHECK: // %bb.0:203; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0204; CHECK-NEXT: sqincd x0, w0, vl16, mul #10205; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0206; CHECK-NEXT: ret207 %out = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %a, i32 9, i32 10)208 ret i32 %out209}210 211define i64 @sqincd_n32_i64(i32 %a) {212; CHECK-LABEL: sqincd_n32_i64:213; CHECK: // %bb.0:214; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0215; CHECK-NEXT: sqincd x0, w0, vl3, mul #4216; CHECK-NEXT: ret217 %out = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %a, i32 3, i32 4)218 %out_sext = sext i32 %out to i64219 220 ret i64 %out_sext221}222 223define i64 @sqincd_n64(i64 %a) {224; CHECK-LABEL: sqincd_n64:225; CHECK: // %bb.0:226; CHECK-NEXT: sqincd x0, vl32, mul #11227; CHECK-NEXT: ret228 %out = call i64 @llvm.aarch64.sve.sqincd.n64(i64 %a, i32 10, i32 11)229 ret i64 %out230}231 232;233; SQINCP (scalar)234;235 236define i32 @sqincp_n32_b8_i32(i32 %a, <vscale x 16 x i1> %b) {237; CHECK-LABEL: sqincp_n32_b8_i32:238; CHECK: // %bb.0:239; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0240; CHECK-NEXT: sqincp x0, p0.b, w0241; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0242; CHECK-NEXT: ret243 %out = call i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32 %a, <vscale x 16 x i1> %b)244 ret i32 %out245}246 247define i64 @sqincp_n32_b8_i64(i32 %a, <vscale x 16 x i1> %b) {248; CHECK-LABEL: sqincp_n32_b8_i64:249; CHECK: // %bb.0:250; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0251; CHECK-NEXT: sqincp x0, p0.b, w0252; CHECK-NEXT: ret253 %out = call i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32 %a, <vscale x 16 x i1> %b)254 %out_sext = sext i32 %out to i64255 256 ret i64 %out_sext257}258 259define i32 @sqincp_n32_b16_i32(i32 %a, <vscale x 8 x i1> %b) {260; CHECK-LABEL: sqincp_n32_b16_i32:261; CHECK: // %bb.0:262; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0263; CHECK-NEXT: sqincp x0, p0.h, w0264; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0265; CHECK-NEXT: ret266 %out = call i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32 %a, <vscale x 8 x i1> %b)267 ret i32 %out268}269 270define i64 @sqincp_n32_b16_i64(i32 %a, <vscale x 8 x i1> %b) {271; CHECK-LABEL: sqincp_n32_b16_i64:272; CHECK: // %bb.0:273; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0274; CHECK-NEXT: sqincp x0, p0.h, w0275; CHECK-NEXT: ret276 %out = call i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32 %a, <vscale x 8 x i1> %b)277 %out_sext = sext i32 %out to i64278 279 ret i64 %out_sext280}281 282define i32 @sqincp_n32_b32_i32(i32 %a, <vscale x 4 x i1> %b) {283; CHECK-LABEL: sqincp_n32_b32_i32:284; CHECK: // %bb.0:285; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0286; CHECK-NEXT: sqincp x0, p0.s, w0287; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0288; CHECK-NEXT: ret289 %out = call i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32 %a, <vscale x 4 x i1> %b)290 ret i32 %out291}292 293define i64 @sqincp_n32_b32_i64(i32 %a, <vscale x 4 x i1> %b) {294; CHECK-LABEL: sqincp_n32_b32_i64:295; CHECK: // %bb.0:296; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0297; CHECK-NEXT: sqincp x0, p0.s, w0298; CHECK-NEXT: ret299 %out = call i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32 %a, <vscale x 4 x i1> %b)300 %out_sext = sext i32 %out to i64301 302 ret i64 %out_sext303}304 305define i32 @sqincp_n32_b64_i32(i32 %a, <vscale x 2 x i1> %b) {306; CHECK-LABEL: sqincp_n32_b64_i32:307; CHECK: // %bb.0:308; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0309; CHECK-NEXT: sqincp x0, p0.d, w0310; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0311; CHECK-NEXT: ret312 %out = call i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32 %a, <vscale x 2 x i1> %b)313 ret i32 %out314}315 316define i64 @sqincp_n32_b64_i64(i32 %a, <vscale x 2 x i1> %b) {317; CHECK-LABEL: sqincp_n32_b64_i64:318; CHECK: // %bb.0:319; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0320; CHECK-NEXT: sqincp x0, p0.d, w0321; CHECK-NEXT: ret322 %out = call i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32 %a, <vscale x 2 x i1> %b)323 %out_sext = sext i32 %out to i64324 325 ret i64 %out_sext326}327 328define i64 @sqincp_n64_b8(i64 %a, <vscale x 16 x i1> %b) {329; CHECK-LABEL: sqincp_n64_b8:330; CHECK: // %bb.0:331; CHECK-NEXT: sqincp x0, p0.b332; CHECK-NEXT: ret333 %out = call i64 @llvm.aarch64.sve.sqincp.n64.nxv16i1(i64 %a, <vscale x 16 x i1> %b)334 ret i64 %out335}336 337define i64 @sqincp_n64_b16(i64 %a, <vscale x 8 x i1> %b) {338; CHECK-LABEL: sqincp_n64_b16:339; CHECK: // %bb.0:340; CHECK-NEXT: sqincp x0, p0.h341; CHECK-NEXT: ret342 %out = call i64 @llvm.aarch64.sve.sqincp.n64.nxv8i1(i64 %a, <vscale x 8 x i1> %b)343 ret i64 %out344}345 346define i64 @sqincp_n64_b32(i64 %a, <vscale x 4 x i1> %b) {347; CHECK-LABEL: sqincp_n64_b32:348; CHECK: // %bb.0:349; CHECK-NEXT: sqincp x0, p0.s350; CHECK-NEXT: ret351 %out = call i64 @llvm.aarch64.sve.sqincp.n64.nxv4i1(i64 %a, <vscale x 4 x i1> %b)352 ret i64 %out353}354 355define i64 @sqincp_n64_b64(i64 %a, <vscale x 2 x i1> %b) {356; CHECK-LABEL: sqincp_n64_b64:357; CHECK: // %bb.0:358; CHECK-NEXT: sqincp x0, p0.d359; CHECK-NEXT: ret360 %out = call i64 @llvm.aarch64.sve.sqincp.n64.nxv2i1(i64 %a, <vscale x 2 x i1> %b)361 ret i64 %out362}363 364; sqinc{h|w|d}(vector, pattern, multiplier)365declare <vscale x 8 x i16> @llvm.aarch64.sve.sqinch.nxv8i16(<vscale x 8 x i16>, i32, i32)366declare <vscale x 4 x i32> @llvm.aarch64.sve.sqincw.nxv4i32(<vscale x 4 x i32>, i32, i32)367declare <vscale x 2 x i64> @llvm.aarch64.sve.sqincd.nxv2i64(<vscale x 2 x i64>, i32, i32)368 369; sqinc{b|h|w|d}(scalar, pattern, multiplier)370declare i32 @llvm.aarch64.sve.sqincb.n32(i32, i32, i32)371declare i64 @llvm.aarch64.sve.sqincb.n64(i64, i32, i32)372declare i32 @llvm.aarch64.sve.sqinch.n32(i32, i32, i32)373declare i64 @llvm.aarch64.sve.sqinch.n64(i64, i32, i32)374declare i32 @llvm.aarch64.sve.sqincw.n32(i32, i32, i32)375declare i64 @llvm.aarch64.sve.sqincw.n64(i64, i32, i32)376declare i32 @llvm.aarch64.sve.sqincd.n32(i32, i32, i32)377declare i64 @llvm.aarch64.sve.sqincd.n64(i64, i32, i32)378 379; sqincp(scalar, predicate)380declare i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32, <vscale x 16 x i1>)381declare i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32, <vscale x 8 x i1>)382declare i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32, <vscale x 4 x i1>)383declare i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32, <vscale x 2 x i1>)384 385declare i64 @llvm.aarch64.sve.sqincp.n64.nxv16i1(i64, <vscale x 16 x i1>)386declare i64 @llvm.aarch64.sve.sqincp.n64.nxv8i1(i64, <vscale x 8 x i1>)387declare i64 @llvm.aarch64.sve.sqincp.n64.nxv4i1(i64, <vscale x 4 x i1>)388declare i64 @llvm.aarch64.sve.sqincp.n64.nxv2i1(i64, <vscale x 2 x i1>)389 390; sqincp(vector, predicate)391declare <vscale x 8 x i16> @llvm.aarch64.sve.sqincp.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>)392declare <vscale x 4 x i32> @llvm.aarch64.sve.sqincp.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>)393declare <vscale x 2 x i64> @llvm.aarch64.sve.sqincp.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>)394