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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s4 5;6; ST1B7;8 9define void @st1b_i8(<vscale x 16 x i8> %data, <vscale x 16 x i1> %pred, ptr %a, i64 %index) {10; CHECK-LABEL: st1b_i8:11; CHECK: // %bb.0:12; CHECK-NEXT: st1b { z0.b }, p0, [x0, x1]13; CHECK-NEXT: ret14 %base = getelementptr i8, ptr %a, i64 %index15 call void @llvm.aarch64.sve.st1.nxv16i8(<vscale x 16 x i8> %data,16 <vscale x 16 x i1> %pred,17 ptr %base)18 ret void19}20 21 22 23define void @st1b_h(<vscale x 8 x i16> %data, <vscale x 8 x i1> %pred, ptr %a, i64 %index) {24; CHECK-LABEL: st1b_h:25; CHECK: // %bb.0:26; CHECK-NEXT: st1b { z0.h }, p0, [x0, x1]27; CHECK-NEXT: ret28 %base = getelementptr i8, ptr %a, i64 %index29 %trunc = trunc <vscale x 8 x i16> %data to <vscale x 8 x i8>30 call void @llvm.aarch64.sve.st1.nxv8i8(<vscale x 8 x i8> %trunc,31 <vscale x 8 x i1> %pred,32 ptr %base)33 ret void34}35 36define void @st1b_s(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pred, ptr %a, i64 %index) {37; CHECK-LABEL: st1b_s:38; CHECK: // %bb.0:39; CHECK-NEXT: st1b { z0.s }, p0, [x0, x1]40; CHECK-NEXT: ret41 %base = getelementptr i8, ptr %a, i64 %index42 %trunc = trunc <vscale x 4 x i32> %data to <vscale x 4 x i8>43 call void @llvm.aarch64.sve.st1.nxv4i8(<vscale x 4 x i8> %trunc,44 <vscale x 4 x i1> %pred,45 ptr %base)46 ret void47}48 49define void @st1b_d(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pred, ptr %a, i64 %index) {50; CHECK-LABEL: st1b_d:51; CHECK: // %bb.0:52; CHECK-NEXT: st1b { z0.d }, p0, [x0, x1]53; CHECK-NEXT: ret54 %base = getelementptr i8, ptr %a, i64 %index55 %trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i8>56 call void @llvm.aarch64.sve.st1.nxv2i8(<vscale x 2 x i8> %trunc,57 <vscale x 2 x i1> %pred,58 ptr %base)59 ret void60}61 62;63; ST1H64;65 66define void @st1h_i16(<vscale x 8 x i16> %data, <vscale x 8 x i1> %pred, ptr %a, i64 %index) {67; CHECK-LABEL: st1h_i16:68; CHECK: // %bb.0:69; CHECK-NEXT: st1h { z0.h }, p0, [x0, x1, lsl #1]70; CHECK-NEXT: ret71 %base = getelementptr i16, ptr %a, i64 %index72 call void @llvm.aarch64.sve.st1.nxv8i16(<vscale x 8 x i16> %data,73 <vscale x 8 x i1> %pred,74 ptr %base)75 ret void76}77 78define void @st1h_f16(<vscale x 8 x half> %data, <vscale x 8 x i1> %pred, ptr %a, i64 %index) {79; CHECK-LABEL: st1h_f16:80; CHECK: // %bb.0:81; CHECK-NEXT: st1h { z0.h }, p0, [x0, x1, lsl #1]82; CHECK-NEXT: ret83 %base = getelementptr half, ptr %a, i64 %index84 call void @llvm.aarch64.sve.st1.nxv8f16(<vscale x 8 x half> %data,85 <vscale x 8 x i1> %pred,86 ptr %base)87 ret void88}89 90define void @st1h_bf16(<vscale x 8 x bfloat> %data, <vscale x 8 x i1> %pred, ptr %a, i64 %index) #0 {91; CHECK-LABEL: st1h_bf16:92; CHECK: // %bb.0:93; CHECK-NEXT: st1h { z0.h }, p0, [x0, x1, lsl #1]94; CHECK-NEXT: ret95 %base = getelementptr bfloat, ptr %a, i64 %index96 call void @llvm.aarch64.sve.st1.nxv8bf16(<vscale x 8 x bfloat> %data,97 <vscale x 8 x i1> %pred,98 ptr %base)99 ret void100}101 102define void @st1h_s(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pred, ptr %addr) {103; CHECK-LABEL: st1h_s:104; CHECK: // %bb.0:105; CHECK-NEXT: st1h { z0.s }, p0, [x0]106; CHECK-NEXT: ret107 %trunc = trunc <vscale x 4 x i32> %data to <vscale x 4 x i16>108 call void @llvm.aarch64.sve.st1.nxv4i16(<vscale x 4 x i16> %trunc,109 <vscale x 4 x i1> %pred,110 ptr %addr)111 ret void112}113 114define void @st1h_d(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pred, ptr %a, i64 %index) {115; CHECK-LABEL: st1h_d:116; CHECK: // %bb.0:117; CHECK-NEXT: st1h { z0.d }, p0, [x0, x1, lsl #1]118; CHECK-NEXT: ret119 %base = getelementptr i16, ptr %a, i64 %index120 %trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16>121 call void @llvm.aarch64.sve.st1.nxv2i16(<vscale x 2 x i16> %trunc,122 <vscale x 2 x i1> %pred,123 ptr %base)124 ret void125}126 127;128; ST1W129;130 131define void @st1w_i32(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pred, ptr %a, i64 %index) {132; CHECK-LABEL: st1w_i32:133; CHECK: // %bb.0:134; CHECK-NEXT: st1w { z0.s }, p0, [x0, x1, lsl #2]135; CHECK-NEXT: ret136 %base = getelementptr i32, ptr %a, i64 %index137 call void @llvm.aarch64.sve.st1.nxv4i32(<vscale x 4 x i32> %data,138 <vscale x 4 x i1> %pred,139 ptr %base)140 ret void141}142 143define void @st1w_f32(<vscale x 4 x float> %data, <vscale x 4 x i1> %pred, ptr %a, i64 %index) {144; CHECK-LABEL: st1w_f32:145; CHECK: // %bb.0:146; CHECK-NEXT: st1w { z0.s }, p0, [x0, x1, lsl #2]147; CHECK-NEXT: ret148 %base = getelementptr float, ptr %a, i64 %index149 call void @llvm.aarch64.sve.st1.nxv4f32(<vscale x 4 x float> %data,150 <vscale x 4 x i1> %pred,151 ptr %base)152 ret void153}154 155define void @st1w_d(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pred, ptr %a, i64 %index) {156; CHECK-LABEL: st1w_d:157; CHECK: // %bb.0:158; CHECK-NEXT: st1w { z0.d }, p0, [x0, x1, lsl #2]159; CHECK-NEXT: ret160 %base = getelementptr i32, ptr %a, i64 %index161 %trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32>162 call void @llvm.aarch64.sve.st1.nxv2i32(<vscale x 2 x i32> %trunc,163 <vscale x 2 x i1> %pred,164 ptr %base)165 ret void166}167 168;169; ST1D170;171 172define void @st1d_i64(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pred, ptr %a, i64 %index) {173; CHECK-LABEL: st1d_i64:174; CHECK: // %bb.0:175; CHECK-NEXT: st1d { z0.d }, p0, [x0, x1, lsl #3]176; CHECK-NEXT: ret177 %base = getelementptr i64, ptr %a, i64 %index178 call void @llvm.aarch64.sve.st1.nxv2i64(<vscale x 2 x i64> %data,179 <vscale x 2 x i1> %pred,180 ptr %base)181 ret void182}183 184define void @st1d_f64(<vscale x 2 x double> %data, <vscale x 2 x i1> %pred, ptr %a, i64 %index) {185; CHECK-LABEL: st1d_f64:186; CHECK: // %bb.0:187; CHECK-NEXT: st1d { z0.d }, p0, [x0, x1, lsl #3]188; CHECK-NEXT: ret189 %base = getelementptr double, ptr %a, i64 %index190 call void @llvm.aarch64.sve.st1.nxv2f64(<vscale x 2 x double> %data,191 <vscale x 2 x i1> %pred,192 ptr %base)193 ret void194}195 196declare void @llvm.aarch64.sve.st1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, ptr)197 198declare void @llvm.aarch64.sve.st1.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i1>, ptr)199declare void @llvm.aarch64.sve.st1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, ptr)200declare void @llvm.aarch64.sve.st1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, ptr)201declare void @llvm.aarch64.sve.st1.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x i1>, ptr)202 203declare void @llvm.aarch64.sve.st1.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i1>, ptr)204declare void @llvm.aarch64.sve.st1.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i1>, ptr)205declare void @llvm.aarch64.sve.st1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, ptr)206declare void @llvm.aarch64.sve.st1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, ptr)207 208declare void @llvm.aarch64.sve.st1.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i1>, ptr)209declare void @llvm.aarch64.sve.st1.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, ptr)210declare void @llvm.aarch64.sve.st1.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, ptr)211declare void @llvm.aarch64.sve.st1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, ptr)212declare void @llvm.aarch64.sve.st1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, ptr)213 214; +bf16 is required for the bfloat version.215attributes #0 = { "target-features"="+bf16" }216