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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4; These tests are here to ensure we don't get a selection error caused5; by performPostLD1Combine, which should bail out if the return6; type is not 128 or 64 bit vector.7 8define <vscale x 4 x i32> @test_post_ld1_insert(ptr %a, ptr %ptr, i64 %inc) {9; CHECK-LABEL: test_post_ld1_insert:10; CHECK: // %bb.0:11; CHECK-NEXT: ldr s0, [x0]12; CHECK-NEXT: add x8, x0, x2, lsl #213; CHECK-NEXT: str x8, [x1]14; CHECK-NEXT: ret15 %load = load i32, ptr %a16 %ins = insertelement <vscale x 4 x i32> undef, i32 %load, i32 017 %gep = getelementptr i32, ptr %a, i64 %inc18 store ptr %gep, ptr %ptr19 ret <vscale x 4 x i32> %ins20}21 22define <vscale x 2 x double> @test_post_ld1_dup(ptr %a, ptr %ptr, i64 %inc) {23; CHECK-LABEL: test_post_ld1_dup:24; CHECK: // %bb.0:25; CHECK-NEXT: ptrue p0.d26; CHECK-NEXT: add x8, x0, x2, lsl #327; CHECK-NEXT: ld1rd { z0.d }, p0/z, [x0]28; CHECK-NEXT: str x8, [x1]29; CHECK-NEXT: ret30 %load = load double, ptr %a31 %dup = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double %load)32 %gep = getelementptr double, ptr %a, i64 %inc33 store ptr %gep, ptr %ptr34 ret <vscale x 2 x double> %dup35}36 37define void @test_post_ld1_int_fixed(ptr %data, i64 %idx, ptr %addr, ptr %res_ptr) #1 {38; CHECK-LABEL: test_post_ld1_int_fixed:39; CHECK: // %bb.0:40; CHECK-NEXT: mov w8, #2 // =0x241; CHECK-NEXT: index z0.d, #0, #142; CHECK-NEXT: ptrue p0.d43; CHECK-NEXT: mov z1.d, x844; CHECK-NEXT: ldr z2, [x2]45; CHECK-NEXT: ldr x8, [x0]46; CHECK-NEXT: ptrue p1.d, vl147; CHECK-NEXT: ldr x9, [x0, x1, lsl #3]48; CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d49; CHECK-NEXT: mov z0.d, z2.d50; CHECK-NEXT: mov z0.d, p1/m, x851; CHECK-NEXT: mov z2.d, p0/m, x952; CHECK-NEXT: add z0.d, z0.d, z2.d53; CHECK-NEXT: str z0, [x3]54; CHECK-NEXT: ret55 %A = load <4 x i64>, ptr %addr56 %ld1 = load i64, ptr %data57 %vec1 = insertelement <4 x i64> %A, i64 %ld1, i32 058 %gep = getelementptr i64, ptr %data, i64 %idx59 %ld2 = load i64, ptr %gep60 %vec2 = insertelement <4 x i64> %A, i64 %ld2, i32 261 %res = add <4 x i64> %vec1, %vec262 store <4 x i64> %res, ptr %res_ptr63 ret void64}65 66define void @test_post_ld1_double_fixed(ptr %data, i64 %idx, ptr %addr, ptr %res_ptr) #1 {67; CHECK-LABEL: test_post_ld1_double_fixed:68; CHECK: // %bb.0:69; CHECK-NEXT: mov w8, #2 // =0x270; CHECK-NEXT: index z0.d, #0, #171; CHECK-NEXT: ptrue p0.d72; CHECK-NEXT: mov z1.d, x873; CHECK-NEXT: ptrue p1.d, vl174; CHECK-NEXT: ldr d2, [x0, x1, lsl #3]75; CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d76; CHECK-NEXT: ldr z0, [x2]77; CHECK-NEXT: ldr d1, [x0]78; CHECK-NEXT: sel z1.d, p1, z1.d, z0.d79; CHECK-NEXT: mov z0.d, p0/m, d280; CHECK-NEXT: fadd z0.d, z1.d, z0.d81; CHECK-NEXT: str z0, [x3]82; CHECK-NEXT: ret83 %A = load <4 x double>, ptr %addr84 %ld1 = load double, ptr %data85 %vec1 = insertelement <4 x double> %A, double %ld1, i32 086 %gep = getelementptr double, ptr %data, i64 %idx87 %ld2 = load double, ptr %gep88 %vec2 = insertelement <4 x double> %A, double %ld2, i32 289 %res = fadd <4 x double> %vec1, %vec290 store <4 x double> %res, ptr %res_ptr91 ret void92}93attributes #1 = { vscale_range(2,2) "target-features"="+neon,+sve" }94 95declare <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double)96