149 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: opt -S -loop-reduce < %s | FileCheck %s --check-prefix=IR3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s --check-prefix=ASM4; Note: To update this test, please run utils/update_test_checks.py and utils/update_llc_test_checks.py separately on opt/llc run line.5 6target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"7target triple = "aarch64-linux-gnu"8 9; These tests check that the IR coming out of LSR does not cast input/output pointer from ptr to ptr type.10; And scaled-index addressing mode is leveraged in the generated assembly, i.e. ld1h { z1.h }, p0/z, [x0, x8, lsl #1].11 12define void @ld_st_nxv8i16(ptr %in, ptr %out) {13; IR-LABEL: @ld_st_nxv8i16(14; IR-NEXT: entry:15; IR-NEXT: br label [[LOOP_PH:%.*]]16; IR: loop.ph:17; IR-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()18; IR-NEXT: [[SCALED_VF:%.*]] = shl i64 [[VSCALE]], 319; IR-NEXT: br label [[LOOP:%.*]]20; IR: loop:21; IR-NEXT: [[INDVAR:%.*]] = phi i64 [ 0, [[LOOP_PH]] ], [ [[INDVAR_NEXT:%.*]], [[LOOP]] ]22; IR-NEXT: [[TMP0:%.*]] = shl i64 [[INDVAR]], 123; IR-NEXT: [[UGLYGEP1:%.*]] = getelementptr i8, ptr [[IN:%.*]], i64 [[TMP0]]24; IR-NEXT: [[TMP1:%.*]] = shl i64 [[INDVAR]], 125; IR-NEXT: [[UGLYGEP:%.*]] = getelementptr i8, ptr [[OUT:%.*]], i64 [[TMP1]]26; IR-NEXT: [[VAL:%.*]] = load <vscale x 8 x i16>, ptr [[UGLYGEP1]], align 1627; IR-NEXT: [[ADDP_VEC:%.*]] = add <vscale x 8 x i16> [[VAL]], splat (i16 3)28; IR-NEXT: store <vscale x 8 x i16> [[ADDP_VEC]], ptr [[UGLYGEP]], align 1629; IR-NEXT: [[INDVAR_NEXT]] = add nsw i64 [[INDVAR]], [[SCALED_VF]]30; IR-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[INDVAR_NEXT]], 102431; IR-NEXT: br i1 [[EXIT_COND]], label [[LOOP_EXIT:%.*]], label [[LOOP]]32; IR: loop.exit:33; IR-NEXT: br label [[EXIT:%.*]]34; IR: exit:35; IR-NEXT: ret void36;37; ASM-LABEL: ld_st_nxv8i16:38; ASM: // %bb.0: // %entry39; ASM-NEXT: ptrue p0.h40; ASM-NEXT: mov x8, xzr41; ASM-NEXT: cnth x942; ASM-NEXT: .LBB0_1: // %loop43; ASM-NEXT: // =>This Inner Loop Header: Depth=144; ASM-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]45; ASM-NEXT: add z0.h, z0.h, #346; ASM-NEXT: st1h { z0.h }, p0, [x1, x8, lsl #1]47; ASM-NEXT: add x8, x8, x948; ASM-NEXT: cmp x8, #102449; ASM-NEXT: b.ne .LBB0_150; ASM-NEXT: // %bb.2: // %exit51; ASM-NEXT: ret52entry:53 br label %loop.ph54 55loop.ph:56 %vscale = call i64 @llvm.vscale.i64()57 %scaled_vf = shl i64 %vscale, 358 br label %loop59 60loop: ; preds = %loop, %loop.ph61 %indvar = phi i64 [ 0, %loop.ph ], [ %indvar.next, %loop ]62 %ptr.in = getelementptr inbounds i16, ptr %in, i64 %indvar63 %ptr.out = getelementptr inbounds i16, ptr %out, i64 %indvar64 %val = load <vscale x 8 x i16>, ptr %ptr.in, align 1665 %addp_vec = add <vscale x 8 x i16> %val, splat (i16 3)66 store <vscale x 8 x i16> %addp_vec, ptr %ptr.out, align 1667 %indvar.next = add nsw i64 %indvar, %scaled_vf68 %exit.cond = icmp eq i64 %indvar.next, 102469 br i1 %exit.cond, label %loop.exit, label %loop70 71loop.exit: ; preds = %loop72 br label %exit73 74exit:75 ret void76}77 78define void @masked_ld_st_nxv8i16(ptr %in, ptr %out, i64 %n) {79; IR-LABEL: @masked_ld_st_nxv8i16(80; IR-NEXT: entry:81; IR-NEXT: br label [[LOOP_PH:%.*]]82; IR: loop.ph:83; IR-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()84; IR-NEXT: [[SCALED_VF:%.*]] = shl i64 [[VSCALE]], 385; IR-NEXT: br label [[LOOP:%.*]]86; IR: loop:87; IR-NEXT: [[INDVAR:%.*]] = phi i64 [ 0, [[LOOP_PH]] ], [ [[INDVAR_NEXT:%.*]], [[LOOP]] ]88; IR-NEXT: [[TMP0:%.*]] = shl i64 [[INDVAR]], 189; IR-NEXT: [[UGLYGEP1:%.*]] = getelementptr i8, ptr [[IN:%.*]], i64 [[TMP0]]90; IR-NEXT: [[TMP1:%.*]] = shl i64 [[INDVAR]], 191; IR-NEXT: [[UGLYGEP:%.*]] = getelementptr i8, ptr [[OUT:%.*]], i64 [[TMP1]]92; IR-NEXT: [[VAL:%.*]] = call <vscale x 8 x i16> @llvm.masked.load.nxv8i16.p0(ptr align 4 [[UGLYGEP1]], <vscale x 8 x i1> splat (i1 true), <vscale x 8 x i16> poison)93; IR-NEXT: [[ADDP_VEC:%.*]] = add <vscale x 8 x i16> [[VAL]], splat (i16 3)94; IR-NEXT: call void @llvm.masked.store.nxv8i16.p0(<vscale x 8 x i16> [[ADDP_VEC]], ptr align 4 [[UGLYGEP]], <vscale x 8 x i1> splat (i1 true))95; IR-NEXT: [[INDVAR_NEXT]] = add nsw i64 [[INDVAR]], [[SCALED_VF]]96; IR-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[N:%.*]], [[INDVAR_NEXT]]97; IR-NEXT: br i1 [[EXIT_COND]], label [[LOOP_EXIT:%.*]], label [[LOOP]]98; IR: loop.exit:99; IR-NEXT: br label [[EXIT:%.*]]100; IR: exit:101; IR-NEXT: ret void102;103; ASM-LABEL: masked_ld_st_nxv8i16:104; ASM: // %bb.0: // %entry105; ASM-NEXT: ptrue p0.h106; ASM-NEXT: mov x8, xzr107; ASM-NEXT: cnth x9108; ASM-NEXT: .LBB1_1: // %loop109; ASM-NEXT: // =>This Inner Loop Header: Depth=1110; ASM-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]111; ASM-NEXT: add z0.h, z0.h, #3112; ASM-NEXT: st1h { z0.h }, p0, [x1, x8, lsl #1]113; ASM-NEXT: add x8, x8, x9114; ASM-NEXT: cmp x2, x8115; ASM-NEXT: b.ne .LBB1_1116; ASM-NEXT: // %bb.2: // %exit117; ASM-NEXT: ret118entry:119 br label %loop.ph120 121loop.ph:122 %vscale = call i64 @llvm.vscale.i64()123 %scaled_vf = shl i64 %vscale, 3124 br label %loop125 126loop: ; preds = %loop, %loop.ph127 %indvar = phi i64 [ 0, %loop.ph ], [ %indvar.next, %loop ]128 %ptr.in = getelementptr inbounds i16, ptr %in, i64 %indvar129 %ptr.out = getelementptr inbounds i16, ptr %out, i64 %indvar130 %val = call <vscale x 8 x i16> @llvm.masked.load.nxv8i16.p0(ptr %ptr.in, i32 4, <vscale x 8 x i1> splat (i1 true), <vscale x 8 x i16> poison)131 %addp_vec = add <vscale x 8 x i16> %val, splat (i16 3)132 call void @llvm.masked.store.nxv8i16.p0(<vscale x 8 x i16> %addp_vec, ptr %ptr.out, i32 4, <vscale x 8 x i1> splat (i1 true))133 %indvar.next = add nsw i64 %indvar, %scaled_vf134 %exit.cond = icmp eq i64 %indvar.next, %n135 br i1 %exit.cond, label %loop.exit, label %loop136 137loop.exit: ; preds = %loop138 br label %exit139 140exit:141 ret void142}143 144declare i64 @llvm.vscale.i64()145 146declare <vscale x 8 x i16> @llvm.masked.load.nxv8i16.p0(ptr, i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i16>)147 148declare void @llvm.masked.store.nxv8i16.p0(<vscale x 8 x i16>, ptr, i32 immarg, <vscale x 8 x i1>)149