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1; RUN: llc -mtriple=aarch64 -mattr=+sve2p2 < %s2 3;; These masked.compressstore operations could be natively supported with +sve2p24;; (or by promoting to 32/64 bit elements + a truncstore), but currently are not5;; supported.6 7; XFAIL: *8 9define void @test_compressstore_nxv8i16(ptr %p, <vscale x 8 x i16> %vec, <vscale x 8 x i1> %mask) {10 tail call void @llvm.masked.compressstore.nxv8i16(<vscale x 8 x i16> %vec, ptr align 2 %p, <vscale x 8 x i1> %mask)11 ret void12}13 14define void @test_compressstore_nxv16i8(ptr %p, <vscale x 16 x i8> %vec, <vscale x 16 x i1> %mask) {15 tail call void @llvm.masked.compressstore.nxv16i8(<vscale x 16 x i8> %vec, ptr align 1 %p, <vscale x 16 x i1> %mask)16 ret void17}18