187 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s3 4;5; Masked Additions6;7 8define <vscale x 16 x i8> @masked_add_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i1> %mask) {9; CHECK-LABEL: masked_add_nxv16i8:10; CHECK: // %bb.0:11; CHECK-NEXT: add z0.b, p0/m, z0.b, z1.b12; CHECK-NEXT: ret13 %select = select <vscale x 16 x i1> %mask, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer14 %ret = add <vscale x 16 x i8> %a, %select15 ret <vscale x 16 x i8> %ret16}17 18define <vscale x 8 x i16> @masked_add_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i1> %mask) {19; CHECK-LABEL: masked_add_nxv8i16:20; CHECK: // %bb.0:21; CHECK-NEXT: add z0.h, p0/m, z0.h, z1.h22; CHECK-NEXT: ret23 %select = select <vscale x 8 x i1> %mask, <vscale x 8 x i16> %b, <vscale x 8 x i16> zeroinitializer24 %ret = add <vscale x 8 x i16> %a, %select25 ret <vscale x 8 x i16> %ret26}27 28define <vscale x 4 x i32> @masked_add_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i1> %mask) {29; CHECK-LABEL: masked_add_nxv4i32:30; CHECK: // %bb.0:31; CHECK-NEXT: add z0.s, p0/m, z0.s, z1.s32; CHECK-NEXT: ret33 %select = select <vscale x 4 x i1> %mask, <vscale x 4 x i32> %b, <vscale x 4 x i32> zeroinitializer34 %ret = add <vscale x 4 x i32> %a, %select35 ret <vscale x 4 x i32> %ret36}37 38define <vscale x 2 x i64> @masked_add_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i1> %mask) {39; CHECK-LABEL: masked_add_nxv2i64:40; CHECK: // %bb.0:41; CHECK-NEXT: add z0.d, p0/m, z0.d, z1.d42; CHECK-NEXT: ret43 %select = select <vscale x 2 x i1> %mask, <vscale x 2 x i64> %b, <vscale x 2 x i64> zeroinitializer44 %ret = add <vscale x 2 x i64> %a, %select45 ret <vscale x 2 x i64> %ret46}47 48;49; Masked Subtractions50;51 52define <vscale x 16 x i8> @masked_sub_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i1> %mask) {53; CHECK-LABEL: masked_sub_nxv16i8:54; CHECK: // %bb.0:55; CHECK-NEXT: sub z0.b, p0/m, z0.b, z1.b56; CHECK-NEXT: ret57 %select = select <vscale x 16 x i1> %mask, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer58 %ret = sub <vscale x 16 x i8> %a, %select59 ret <vscale x 16 x i8> %ret60}61 62define <vscale x 8 x i16> @masked_sub_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i1> %mask) {63; CHECK-LABEL: masked_sub_nxv8i16:64; CHECK: // %bb.0:65; CHECK-NEXT: sub z0.h, p0/m, z0.h, z1.h66; CHECK-NEXT: ret67 %select = select <vscale x 8 x i1> %mask, <vscale x 8 x i16> %b, <vscale x 8 x i16> zeroinitializer68 %ret = sub <vscale x 8 x i16> %a, %select69 ret <vscale x 8 x i16> %ret70}71 72define <vscale x 4 x i32> @masked_sub_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i1> %mask) {73; CHECK-LABEL: masked_sub_nxv4i32:74; CHECK: // %bb.0:75; CHECK-NEXT: sub z0.s, p0/m, z0.s, z1.s76; CHECK-NEXT: ret77 %select = select <vscale x 4 x i1> %mask, <vscale x 4 x i32> %b, <vscale x 4 x i32> zeroinitializer78 %ret = sub <vscale x 4 x i32> %a, %select79 ret <vscale x 4 x i32> %ret80}81 82define <vscale x 2 x i64> @masked_sub_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i1> %mask) {83; CHECK-LABEL: masked_sub_nxv2i64:84; CHECK: // %bb.0:85; CHECK-NEXT: sub z0.d, p0/m, z0.d, z1.d86; CHECK-NEXT: ret87 %select = select <vscale x 2 x i1> %mask, <vscale x 2 x i64> %b, <vscale x 2 x i64> zeroinitializer88 %ret = sub <vscale x 2 x i64> %a, %select89 ret <vscale x 2 x i64> %ret90}91 92;93; Masked multiply-add94;95 96define <vscale x 16 x i8> @masked_mla_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i1> %mask) {97; CHECK-LABEL: masked_mla_nxv16i8:98; CHECK: // %bb.0:99; CHECK-NEXT: mla z0.b, p0/m, z1.b, z2.b100; CHECK-NEXT: ret101 %mul = mul nsw <vscale x 16 x i8> %b, %c102 %sel = select <vscale x 16 x i1> %mask, <vscale x 16 x i8> %mul, <vscale x 16 x i8> zeroinitializer103 %add = add <vscale x 16 x i8> %a, %sel104 ret <vscale x 16 x i8> %add105}106 107define <vscale x 8 x i16> @masked_mla_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i1> %mask) {108; CHECK-LABEL: masked_mla_nxv8i16:109; CHECK: // %bb.0:110; CHECK-NEXT: mla z0.h, p0/m, z1.h, z2.h111; CHECK-NEXT: ret112 %mul = mul nsw <vscale x 8 x i16> %b, %c113 %sel = select <vscale x 8 x i1> %mask, <vscale x 8 x i16> %mul, <vscale x 8 x i16> zeroinitializer114 %add = add <vscale x 8 x i16> %a, %sel115 ret <vscale x 8 x i16> %add116}117 118define <vscale x 4 x i32> @masked_mla_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i1> %mask) {119; CHECK-LABEL: masked_mla_nxv4i32:120; CHECK: // %bb.0:121; CHECK-NEXT: mla z0.s, p0/m, z1.s, z2.s122; CHECK-NEXT: ret123 %mul = mul nsw <vscale x 4 x i32> %b, %c124 %sel = select <vscale x 4 x i1> %mask, <vscale x 4 x i32> %mul, <vscale x 4 x i32> zeroinitializer125 %add = add <vscale x 4 x i32> %a, %sel126 ret <vscale x 4 x i32> %add127}128 129define <vscale x 2 x i64> @masked_mla_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i1> %mask) {130; CHECK-LABEL: masked_mla_nxv2i64:131; CHECK: // %bb.0:132; CHECK-NEXT: mla z0.d, p0/m, z1.d, z2.d133; CHECK-NEXT: ret134 %mul = mul nsw <vscale x 2 x i64> %b, %c135 %sel = select <vscale x 2 x i1> %mask, <vscale x 2 x i64> %mul, <vscale x 2 x i64> zeroinitializer136 %add = add <vscale x 2 x i64> %a, %sel137 ret <vscale x 2 x i64> %add138}139 140;141; Masked multiply-subtract142;143 144define <vscale x 16 x i8> @masked_mls_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i1> %mask) {145; CHECK-LABEL: masked_mls_nxv16i8:146; CHECK: // %bb.0:147; CHECK-NEXT: mls z0.b, p0/m, z1.b, z2.b148; CHECK-NEXT: ret149 %mul = mul nsw <vscale x 16 x i8> %b, %c150 %sel = select <vscale x 16 x i1> %mask, <vscale x 16 x i8> %mul, <vscale x 16 x i8> zeroinitializer151 %sub = sub <vscale x 16 x i8> %a, %sel152 ret <vscale x 16 x i8> %sub153}154 155define <vscale x 8 x i16> @masked_mls_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i1> %mask) {156; CHECK-LABEL: masked_mls_nxv8i16:157; CHECK: // %bb.0:158; CHECK-NEXT: mls z0.h, p0/m, z1.h, z2.h159; CHECK-NEXT: ret160 %mul = mul nsw <vscale x 8 x i16> %b, %c161 %sel = select <vscale x 8 x i1> %mask, <vscale x 8 x i16> %mul, <vscale x 8 x i16> zeroinitializer162 %sub = sub <vscale x 8 x i16> %a, %sel163 ret <vscale x 8 x i16> %sub164}165 166define <vscale x 4 x i32> @masked_mls_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i1> %mask) {167; CHECK-LABEL: masked_mls_nxv4i32:168; CHECK: // %bb.0:169; CHECK-NEXT: mls z0.s, p0/m, z1.s, z2.s170; CHECK-NEXT: ret171 %mul = mul nsw <vscale x 4 x i32> %b, %c172 %sel = select <vscale x 4 x i1> %mask, <vscale x 4 x i32> %mul, <vscale x 4 x i32> zeroinitializer173 %sub = sub <vscale x 4 x i32> %a, %sel174 ret <vscale x 4 x i32> %sub175}176 177define <vscale x 2 x i64> @masked_mls_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i1> %mask) {178; CHECK-LABEL: masked_mls_nxv2i64:179; CHECK: // %bb.0:180; CHECK-NEXT: mls z0.d, p0/m, z1.d, z2.d181; CHECK-NEXT: ret182 %mul = mul nsw <vscale x 2 x i64> %b, %c183 %sel = select <vscale x 2 x i1> %mask, <vscale x 2 x i64> %mul, <vscale x 2 x i64> zeroinitializer184 %sub = sub <vscale x 2 x i64> %a, %sel185 ret <vscale x 2 x i64> %sub186}187