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1; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve -asm-verbose=0 < %s | FileCheck %s2 3;4; Masked Loads5;6 7define <vscale x 2 x i64> @masked_load_nxv2i64(ptr %a, <vscale x 2 x i1> %mask) nounwind {8; CHECK-LABEL: masked_load_nxv2i64:9; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]10; CHECK-NEXT: ret11 %load = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64(ptr %a, i32 8, <vscale x 2 x i1> %mask, <vscale x 2 x i64> poison)12 ret <vscale x 2 x i64> %load13}14 15define <vscale x 4 x i32> @masked_load_nxv4i32(ptr %a, <vscale x 4 x i1> %mask) nounwind {16; CHECK-LABEL: masked_load_nxv4i32:17; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]18; CHECK-NEXT: ret19 %load = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32(ptr %a, i32 4, <vscale x 4 x i1> %mask, <vscale x 4 x i32> poison)20 ret <vscale x 4 x i32> %load21}22 23define <vscale x 8 x i16> @masked_load_nxv8i16(ptr %a, <vscale x 8 x i1> %mask) nounwind {24; CHECK-LABEL: masked_load_nxv8i16:25; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]26; CHECK-NEXT: ret27 %load = call <vscale x 8 x i16> @llvm.masked.load.nxv8i16(ptr %a, i32 2, <vscale x 8 x i1> %mask, <vscale x 8 x i16> poison)28 ret <vscale x 8 x i16> %load29}30 31define <vscale x 16 x i8> @masked_load_nxv16i8(ptr %a, <vscale x 16 x i1> %mask) nounwind {32; CHECK-LABEL: masked_load_nxv16i8:33; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]34; CHECK-NEXT: ret35 %load = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8(ptr %a, i32 1, <vscale x 16 x i1> %mask, <vscale x 16 x i8> poison)36 ret <vscale x 16 x i8> %load37}38 39define <vscale x 2 x double> @masked_load_nxv2f64(ptr %a, <vscale x 2 x i1> %mask) nounwind {40; CHECK-LABEL: masked_load_nxv2f64:41; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]42; CHECK-NEXT: ret43 %load = call <vscale x 2 x double> @llvm.masked.load.nxv2f64(ptr %a, i32 8, <vscale x 2 x i1> %mask, <vscale x 2 x double> poison)44 ret <vscale x 2 x double> %load45}46 47define <vscale x 2 x float> @masked_load_nxv2f32(ptr %a, <vscale x 2 x i1> %mask) nounwind {48; CHECK-LABEL: masked_load_nxv2f32:49; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]50; CHECK-NEXT: ret51 %load = call <vscale x 2 x float> @llvm.masked.load.nxv2f32(ptr %a, i32 4, <vscale x 2 x i1> %mask, <vscale x 2 x float> poison)52 ret <vscale x 2 x float> %load53}54 55define <vscale x 2 x half> @masked_load_nxv2f16(ptr %a, <vscale x 2 x i1> %mask) nounwind {56; CHECK-LABEL: masked_load_nxv2f16:57; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0]58; CHECK-NEXT: ret59 %load = call <vscale x 2 x half> @llvm.masked.load.nxv2f16(ptr %a, i32 2, <vscale x 2 x i1> %mask, <vscale x 2 x half> poison)60 ret <vscale x 2 x half> %load61}62 63define <vscale x 2 x bfloat> @masked_load_nxv2bf16(ptr %a, <vscale x 2 x i1> %mask) nounwind #0 {64; CHECK-LABEL: masked_load_nxv2bf16:65; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0]66; CHECK-NEXT: ret67 %load = call <vscale x 2 x bfloat> @llvm.masked.load.nxv2bf16(ptr %a, i32 2, <vscale x 2 x i1> %mask, <vscale x 2 x bfloat> poison)68 ret <vscale x 2 x bfloat> %load69}70 71define <vscale x 4 x float> @masked_load_nxv4f32(ptr %a, <vscale x 4 x i1> %mask) nounwind {72; CHECK-LABEL: masked_load_nxv4f32:73; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]74; CHECK-NEXT: ret75 %load = call <vscale x 4 x float> @llvm.masked.load.nxv4f32(ptr %a, i32 4, <vscale x 4 x i1> %mask, <vscale x 4 x float> poison)76 ret <vscale x 4 x float> %load77}78 79define <vscale x 4 x half> @masked_load_nxv4f16(ptr %a, <vscale x 4 x i1> %mask) nounwind {80; CHECK-LABEL: masked_load_nxv4f16:81; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]82; CHECK-NEXT: ret83 %load = call <vscale x 4 x half> @llvm.masked.load.nxv4f16(ptr %a, i32 2, <vscale x 4 x i1> %mask, <vscale x 4 x half> poison)84 ret <vscale x 4 x half> %load85}86 87define <vscale x 4 x bfloat> @masked_load_nxv4bf16(ptr %a, <vscale x 4 x i1> %mask) nounwind #0 {88; CHECK-LABEL: masked_load_nxv4bf16:89; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]90; CHECK-NEXT: ret91 %load = call <vscale x 4 x bfloat> @llvm.masked.load.nxv4bf16(ptr %a, i32 2, <vscale x 4 x i1> %mask, <vscale x 4 x bfloat> poison)92 ret <vscale x 4 x bfloat> %load93}94 95define <vscale x 8 x half> @masked_load_nxv8f16(ptr %a, <vscale x 8 x i1> %mask) nounwind {96; CHECK-LABEL: masked_load_nxv8f16:97; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]98; CHECK-NEXT: ret99 %load = call <vscale x 8 x half> @llvm.masked.load.nxv8f16(ptr %a, i32 2, <vscale x 8 x i1> %mask, <vscale x 8 x half> poison)100 ret <vscale x 8 x half> %load101}102 103define <vscale x 8 x bfloat> @masked_load_nxv8bf16(ptr %a, <vscale x 8 x i1> %mask) nounwind #0 {104; CHECK-LABEL: masked_load_nxv8bf16:105; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]106; CHECK-NEXT: ret107 %load = call <vscale x 8 x bfloat> @llvm.masked.load.nxv8bf16(ptr %a, i32 2, <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> poison)108 ret <vscale x 8 x bfloat> %load109}110 111define <vscale x 4 x i32> @masked_load_passthru(ptr %a, <vscale x 4 x i1> %mask, <vscale x 4 x i32> %passthru) nounwind {112; CHECK-LABEL: masked_load_passthru:113; CHECK-NEXT: ld1w { z1.s }, p0/z, [x0]114; CHECK-NEXT: mov z0.s, p0/m, z1.s115; CHECK-NEXT: ret116 %load = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32(ptr %a, i32 4, <vscale x 4 x i1> %mask, <vscale x 4 x i32> %passthru)117 ret <vscale x 4 x i32> %load118}119 120; Masked load requires promotion121define <vscale x 2 x i16> @masked_load_nxv2i16(ptr noalias %in, <vscale x 2 x i1> %mask) {122; CHECK-LABEL: masked_load_nxv2i16123; CHECK: ld1h { z0.d }, p0/z, [x0]124; CHECK-NEXT: ret125 %wide.load = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16(ptr %in, i32 2, <vscale x 2 x i1> %mask, <vscale x 2 x i16> poison)126 ret <vscale x 2 x i16> %wide.load127}128 129;130; Masked Stores131;132 133define void @masked_store_nxv2i64(ptr %a, <vscale x 2 x i64> %val, <vscale x 2 x i1> %mask) nounwind {134; CHECK-LABEL: masked_store_nxv2i64:135; CHECK-NEXT: st1d { z0.d }, p0, [x0]136; CHECK-NEXT: ret137 call void @llvm.masked.store.nxv2i64(<vscale x 2 x i64> %val, ptr %a, i32 8, <vscale x 2 x i1> %mask)138 ret void139}140 141define void @masked_store_nxv4i32(ptr %a, <vscale x 4 x i32> %val, <vscale x 4 x i1> %mask) nounwind {142; CHECK-LABEL: masked_store_nxv4i32:143; CHECK-NEXT: st1w { z0.s }, p0, [x0]144; CHECK-NEXT: ret145 call void @llvm.masked.store.nxv4i32(<vscale x 4 x i32> %val, ptr %a, i32 4, <vscale x 4 x i1> %mask)146 ret void147}148 149define void @masked_store_nxv8i16(ptr %a, <vscale x 8 x i16> %val, <vscale x 8 x i1> %mask) nounwind {150; CHECK-LABEL: masked_store_nxv8i16:151; CHECK-NEXT: st1h { z0.h }, p0, [x0]152; CHECK-NEXT: ret153 call void @llvm.masked.store.nxv8i16(<vscale x 8 x i16> %val, ptr %a, i32 2, <vscale x 8 x i1> %mask)154 ret void155}156 157define void @masked_store_nxv16i8(ptr %a, <vscale x 16 x i8> %val, <vscale x 16 x i1> %mask) nounwind {158; CHECK-LABEL: masked_store_nxv16i8:159; CHECK-NEXT: st1b { z0.b }, p0, [x0]160; CHECK-NEXT: ret161 call void @llvm.masked.store.nxv16i8(<vscale x 16 x i8> %val, ptr %a, i32 1, <vscale x 16 x i1> %mask)162 ret void163}164 165define void @masked_store_nxv2f64(ptr %a, <vscale x 2 x double> %val, <vscale x 2 x i1> %mask) nounwind {166; CHECK-LABEL: masked_store_nxv2f64:167; CHECK-NEXT: st1d { z0.d }, p0, [x0]168; CHECK-NEXT: ret169 call void @llvm.masked.store.nxv2f64(<vscale x 2 x double> %val, ptr %a, i32 8, <vscale x 2 x i1> %mask)170 ret void171}172 173define void @masked_store_nxv2f32(ptr %a, <vscale x 2 x float> %val, <vscale x 2 x i1> %mask) nounwind {174; CHECK-LABEL: masked_store_nxv2f32:175; CHECK-NEXT: st1w { z0.d }, p0, [x0]176; CHECK-NEXT: ret177 call void @llvm.masked.store.nxv2f32(<vscale x 2 x float> %val, ptr %a, i32 4, <vscale x 2 x i1> %mask)178 ret void179}180 181define void @masked_store_nxv2f16(ptr %a, <vscale x 2 x half> %val, <vscale x 2 x i1> %mask) nounwind {182; CHECK-LABEL: masked_store_nxv2f16:183; CHECK-NEXT: st1h { z0.d }, p0, [x0]184; CHECK-NEXT: ret185 call void @llvm.masked.store.nxv2f16(<vscale x 2 x half> %val, ptr %a, i32 4, <vscale x 2 x i1> %mask)186 ret void187}188 189define void @masked_store_nxv4f32(ptr %a, <vscale x 4 x float> %val, <vscale x 4 x i1> %mask) nounwind {190; CHECK-LABEL: masked_store_nxv4f32:191; CHECK-NEXT: st1w { z0.s }, p0, [x0]192; CHECK-NEXT: ret193 call void @llvm.masked.store.nxv4f32(<vscale x 4 x float> %val, ptr %a, i32 4, <vscale x 4 x i1> %mask)194 ret void195}196 197define void @masked_store_nxv4f16(ptr %a, <vscale x 4 x half> %val, <vscale x 4 x i1> %mask) nounwind {198; CHECK-LABEL: masked_store_nxv4f16:199; CHECK-NEXT: st1h { z0.s }, p0, [x0]200; CHECK-NEXT: ret201 call void @llvm.masked.store.nxv4f16(<vscale x 4 x half> %val, ptr %a, i32 2, <vscale x 4 x i1> %mask)202 ret void203}204 205define void @masked_store_nxv8f16(ptr %a, <vscale x 8 x half> %val, <vscale x 8 x i1> %mask) nounwind {206; CHECK-LABEL: masked_store_nxv8f16:207; CHECK-NEXT: st1h { z0.h }, p0, [x0]208; CHECK-NEXT: ret209 call void @llvm.masked.store.nxv8f16(<vscale x 8 x half> %val, ptr %a, i32 2, <vscale x 8 x i1> %mask)210 ret void211}212 213define void @masked_store_nxv2bf16(ptr %a, <vscale x 2 x bfloat> %val, <vscale x 2 x i1> %mask) nounwind #0 {214; CHECK-LABEL: masked_store_nxv2bf16:215; CHECK-NEXT: st1h { z0.d }, p0, [x0]216; CHECK-NEXT: ret217 call void @llvm.masked.store.nxv2bf16(<vscale x 2 x bfloat> %val, ptr %a, i32 2, <vscale x 2 x i1> %mask)218 ret void219}220 221define void @masked_store_nxv4bf16(ptr %a, <vscale x 4 x bfloat> %val, <vscale x 4 x i1> %mask) nounwind #0 {222; CHECK-LABEL: masked_store_nxv4bf16:223; CHECK-NEXT: st1h { z0.s }, p0, [x0]224; CHECK-NEXT: ret225 call void @llvm.masked.store.nxv4bf16(<vscale x 4 x bfloat> %val, ptr %a, i32 2, <vscale x 4 x i1> %mask)226 ret void227}228 229define void @masked_store_nxv8bf16(ptr %a, <vscale x 8 x bfloat> %val, <vscale x 8 x i1> %mask) nounwind #0 {230; CHECK-LABEL: masked_store_nxv8bf16:231; CHECK-NEXT: st1h { z0.h }, p0, [x0]232; CHECK-NEXT: ret233 call void @llvm.masked.store.nxv8bf16(<vscale x 8 x bfloat> %val, ptr %a, i32 2, <vscale x 8 x i1> %mask)234 ret void235}236 237;238; Masked load store of pointer data type239;240 241; Pointer of integer type242 243define <vscale x 2 x ptr> @masked.load.nxv2p0i8(ptr %vector_ptr, <vscale x 2 x i1> %mask) nounwind {244; CHECK-LABEL: masked.load.nxv2p0i8:245; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]246; CHECK-NEXT: ret247 %v = call <vscale x 2 x ptr> @llvm.masked.load.nxv2p0.p0(ptr %vector_ptr, i32 8, <vscale x 2 x i1> %mask, <vscale x 2 x ptr> poison)248 ret <vscale x 2 x ptr> %v249}250define <vscale x 2 x ptr> @masked.load.nxv2p0i16(ptr %vector_ptr, <vscale x 2 x i1> %mask) nounwind {251; CHECK-LABEL: masked.load.nxv2p0i16:252; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]253; CHECK-NEXT: ret254 %v = call <vscale x 2 x ptr> @llvm.masked.load.nxv2p0.p0(ptr %vector_ptr, i32 8, <vscale x 2 x i1> %mask, <vscale x 2 x ptr> poison)255 ret <vscale x 2 x ptr> %v256}257define <vscale x 2 x ptr> @masked.load.nxv2p0i32(ptr %vector_ptr, <vscale x 2 x i1> %mask) nounwind {258; CHECK-LABEL: masked.load.nxv2p0i32:259; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]260; CHECK-NEXT: ret261 %v = call <vscale x 2 x ptr> @llvm.masked.load.nxv2p0.p0(ptr %vector_ptr, i32 8, <vscale x 2 x i1> %mask, <vscale x 2 x ptr> poison)262 ret <vscale x 2 x ptr> %v263}264define <vscale x 2 x ptr> @masked.load.nxv2p0i64(ptr %vector_ptr, <vscale x 2 x i1> %mask) nounwind {265; CHECK-LABEL: masked.load.nxv2p0i64:266; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]267; CHECK-NEXT: ret268 %v = call <vscale x 2 x ptr> @llvm.masked.load.nxv2p0.p0(ptr %vector_ptr, i32 8, <vscale x 2 x i1> %mask, <vscale x 2 x ptr> poison)269 ret <vscale x 2 x ptr> %v270}271 272; Pointer of floating-point type273 274define <vscale x 2 x ptr> @masked.load.nxv2p0bf16(ptr %vector_ptr, <vscale x 2 x i1> %mask) nounwind #0 {275; CHECK-LABEL: masked.load.nxv2p0bf16:276; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]277; CHECK-NEXT: ret278 %v = call <vscale x 2 x ptr> @llvm.masked.load.nxv2p0.p0(ptr %vector_ptr, i32 8, <vscale x 2 x i1> %mask, <vscale x 2 x ptr> poison)279 ret <vscale x 2 x ptr> %v280}281define <vscale x 2 x ptr> @masked.load.nxv2p0f16(ptr %vector_ptr, <vscale x 2 x i1> %mask) nounwind {282; CHECK-LABEL: masked.load.nxv2p0f16:283; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]284; CHECK-NEXT: ret285 %v = call <vscale x 2 x ptr> @llvm.masked.load.nxv2p0.p0(ptr %vector_ptr, i32 8, <vscale x 2 x i1> %mask, <vscale x 2 x ptr> poison)286 ret <vscale x 2 x ptr> %v287}288define <vscale x 2 x ptr> @masked.load.nxv2p0f32(ptr %vector_ptr, <vscale x 2 x i1> %mask) nounwind {289; CHECK-LABEL: masked.load.nxv2p0f32:290; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]291; CHECK-NEXT: ret292 %v = call <vscale x 2 x ptr> @llvm.masked.load.nxv2p0.p0(ptr %vector_ptr, i32 8, <vscale x 2 x i1> %mask, <vscale x 2 x ptr> poison)293 ret <vscale x 2 x ptr> %v294}295define <vscale x 2 x ptr> @masked.load.nxv2p0f64(ptr %vector_ptr, <vscale x 2 x i1> %mask) nounwind {296; CHECK-LABEL: masked.load.nxv2p0f64:297; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]298; CHECK-NEXT: ret299 %v = call <vscale x 2 x ptr> @llvm.masked.load.nxv2p0.p0(ptr %vector_ptr, i32 8, <vscale x 2 x i1> %mask, <vscale x 2 x ptr> poison)300 ret <vscale x 2 x ptr> %v301}302 303; Pointer of array type304 305define void @masked.store.nxv2p0a64i16(<vscale x 2 x ptr> %data, ptr %vector_ptr, <vscale x 2 x i1> %mask) nounwind {306; CHECK-LABEL: masked.store.nxv2p0a64i16:307; CHECK-NEXT: st1d { z0.d }, p0, [x0]308; CHECK-NEXT: ret309 call void @llvm.masked.store.nxv2p0.p0(<vscale x 2 x ptr> %data, ptr %vector_ptr, i32 8, <vscale x 2 x i1> %mask)310 ret void311}312 313; Pointer of struct type314 315%struct = type { ptr, i32 }316define void @masked.store.nxv2p0s_struct(<vscale x 2 x ptr> %data, ptr %vector_ptr, <vscale x 2 x i1> %mask) nounwind {317; CHECK-LABEL: masked.store.nxv2p0s_struct:318; CHECK-NEXT: st1d { z0.d }, p0, [x0]319; CHECK-NEXT: ret320 call void @llvm.masked.store.nxv2p0.p0(<vscale x 2 x ptr> %data, ptr %vector_ptr, i32 8, <vscale x 2 x i1> %mask)321 ret void322}323 324 325declare <vscale x 2 x i64> @llvm.masked.load.nxv2i64(ptr, i32, <vscale x 2 x i1>, <vscale x 2 x i64>)326declare <vscale x 4 x i32> @llvm.masked.load.nxv4i32(ptr, i32, <vscale x 4 x i1>, <vscale x 4 x i32>)327declare <vscale x 2 x i16> @llvm.masked.load.nxv2i16(ptr, i32, <vscale x 2 x i1>, <vscale x 2 x i16>)328declare <vscale x 8 x i16> @llvm.masked.load.nxv8i16(ptr, i32, <vscale x 8 x i1>, <vscale x 8 x i16>)329declare <vscale x 16 x i8> @llvm.masked.load.nxv16i8(ptr, i32, <vscale x 16 x i1>, <vscale x 16 x i8>)330 331declare <vscale x 2 x double> @llvm.masked.load.nxv2f64(ptr, i32, <vscale x 2 x i1>, <vscale x 2 x double>)332declare <vscale x 2 x float> @llvm.masked.load.nxv2f32(ptr, i32, <vscale x 2 x i1>, <vscale x 2 x float>)333declare <vscale x 2 x half> @llvm.masked.load.nxv2f16(ptr, i32, <vscale x 2 x i1>, <vscale x 2 x half>)334declare <vscale x 4 x float> @llvm.masked.load.nxv4f32(ptr, i32, <vscale x 4 x i1>, <vscale x 4 x float>)335declare <vscale x 4 x half> @llvm.masked.load.nxv4f16(ptr, i32, <vscale x 4 x i1>, <vscale x 4 x half>)336declare <vscale x 8 x half> @llvm.masked.load.nxv8f16(ptr, i32, <vscale x 8 x i1>, <vscale x 8 x half>)337declare <vscale x 2 x bfloat> @llvm.masked.load.nxv2bf16(ptr, i32, <vscale x 2 x i1>, <vscale x 2 x bfloat>)338declare <vscale x 4 x bfloat> @llvm.masked.load.nxv4bf16(ptr, i32, <vscale x 4 x i1>, <vscale x 4 x bfloat>)339declare <vscale x 8 x bfloat> @llvm.masked.load.nxv8bf16(ptr, i32, <vscale x 8 x i1>, <vscale x 8 x bfloat>)340 341declare void @llvm.masked.store.nxv2i64(<vscale x 2 x i64>, ptr, i32, <vscale x 2 x i1>)342declare void @llvm.masked.store.nxv4i32(<vscale x 4 x i32>, ptr, i32, <vscale x 4 x i1>)343declare void @llvm.masked.store.nxv8i16(<vscale x 8 x i16>, ptr, i32, <vscale x 8 x i1>)344declare void @llvm.masked.store.nxv16i8(<vscale x 16 x i8>, ptr, i32, <vscale x 16 x i1>)345 346declare void @llvm.masked.store.nxv2f64(<vscale x 2 x double>, ptr, i32, <vscale x 2 x i1>)347declare void @llvm.masked.store.nxv2f32(<vscale x 2 x float>, ptr, i32, <vscale x 2 x i1>)348declare void @llvm.masked.store.nxv2f16(<vscale x 2 x half>, ptr, i32, <vscale x 2 x i1>)349declare void @llvm.masked.store.nxv4f32(<vscale x 4 x float>, ptr, i32, <vscale x 4 x i1>)350declare void @llvm.masked.store.nxv4f16(<vscale x 4 x half>, ptr, i32, <vscale x 4 x i1>)351declare void @llvm.masked.store.nxv8f16(<vscale x 8 x half>, ptr, i32, <vscale x 8 x i1>)352declare void @llvm.masked.store.nxv2bf16(<vscale x 2 x bfloat>, ptr, i32, <vscale x 2 x i1>)353declare void @llvm.masked.store.nxv4bf16(<vscale x 4 x bfloat>, ptr, i32, <vscale x 4 x i1>)354declare void @llvm.masked.store.nxv8bf16(<vscale x 8 x bfloat>, ptr, i32, <vscale x 8 x i1>)355 356declare <vscale x 2 x ptr> @llvm.masked.load.nxv2p0.p0(ptr, i32 immarg, <vscale x 2 x i1>, <vscale x 2 x ptr>)357 358 359declare void @llvm.masked.store.nxv2p0.p0(<vscale x 2 x ptr>, ptr, i32 immarg, <vscale x 2 x i1>)360 361 362; +bf16 is required for the bfloat version.363attributes #0 = { "target-features"="+sve,+bf16" }364