132 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -enable-misched=false < %s | FileCheck %s3 4target triple = "aarch64-linux-gnu"5 6; Tests that exercise various type legalisation scenarios for ISD::MSCATTER.7 8; Code generate the scenario where the offset vector type is illegal.9define void @masked_scatter_nxv16i8(<vscale x 16 x i8> %data, ptr %base, <vscale x 16 x i8> %offsets, <vscale x 16 x i1> %mask) #0 {10; CHECK-LABEL: masked_scatter_nxv16i8:11; CHECK: // %bb.0:12; CHECK-NEXT: sunpklo z2.h, z1.b13; CHECK-NEXT: uunpklo z4.h, z0.b14; CHECK-NEXT: punpklo p1.h, p0.b15; CHECK-NEXT: sunpkhi z1.h, z1.b16; CHECK-NEXT: uunpkhi z0.h, z0.b17; CHECK-NEXT: punpkhi p0.h, p0.b18; CHECK-NEXT: punpklo p2.h, p1.b19; CHECK-NEXT: punpkhi p1.h, p1.b20; CHECK-NEXT: sunpklo z3.s, z2.h21; CHECK-NEXT: uunpklo z5.s, z4.h22; CHECK-NEXT: sunpkhi z2.s, z2.h23; CHECK-NEXT: st1b { z5.s }, p2, [x0, z3.s, sxtw]24; CHECK-NEXT: uunpkhi z3.s, z4.h25; CHECK-NEXT: st1b { z3.s }, p1, [x0, z2.s, sxtw]26; CHECK-NEXT: sunpklo z2.s, z1.h27; CHECK-NEXT: uunpklo z3.s, z0.h28; CHECK-NEXT: sunpkhi z1.s, z1.h29; CHECK-NEXT: uunpkhi z0.s, z0.h30; CHECK-NEXT: punpklo p1.h, p0.b31; CHECK-NEXT: punpkhi p0.h, p0.b32; CHECK-NEXT: st1b { z3.s }, p1, [x0, z2.s, sxtw]33; CHECK-NEXT: st1b { z0.s }, p0, [x0, z1.s, sxtw]34; CHECK-NEXT: ret35 %ptrs = getelementptr i8, ptr %base, <vscale x 16 x i8> %offsets36 call void @llvm.masked.scatter.nxv16i8(<vscale x 16 x i8> %data, <vscale x 16 x ptr> %ptrs, i32 1, <vscale x 16 x i1> %mask)37 ret void38}39 40define void @masked_scatter_nxv8i16(<vscale x 8 x i16> %data, ptr %base, <vscale x 8 x i16> %offsets, <vscale x 8 x i1> %mask) #0 {41; CHECK-LABEL: masked_scatter_nxv8i16:42; CHECK: // %bb.0:43; CHECK-NEXT: sunpklo z2.s, z1.h44; CHECK-NEXT: uunpklo z3.s, z0.h45; CHECK-NEXT: sunpkhi z1.s, z1.h46; CHECK-NEXT: uunpkhi z0.s, z0.h47; CHECK-NEXT: punpklo p1.h, p0.b48; CHECK-NEXT: punpkhi p0.h, p0.b49; CHECK-NEXT: st1h { z3.s }, p1, [x0, z2.s, sxtw #1]50; CHECK-NEXT: st1h { z0.s }, p0, [x0, z1.s, sxtw #1]51; CHECK-NEXT: ret52 %ptrs = getelementptr i16, ptr %base, <vscale x 8 x i16> %offsets53 call void @llvm.masked.scatter.nxv8i16(<vscale x 8 x i16> %data, <vscale x 8 x ptr> %ptrs, i32 1, <vscale x 8 x i1> %mask)54 ret void55}56 57define void @masked_scatter_nxv8bf16(<vscale x 8 x bfloat> %data, ptr %base, <vscale x 8 x i16> %offsets, <vscale x 8 x i1> %mask) #0 {58; CHECK-LABEL: masked_scatter_nxv8bf16:59; CHECK: // %bb.0:60; CHECK-NEXT: sunpklo z2.s, z1.h61; CHECK-NEXT: uunpklo z3.s, z0.h62; CHECK-NEXT: sunpkhi z1.s, z1.h63; CHECK-NEXT: uunpkhi z0.s, z0.h64; CHECK-NEXT: punpklo p1.h, p0.b65; CHECK-NEXT: punpkhi p0.h, p0.b66; CHECK-NEXT: st1h { z3.s }, p1, [x0, z2.s, sxtw #1]67; CHECK-NEXT: st1h { z0.s }, p0, [x0, z1.s, sxtw #1]68; CHECK-NEXT: ret69 %ptrs = getelementptr bfloat, ptr %base, <vscale x 8 x i16> %offsets70 call void @llvm.masked.scatter.nxv8bf16(<vscale x 8 x bfloat> %data, <vscale x 8 x ptr> %ptrs, i32 1, <vscale x 8 x i1> %mask)71 ret void72}73 74define void @masked_scatter_nxv8f32(<vscale x 8 x float> %data, ptr %base, <vscale x 8 x i32> %indexes, <vscale x 8 x i1> %masks) #0 {75; CHECK-LABEL: masked_scatter_nxv8f32:76; CHECK: // %bb.0:77; CHECK-NEXT: punpklo p1.h, p0.b78; CHECK-NEXT: punpkhi p0.h, p0.b79; CHECK-NEXT: st1w { z0.s }, p1, [x0, z2.s, uxtw #2]80; CHECK-NEXT: st1w { z1.s }, p0, [x0, z3.s, uxtw #2]81; CHECK-NEXT: ret82 %ext = zext <vscale x 8 x i32> %indexes to <vscale x 8 x i64>83 %ptrs = getelementptr float, ptr %base, <vscale x 8 x i64> %ext84 call void @llvm.masked.scatter.nxv8f32(<vscale x 8 x float> %data, <vscale x 8 x ptr> %ptrs, i32 0, <vscale x 8 x i1> %masks)85 ret void86}87 88; Code generate the worst case scenario when all vector types are illegal.89define void @masked_scatter_nxv32i32(<vscale x 32 x i32> %data, ptr %base, <vscale x 32 x i32> %offsets, <vscale x 32 x i1> %mask) #0 {90; CHECK-LABEL: masked_scatter_nxv32i32:91; CHECK: // %bb.0:92; CHECK-NEXT: punpklo p2.h, p0.b93; CHECK-NEXT: ldr z30, [x1, #1, mul vl]94; CHECK-NEXT: ldr z31, [x1]95; CHECK-NEXT: punpkhi p0.h, p0.b96; CHECK-NEXT: ldr z28, [x1, #3, mul vl]97; CHECK-NEXT: ldr z29, [x1, #2, mul vl]98; CHECK-NEXT: punpklo p3.h, p2.b99; CHECK-NEXT: ldr z24, [x1, #7, mul vl]100; CHECK-NEXT: ldr z25, [x1, #6, mul vl]101; CHECK-NEXT: punpkhi p2.h, p2.b102; CHECK-NEXT: ldr z26, [x1, #5, mul vl]103; CHECK-NEXT: ldr z27, [x1, #4, mul vl]104; CHECK-NEXT: st1w { z0.s }, p3, [x0, z31.s, sxtw #2]105; CHECK-NEXT: st1w { z1.s }, p2, [x0, z30.s, sxtw #2]106; CHECK-NEXT: punpklo p2.h, p0.b107; CHECK-NEXT: punpkhi p0.h, p0.b108; CHECK-NEXT: st1w { z2.s }, p2, [x0, z29.s, sxtw #2]109; CHECK-NEXT: st1w { z3.s }, p0, [x0, z28.s, sxtw #2]110; CHECK-NEXT: punpklo p0.h, p1.b111; CHECK-NEXT: punpklo p2.h, p0.b112; CHECK-NEXT: punpkhi p0.h, p0.b113; CHECK-NEXT: st1w { z4.s }, p2, [x0, z27.s, sxtw #2]114; CHECK-NEXT: st1w { z5.s }, p0, [x0, z26.s, sxtw #2]115; CHECK-NEXT: punpkhi p0.h, p1.b116; CHECK-NEXT: punpklo p1.h, p0.b117; CHECK-NEXT: punpkhi p0.h, p0.b118; CHECK-NEXT: st1w { z6.s }, p1, [x0, z25.s, sxtw #2]119; CHECK-NEXT: st1w { z7.s }, p0, [x0, z24.s, sxtw #2]120; CHECK-NEXT: ret121 %ptrs = getelementptr i32, ptr %base, <vscale x 32 x i32> %offsets122 call void @llvm.masked.scatter.nxv32i32(<vscale x 32 x i32> %data, <vscale x 32 x ptr> %ptrs, i32 4, <vscale x 32 x i1> %mask)123 ret void124}125 126declare void @llvm.masked.scatter.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x ptr>, i32, <vscale x 16 x i1>)127declare void @llvm.masked.scatter.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x ptr>, i32, <vscale x 8 x i1>)128declare void @llvm.masked.scatter.nxv8f32(<vscale x 8 x float>, <vscale x 8 x ptr>, i32, <vscale x 8 x i1>)129declare void @llvm.masked.scatter.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x ptr>, i32, <vscale x 8 x i1>)130declare void @llvm.masked.scatter.nxv32i32(<vscale x 32 x i32>, <vscale x 32 x ptr>, i32, <vscale x 32 x i1>)131attributes #0 = { nounwind "target-features"="+sve,+bf16" }132