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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mattr=+sve -mtriple=aarch64 %s -o - | FileCheck %s --check-prefixes=CHECK3 4; These tests just check that the plumbing is in place for @llvm.smax, @llvm.umax,5; @llvm.smin, @llvm.umin.6 7; tests for smax:8 9define <vscale x 16 x i8> @smax_select_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {10; CHECK-LABEL: smax_select_i8:11; CHECK: // %bb.0:12; CHECK-NEXT: smax z0.b, p0/m, z0.b, z1.b13; CHECK-NEXT: ret14 %sel = call <vscale x 16 x i8> @llvm.smax.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)15 %out = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %sel, <vscale x 16 x i8> %a16 ret <vscale x 16 x i8> %out17}18 19define <vscale x 8 x i16> @smax_select_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {20; CHECK-LABEL: smax_select_i16:21; CHECK: // %bb.0:22; CHECK-NEXT: smax z0.h, p0/m, z0.h, z1.h23; CHECK-NEXT: ret24 %sel = call <vscale x 8 x i16> @llvm.smax.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)25 %out = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %sel, <vscale x 8 x i16> %a26 ret <vscale x 8 x i16> %out27}28 29define <vscale x 4 x i32> @smax_select_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {30; CHECK-LABEL: smax_select_i32:31; CHECK: // %bb.0:32; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s33; CHECK-NEXT: ret34 %sel = call <vscale x 4 x i32> @llvm.smax.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)35 %out = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %sel, <vscale x 4 x i32> %a36 ret <vscale x 4 x i32> %out37}38 39define <vscale x 2 x i64> @smax_select_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {40; CHECK-LABEL: smax_select_i64:41; CHECK: // %bb.0:42; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d43; CHECK-NEXT: ret44 %sel = call <vscale x 2 x i64> @llvm.smax.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)45 %out = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %sel, <vscale x 2 x i64> %a46 ret <vscale x 2 x i64> %out47}48 49; tests for umax:50 51define <vscale x 16 x i8> @umax_select_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {52; CHECK-LABEL: umax_select_i8:53; CHECK: // %bb.0:54; CHECK-NEXT: umax z0.b, p0/m, z0.b, z1.b55; CHECK-NEXT: ret56 %sel = call <vscale x 16 x i8> @llvm.umax.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)57 %out = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %sel, <vscale x 16 x i8> %a58 ret <vscale x 16 x i8> %out59}60 61define <vscale x 8 x i16> @umax_select_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {62; CHECK-LABEL: umax_select_i16:63; CHECK: // %bb.0:64; CHECK-NEXT: umax z0.h, p0/m, z0.h, z1.h65; CHECK-NEXT: ret66 %sel = call <vscale x 8 x i16> @llvm.umax.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)67 %out = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %sel, <vscale x 8 x i16> %a68 ret <vscale x 8 x i16> %out69}70 71define <vscale x 4 x i32> @umax_select_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {72; CHECK-LABEL: umax_select_i32:73; CHECK: // %bb.0:74; CHECK-NEXT: umax z0.s, p0/m, z0.s, z1.s75; CHECK-NEXT: ret76 %sel = call <vscale x 4 x i32> @llvm.umax.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)77 %out = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %sel, <vscale x 4 x i32> %a78 ret <vscale x 4 x i32> %out79}80 81define <vscale x 2 x i64> @umax_select_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {82; CHECK-LABEL: umax_select_i64:83; CHECK: // %bb.0:84; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d85; CHECK-NEXT: ret86 %sel = call <vscale x 2 x i64> @llvm.umax.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)87 %out = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %sel, <vscale x 2 x i64> %a88 ret <vscale x 2 x i64> %out89}90 91; tests for smin:92 93define <vscale x 16 x i8> @smin_select_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {94; CHECK-LABEL: smin_select_i8:95; CHECK: // %bb.0:96; CHECK-NEXT: smin z0.b, p0/m, z0.b, z1.b97; CHECK-NEXT: ret98 %sel = call <vscale x 16 x i8> @llvm.smin.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)99 %out = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %sel, <vscale x 16 x i8> %a100 ret <vscale x 16 x i8> %out101}102 103define <vscale x 8 x i16> @smin_select_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {104; CHECK-LABEL: smin_select_i16:105; CHECK: // %bb.0:106; CHECK-NEXT: smin z0.h, p0/m, z0.h, z1.h107; CHECK-NEXT: ret108 %sel = call <vscale x 8 x i16> @llvm.smin.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)109 %out = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %sel, <vscale x 8 x i16> %a110 ret <vscale x 8 x i16> %out111}112 113define <vscale x 4 x i32> @smin_select_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {114; CHECK-LABEL: smin_select_i32:115; CHECK: // %bb.0:116; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s117; CHECK-NEXT: ret118 %sel = call <vscale x 4 x i32> @llvm.smin.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)119 %out = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %sel, <vscale x 4 x i32> %a120 ret <vscale x 4 x i32> %out121}122 123define <vscale x 2 x i64> @smin_select_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {124; CHECK-LABEL: smin_select_i64:125; CHECK: // %bb.0:126; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d127; CHECK-NEXT: ret128 %sel = call <vscale x 2 x i64> @llvm.smin.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)129 %out = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %sel, <vscale x 2 x i64> %a130 ret <vscale x 2 x i64> %out131}132 133; tests for umin:134 135define <vscale x 16 x i8> @umin_select_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {136; CHECK-LABEL: umin_select_i8:137; CHECK: // %bb.0:138; CHECK-NEXT: umin z0.b, p0/m, z0.b, z1.b139; CHECK-NEXT: ret140 %sel = call <vscale x 16 x i8> @llvm.umin.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)141 %out = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %sel, <vscale x 16 x i8> %a142 ret <vscale x 16 x i8> %out143}144 145define <vscale x 8 x i16> @umin_select_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {146; CHECK-LABEL: umin_select_i16:147; CHECK: // %bb.0:148; CHECK-NEXT: umin z0.h, p0/m, z0.h, z1.h149; CHECK-NEXT: ret150 %sel = call <vscale x 8 x i16> @llvm.umin.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)151 %out = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %sel, <vscale x 8 x i16> %a152 ret <vscale x 8 x i16> %out153}154 155define <vscale x 4 x i32> @umin_select_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {156; CHECK-LABEL: umin_select_i32:157; CHECK: // %bb.0:158; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s159; CHECK-NEXT: ret160 %sel = call <vscale x 4 x i32> @llvm.umin.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)161 %out = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %sel, <vscale x 4 x i32> %a162 ret <vscale x 4 x i32> %out163}164 165define <vscale x 2 x i64> @umin_select_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {166; CHECK-LABEL: umin_select_i64:167; CHECK: // %bb.0:168; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d169; CHECK-NEXT: ret170 %sel = call <vscale x 2 x i64> @llvm.umin.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)171 %out = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %sel, <vscale x 2 x i64> %a172 ret <vscale x 2 x i64> %out173}174 175 176define <vscale x 2 x i64> @umin_select_i64_multiuse(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, ptr %p) {177; CHECK-LABEL: umin_select_i64_multiuse:178; CHECK: // %bb.0:179; CHECK-NEXT: ptrue p1.d180; CHECK-NEXT: umin z1.d, p1/m, z1.d, z0.d181; CHECK-NEXT: mov z0.d, p0/m, z1.d182; CHECK-NEXT: str z1, [x0]183; CHECK-NEXT: ret184 %sel = call <vscale x 2 x i64> @llvm.umin.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)185 store <vscale x 2 x i64> %sel, ptr %p186 %out = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %sel, <vscale x 2 x i64> %a187 ret <vscale x 2 x i64> %out188}189 190define <vscale x 2 x i64> @smin_select_i64_c(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {191; CHECK-LABEL: smin_select_i64_c:192; CHECK: // %bb.0:193; CHECK-NEXT: smin z1.d, p0/m, z1.d, z0.d194; CHECK-NEXT: mov z0.d, z1.d195; CHECK-NEXT: ret196 %sel = call <vscale x 2 x i64> @llvm.smin.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)197 %out = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %sel, <vscale x 2 x i64> %b198 ret <vscale x 2 x i64> %out199}200 201define <vscale x 2 x i64> @smax_select_i64_c(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {202; CHECK-LABEL: smax_select_i64_c:203; CHECK: // %bb.0:204; CHECK-NEXT: smax z1.d, p0/m, z1.d, z0.d205; CHECK-NEXT: mov z0.d, z1.d206; CHECK-NEXT: ret207 %sel = call <vscale x 2 x i64> @llvm.smax.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)208 %out = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %sel, <vscale x 2 x i64> %b209 ret <vscale x 2 x i64> %out210}211 212define <vscale x 2 x i64> @umin_select_i64_c(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {213; CHECK-LABEL: umin_select_i64_c:214; CHECK: // %bb.0:215; CHECK-NEXT: umin z1.d, p0/m, z1.d, z0.d216; CHECK-NEXT: mov z0.d, z1.d217; CHECK-NEXT: ret218 %sel = call <vscale x 2 x i64> @llvm.umin.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)219 %out = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %sel, <vscale x 2 x i64> %b220 ret <vscale x 2 x i64> %out221}222 223define <vscale x 2 x i64> @umax_select_i64_c(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {224; CHECK-LABEL: umax_select_i64_c:225; CHECK: // %bb.0:226; CHECK-NEXT: umax z1.d, p0/m, z1.d, z0.d227; CHECK-NEXT: mov z0.d, z1.d228; CHECK-NEXT: ret229 %sel = call <vscale x 2 x i64> @llvm.umax.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)230 %out = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %sel, <vscale x 2 x i64> %b231 ret <vscale x 2 x i64> %out232}233 234 235declare <vscale x 16 x i8> @llvm.smax.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)236declare <vscale x 8 x i16> @llvm.smax.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)237declare <vscale x 4 x i32> @llvm.smax.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)238declare <vscale x 2 x i64> @llvm.smax.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)239 240declare <vscale x 16 x i8> @llvm.umax.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)241declare <vscale x 8 x i16> @llvm.umax.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)242declare <vscale x 4 x i32> @llvm.umax.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)243declare <vscale x 2 x i64> @llvm.umax.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)244 245declare <vscale x 16 x i8> @llvm.smin.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)246declare <vscale x 8 x i16> @llvm.smin.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)247declare <vscale x 4 x i32> @llvm.smin.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)248declare <vscale x 2 x i64> @llvm.smin.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)249 250declare <vscale x 16 x i8> @llvm.umin.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)251declare <vscale x 8 x i16> @llvm.umin.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)252declare <vscale x 4 x i32> @llvm.umin.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)253declare <vscale x 2 x i64> @llvm.umin.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)254