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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4; Zeroing.5 6define <vscale x 16 x i8> @mov_z_b(<vscale x 16 x i1> %pg) {7; CHECK-LABEL: mov_z_b:8; CHECK: // %bb.0:9; CHECK-NEXT: mov z0.b, p0/z, #1 // =0x110; CHECK-NEXT: ret11 %r = tail call <vscale x 16 x i8> @llvm.aarch64.sve.dup.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %pg, i8 1)12 ret <vscale x 16 x i8> %r13}14 15define <vscale x 8 x i16> @mov_z_h(<vscale x 8 x i1> %pg) {16; CHECK-LABEL: mov_z_h:17; CHECK: // %bb.0:18; CHECK-NEXT: mov z0.h, p0/z, #1 // =0x119; CHECK-NEXT: ret20 %r = tail call <vscale x 8 x i16> @llvm.aarch64.sve.dup.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %pg, i16 1)21 ret <vscale x 8 x i16> %r22}23 24define <vscale x 4 x i32> @mov_z_s(<vscale x 4 x i1> %pg) {25; CHECK-LABEL: mov_z_s:26; CHECK: // %bb.0:27; CHECK-NEXT: mov z0.s, p0/z, #1 // =0x128; CHECK-NEXT: ret29 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %pg, i32 1)30 ret <vscale x 4 x i32> %r31}32 33define <vscale x 2 x i64> @mov_z_d(<vscale x 2 x i1> %pg) {34; CHECK-LABEL: mov_z_d:35; CHECK: // %bb.0:36; CHECK-NEXT: mov z0.d, p0/z, #1 // =0x137; CHECK-NEXT: ret38 %r = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, i64 1)39 ret <vscale x 2 x i64> %r40}41 42; Merging.43 44define <vscale x 16 x i8> @mov_m_b(<vscale x 16 x i8> %zd, <vscale x 16 x i1> %pg) {45; CHECK-LABEL: mov_m_b:46; CHECK: // %bb.0:47; CHECK-NEXT: mov z0.b, p0/m, #1 // =0x148; CHECK-NEXT: ret49 %r = tail call <vscale x 16 x i8> @llvm.aarch64.sve.dup.nxv16i8(<vscale x 16 x i8> %zd, <vscale x 16 x i1> %pg, i8 1)50 ret <vscale x 16 x i8> %r51}52 53define <vscale x 8 x i16> @mov_m_h(<vscale x 8 x i16> %zd, <vscale x 8 x i1> %pg) {54; CHECK-LABEL: mov_m_h:55; CHECK: // %bb.0:56; CHECK-NEXT: mov z0.h, p0/m, #1 // =0x157; CHECK-NEXT: ret58 %r = tail call <vscale x 8 x i16> @llvm.aarch64.sve.dup.nxv8i16(<vscale x 8 x i16> %zd, <vscale x 8 x i1> %pg, i16 1)59 ret <vscale x 8 x i16> %r60}61 62define <vscale x 4 x i32> @mov_m_s(<vscale x 4 x i32> %zd, <vscale x 4 x i1> %pg) {63; CHECK-LABEL: mov_m_s:64; CHECK: // %bb.0:65; CHECK-NEXT: mov z0.s, p0/m, #1 // =0x166; CHECK-NEXT: ret67 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.nxv4i32(<vscale x 4 x i32> %zd, <vscale x 4 x i1> %pg, i32 1)68 ret <vscale x 4 x i32> %r69}70 71define <vscale x 2 x i64> @mov_m_d(<vscale x 2 x i64> %zd, <vscale x 2 x i1> %pg) {72; CHECK-LABEL: mov_m_d:73; CHECK: // %bb.0:74; CHECK-NEXT: mov z0.d, p0/m, #1 // =0x175; CHECK-NEXT: ret76 %r = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.nxv2i64(<vscale x 2 x i64> %zd, <vscale x 2 x i1> %pg, i64 1)77 ret <vscale x 2 x i64> %r78}79 80declare <vscale x 16 x i8> @llvm.aarch64.sve.dup.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, i8)81declare <vscale x 8 x i16> @llvm.aarch64.sve.dup.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, i16)82declare <vscale x 4 x i32> @llvm.aarch64.sve.dup.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32)83declare <vscale x 2 x i64> @llvm.aarch64.sve.dup.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i64)84