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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64 -mattr=+sve %s -o - | FileCheck %s --check-prefix=CHECK-SVE3; RUN: llc -mtriple=aarch64 -mattr=+sve2 %s -o - | FileCheck %s --check-prefix=CHECK-SVE24 5define <vscale x 2 x i64> @signed_wide_add_nxv4i32(<vscale x 2 x i64> %acc, <vscale x 4 x i32> %input){6; CHECK-SVE-LABEL: signed_wide_add_nxv4i32:7; CHECK-SVE: // %bb.0: // %entry8; CHECK-SVE-NEXT: sunpklo z2.d, z1.s9; CHECK-SVE-NEXT: sunpkhi z1.d, z1.s10; CHECK-SVE-NEXT: add z0.d, z0.d, z2.d11; CHECK-SVE-NEXT: add z0.d, z0.d, z1.d12; CHECK-SVE-NEXT: ret13;14; CHECK-SVE2-LABEL: signed_wide_add_nxv4i32:15; CHECK-SVE2: // %bb.0: // %entry16; CHECK-SVE2-NEXT: saddwb z0.d, z0.d, z1.s17; CHECK-SVE2-NEXT: saddwt z0.d, z0.d, z1.s18; CHECK-SVE2-NEXT: ret19entry:20 %input.wide = sext <vscale x 4 x i32> %input to <vscale x 4 x i64>21 %partial.reduce = tail call <vscale x 2 x i64> @llvm.vector.partial.reduce.add.nxv2i64.nxv4i64(<vscale x 2 x i64> %acc, <vscale x 4 x i64> %input.wide)22 ret <vscale x 2 x i64> %partial.reduce23}24 25define <vscale x 2 x i64> @unsigned_wide_add_nxv4i32(<vscale x 2 x i64> %acc, <vscale x 4 x i32> %input){26; CHECK-SVE-LABEL: unsigned_wide_add_nxv4i32:27; CHECK-SVE: // %bb.0: // %entry28; CHECK-SVE-NEXT: uunpklo z2.d, z1.s29; CHECK-SVE-NEXT: uunpkhi z1.d, z1.s30; CHECK-SVE-NEXT: add z0.d, z0.d, z2.d31; CHECK-SVE-NEXT: add z0.d, z0.d, z1.d32; CHECK-SVE-NEXT: ret33;34; CHECK-SVE2-LABEL: unsigned_wide_add_nxv4i32:35; CHECK-SVE2: // %bb.0: // %entry36; CHECK-SVE2-NEXT: uaddwb z0.d, z0.d, z1.s37; CHECK-SVE2-NEXT: uaddwt z0.d, z0.d, z1.s38; CHECK-SVE2-NEXT: ret39entry:40 %input.wide = zext <vscale x 4 x i32> %input to <vscale x 4 x i64>41 %partial.reduce = tail call <vscale x 2 x i64> @llvm.vector.partial.reduce.add.nxv2i64.nxv4i64(<vscale x 2 x i64> %acc, <vscale x 4 x i64> %input.wide)42 ret <vscale x 2 x i64> %partial.reduce43}44 45define <vscale x 4 x i32> @signed_wide_add_nxv8i16(<vscale x 4 x i32> %acc, <vscale x 8 x i16> %input){46; CHECK-SVE-LABEL: signed_wide_add_nxv8i16:47; CHECK-SVE: // %bb.0: // %entry48; CHECK-SVE-NEXT: sunpklo z2.s, z1.h49; CHECK-SVE-NEXT: sunpkhi z1.s, z1.h50; CHECK-SVE-NEXT: add z0.s, z0.s, z2.s51; CHECK-SVE-NEXT: add z0.s, z0.s, z1.s52; CHECK-SVE-NEXT: ret53;54; CHECK-SVE2-LABEL: signed_wide_add_nxv8i16:55; CHECK-SVE2: // %bb.0: // %entry56; CHECK-SVE2-NEXT: saddwb z0.s, z0.s, z1.h57; CHECK-SVE2-NEXT: saddwt z0.s, z0.s, z1.h58; CHECK-SVE2-NEXT: ret59entry:60 %input.wide = sext <vscale x 8 x i16> %input to <vscale x 8 x i32>61 %partial.reduce = tail call <vscale x 4 x i32> @llvm.vector.partial.reduce.add.nxv4i32.nxv8i32(<vscale x 4 x i32> %acc, <vscale x 8 x i32> %input.wide)62 ret <vscale x 4 x i32> %partial.reduce63}64 65define <vscale x 4 x i32> @unsigned_wide_add_nxv8i16(<vscale x 4 x i32> %acc, <vscale x 8 x i16> %input){66; CHECK-SVE-LABEL: unsigned_wide_add_nxv8i16:67; CHECK-SVE: // %bb.0: // %entry68; CHECK-SVE-NEXT: uunpklo z2.s, z1.h69; CHECK-SVE-NEXT: uunpkhi z1.s, z1.h70; CHECK-SVE-NEXT: add z0.s, z0.s, z2.s71; CHECK-SVE-NEXT: add z0.s, z0.s, z1.s72; CHECK-SVE-NEXT: ret73;74; CHECK-SVE2-LABEL: unsigned_wide_add_nxv8i16:75; CHECK-SVE2: // %bb.0: // %entry76; CHECK-SVE2-NEXT: uaddwb z0.s, z0.s, z1.h77; CHECK-SVE2-NEXT: uaddwt z0.s, z0.s, z1.h78; CHECK-SVE2-NEXT: ret79entry:80 %input.wide = zext <vscale x 8 x i16> %input to <vscale x 8 x i32>81 %partial.reduce = tail call <vscale x 4 x i32> @llvm.vector.partial.reduce.add.nxv4i32.nxv8i32(<vscale x 4 x i32> %acc, <vscale x 8 x i32> %input.wide)82 ret <vscale x 4 x i32> %partial.reduce83}84 85define <vscale x 8 x i16> @signed_wide_add_nxv16i8(<vscale x 8 x i16> %acc, <vscale x 16 x i8> %input){86; CHECK-SVE-LABEL: signed_wide_add_nxv16i8:87; CHECK-SVE: // %bb.0: // %entry88; CHECK-SVE-NEXT: sunpklo z2.h, z1.b89; CHECK-SVE-NEXT: sunpkhi z1.h, z1.b90; CHECK-SVE-NEXT: add z0.h, z0.h, z2.h91; CHECK-SVE-NEXT: add z0.h, z0.h, z1.h92; CHECK-SVE-NEXT: ret93;94; CHECK-SVE2-LABEL: signed_wide_add_nxv16i8:95; CHECK-SVE2: // %bb.0: // %entry96; CHECK-SVE2-NEXT: saddwb z0.h, z0.h, z1.b97; CHECK-SVE2-NEXT: saddwt z0.h, z0.h, z1.b98; CHECK-SVE2-NEXT: ret99entry:100 %input.wide = sext <vscale x 16 x i8> %input to <vscale x 16 x i16>101 %partial.reduce = tail call <vscale x 8 x i16> @llvm.vector.partial.reduce.add.nxv8i16.nxv16i16(<vscale x 8 x i16> %acc, <vscale x 16 x i16> %input.wide)102 ret <vscale x 8 x i16> %partial.reduce103}104 105define <vscale x 8 x i16> @unsigned_wide_add_nxv16i8(<vscale x 8 x i16> %acc, <vscale x 16 x i8> %input){106; CHECK-SVE-LABEL: unsigned_wide_add_nxv16i8:107; CHECK-SVE: // %bb.0: // %entry108; CHECK-SVE-NEXT: uunpklo z2.h, z1.b109; CHECK-SVE-NEXT: uunpkhi z1.h, z1.b110; CHECK-SVE-NEXT: add z0.h, z0.h, z2.h111; CHECK-SVE-NEXT: add z0.h, z0.h, z1.h112; CHECK-SVE-NEXT: ret113;114; CHECK-SVE2-LABEL: unsigned_wide_add_nxv16i8:115; CHECK-SVE2: // %bb.0: // %entry116; CHECK-SVE2-NEXT: uaddwb z0.h, z0.h, z1.b117; CHECK-SVE2-NEXT: uaddwt z0.h, z0.h, z1.b118; CHECK-SVE2-NEXT: ret119entry:120 %input.wide = zext <vscale x 16 x i8> %input to <vscale x 16 x i16>121 %partial.reduce = tail call <vscale x 8 x i16> @llvm.vector.partial.reduce.add.nxv8i16.nxv16i16(<vscale x 8 x i16> %acc, <vscale x 16 x i16> %input.wide)122 ret <vscale x 8 x i16> %partial.reduce123}124 125define <vscale x 2 x i32> @signed_wide_add_nxv4i16(<vscale x 2 x i32> %acc, <vscale x 4 x i16> %input){126; CHECK-SVE-LABEL: signed_wide_add_nxv4i16:127; CHECK-SVE: // %bb.0: // %entry128; CHECK-SVE-NEXT: ptrue p0.s129; CHECK-SVE-NEXT: sxth z1.s, p0/m, z1.s130; CHECK-SVE-NEXT: uunpklo z2.d, z1.s131; CHECK-SVE-NEXT: uunpkhi z1.d, z1.s132; CHECK-SVE-NEXT: add z0.d, z0.d, z2.d133; CHECK-SVE-NEXT: add z0.d, z1.d, z0.d134; CHECK-SVE-NEXT: ret135;136; CHECK-SVE2-LABEL: signed_wide_add_nxv4i16:137; CHECK-SVE2: // %bb.0: // %entry138; CHECK-SVE2-NEXT: ptrue p0.s139; CHECK-SVE2-NEXT: sxth z1.s, p0/m, z1.s140; CHECK-SVE2-NEXT: saddwb z0.d, z0.d, z1.s141; CHECK-SVE2-NEXT: saddwt z0.d, z0.d, z1.s142; CHECK-SVE2-NEXT: ret143entry:144 %input.wide = sext <vscale x 4 x i16> %input to <vscale x 4 x i32>145 %partial.reduce = tail call <vscale x 2 x i32> @llvm.vector.partial.reduce.add.nxv2i32.nxv4i32(<vscale x 2 x i32> %acc, <vscale x 4 x i32> %input.wide)146 ret <vscale x 2 x i32> %partial.reduce147}148 149define <vscale x 2 x i32> @unsigned_wide_add_nxv4i16(<vscale x 2 x i32> %acc, <vscale x 4 x i16> %input){150; CHECK-SVE-LABEL: unsigned_wide_add_nxv4i16:151; CHECK-SVE: // %bb.0: // %entry152; CHECK-SVE-NEXT: and z1.s, z1.s, #0xffff153; CHECK-SVE-NEXT: uunpklo z2.d, z1.s154; CHECK-SVE-NEXT: uunpkhi z1.d, z1.s155; CHECK-SVE-NEXT: add z0.d, z0.d, z2.d156; CHECK-SVE-NEXT: add z0.d, z1.d, z0.d157; CHECK-SVE-NEXT: ret158;159; CHECK-SVE2-LABEL: unsigned_wide_add_nxv4i16:160; CHECK-SVE2: // %bb.0: // %entry161; CHECK-SVE2-NEXT: and z1.s, z1.s, #0xffff162; CHECK-SVE2-NEXT: uaddwb z0.d, z0.d, z1.s163; CHECK-SVE2-NEXT: uaddwt z0.d, z0.d, z1.s164; CHECK-SVE2-NEXT: ret165entry:166 %input.wide = zext <vscale x 4 x i16> %input to <vscale x 4 x i32>167 %partial.reduce = tail call <vscale x 2 x i32> @llvm.vector.partial.reduce.add.nxv2i32.nxv4i32(<vscale x 2 x i32> %acc, <vscale x 4 x i32> %input.wide)168 ret <vscale x 2 x i32> %partial.reduce169}170 171define <vscale x 4 x i64> @signed_wide_add_nxv8i32(<vscale x 4 x i64> %acc, <vscale x 8 x i32> %input){172; CHECK-SVE-LABEL: signed_wide_add_nxv8i32:173; CHECK-SVE: // %bb.0: // %entry174; CHECK-SVE-NEXT: sunpklo z4.d, z3.s175; CHECK-SVE-NEXT: sunpklo z5.d, z2.s176; CHECK-SVE-NEXT: sunpkhi z3.d, z3.s177; CHECK-SVE-NEXT: sunpkhi z2.d, z2.s178; CHECK-SVE-NEXT: add z0.d, z0.d, z5.d179; CHECK-SVE-NEXT: add z1.d, z1.d, z4.d180; CHECK-SVE-NEXT: add z0.d, z0.d, z2.d181; CHECK-SVE-NEXT: add z1.d, z1.d, z3.d182; CHECK-SVE-NEXT: ret183;184; CHECK-SVE2-LABEL: signed_wide_add_nxv8i32:185; CHECK-SVE2: // %bb.0: // %entry186; CHECK-SVE2-NEXT: saddwb z1.d, z1.d, z3.s187; CHECK-SVE2-NEXT: saddwb z0.d, z0.d, z2.s188; CHECK-SVE2-NEXT: saddwt z1.d, z1.d, z3.s189; CHECK-SVE2-NEXT: saddwt z0.d, z0.d, z2.s190; CHECK-SVE2-NEXT: ret191entry:192 %input.wide = sext <vscale x 8 x i32> %input to <vscale x 8 x i64>193 %partial.reduce = tail call <vscale x 4 x i64> @llvm.vector.partial.reduce.add.nxv4i64.nxv8i64(<vscale x 4 x i64> %acc, <vscale x 8 x i64> %input.wide)194 ret <vscale x 4 x i64> %partial.reduce195}196 197define <vscale x 4 x i64> @unsigned_wide_add_nxv8i32(<vscale x 4 x i64> %acc, <vscale x 8 x i32> %input){198; CHECK-SVE-LABEL: unsigned_wide_add_nxv8i32:199; CHECK-SVE: // %bb.0: // %entry200; CHECK-SVE-NEXT: uunpklo z4.d, z3.s201; CHECK-SVE-NEXT: uunpklo z5.d, z2.s202; CHECK-SVE-NEXT: uunpkhi z3.d, z3.s203; CHECK-SVE-NEXT: uunpkhi z2.d, z2.s204; CHECK-SVE-NEXT: add z0.d, z0.d, z5.d205; CHECK-SVE-NEXT: add z1.d, z1.d, z4.d206; CHECK-SVE-NEXT: add z0.d, z0.d, z2.d207; CHECK-SVE-NEXT: add z1.d, z1.d, z3.d208; CHECK-SVE-NEXT: ret209;210; CHECK-SVE2-LABEL: unsigned_wide_add_nxv8i32:211; CHECK-SVE2: // %bb.0: // %entry212; CHECK-SVE2-NEXT: uaddwb z1.d, z1.d, z3.s213; CHECK-SVE2-NEXT: uaddwb z0.d, z0.d, z2.s214; CHECK-SVE2-NEXT: uaddwt z1.d, z1.d, z3.s215; CHECK-SVE2-NEXT: uaddwt z0.d, z0.d, z2.s216; CHECK-SVE2-NEXT: ret217entry:218 %input.wide = zext <vscale x 8 x i32> %input to <vscale x 8 x i64>219 %partial.reduce = tail call <vscale x 4 x i64> @llvm.vector.partial.reduce.add.nxv4i64.nxv8i64(<vscale x 4 x i64> %acc, <vscale x 8 x i64> %input.wide)220 ret <vscale x 4 x i64> %partial.reduce221}222