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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4; LEGAL ADDS5 6define <vscale x 16 x i1> @add_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {7; CHECK-LABEL: add_nxv16i1:8; CHECK: // %bb.0:9; CHECK-NEXT: ptrue p2.b10; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b11; CHECK-NEXT: ret12 %res = add <vscale x 16 x i1> %a, %b13 ret <vscale x 16 x i1> %res;14}15 16define <vscale x 8 x i1> @add_nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {17; CHECK-LABEL: add_nxv8i1:18; CHECK: // %bb.0:19; CHECK-NEXT: ptrue p2.h20; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b21; CHECK-NEXT: ret22 %res = add <vscale x 8 x i1> %a, %b23 ret <vscale x 8 x i1> %res;24}25 26define <vscale x 4 x i1> @add_nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {27; CHECK-LABEL: add_nxv4i1:28; CHECK: // %bb.0:29; CHECK-NEXT: ptrue p2.s30; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b31; CHECK-NEXT: ret32 %res = add <vscale x 4 x i1> %a, %b33 ret <vscale x 4 x i1> %res;34}35 36define <vscale x 2 x i1> @add_nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {37; CHECK-LABEL: add_nxv2i1:38; CHECK: // %bb.0:39; CHECK-NEXT: ptrue p2.d40; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b41; CHECK-NEXT: ret42 %res = add <vscale x 2 x i1> %a, %b43 ret <vscale x 2 x i1> %res;44}45 46 47; ILLEGAL ADDS48 49define aarch64_sve_vector_pcs <vscale x 64 x i1> @add_nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b) uwtable {50; CHECK-LABEL: add_nxv64i1:51; CHECK: // %bb.0:52; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill53; CHECK-NEXT: .cfi_def_cfa_offset 1654; CHECK-NEXT: .cfi_offset w29, -1655; CHECK-NEXT: addvl sp, sp, #-156; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG57; CHECK-NEXT: str p8, [sp, #3, mul vl] // 2-byte Spill58; CHECK-NEXT: str p7, [sp, #4, mul vl] // 2-byte Spill59; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill60; CHECK-NEXT: ptrue p6.b61; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill62; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill63; CHECK-NEXT: ldr p4, [x0]64; CHECK-NEXT: ldr p5, [x1]65; CHECK-NEXT: ldr p7, [x2]66; CHECK-NEXT: ldr p8, [x3]67; CHECK-NEXT: eor p0.b, p6/z, p0.b, p4.b68; CHECK-NEXT: eor p1.b, p6/z, p1.b, p5.b69; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload70; CHECK-NEXT: eor p2.b, p6/z, p2.b, p7.b71; CHECK-NEXT: ldr p7, [sp, #4, mul vl] // 2-byte Reload72; CHECK-NEXT: eor p3.b, p6/z, p3.b, p8.b73; CHECK-NEXT: ldr p8, [sp, #3, mul vl] // 2-byte Reload74; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload75; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload76; CHECK-NEXT: addvl sp, sp, #177; CHECK-NEXT: .cfi_def_cfa wsp, 1678; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload79; CHECK-NEXT: .cfi_def_cfa_offset 080; CHECK-NEXT: .cfi_restore w2981; CHECK-NEXT: ret82 %res = add <vscale x 64 x i1> %a, %b83 ret <vscale x 64 x i1> %res;84}85 86 87; LEGAL SUBS88 89define <vscale x 16 x i1> @sub_xv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {90; CHECK-LABEL: sub_xv16i1:91; CHECK: // %bb.0:92; CHECK-NEXT: ptrue p2.b93; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b94; CHECK-NEXT: ret95 %res = sub <vscale x 16 x i1> %a, %b96 ret <vscale x 16 x i1> %res;97}98 99define <vscale x 8 x i1> @sub_xv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {100; CHECK-LABEL: sub_xv8i1:101; CHECK: // %bb.0:102; CHECK-NEXT: ptrue p2.h103; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b104; CHECK-NEXT: ret105 %res = sub <vscale x 8 x i1> %a, %b106 ret <vscale x 8 x i1> %res;107}108 109define <vscale x 4 x i1> @sub_xv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {110; CHECK-LABEL: sub_xv4i1:111; CHECK: // %bb.0:112; CHECK-NEXT: ptrue p2.s113; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b114; CHECK-NEXT: ret115 %res = sub <vscale x 4 x i1> %a, %b116 ret <vscale x 4 x i1> %res;117}118 119define <vscale x 2 x i1> @sub_xv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {120; CHECK-LABEL: sub_xv2i1:121; CHECK: // %bb.0:122; CHECK-NEXT: ptrue p2.d123; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b124; CHECK-NEXT: ret125 %res = sub <vscale x 2 x i1> %a, %b126 ret <vscale x 2 x i1> %res;127}128 129 130; ILLEGAL SUBGS131 132 133define aarch64_sve_vector_pcs <vscale x 64 x i1> @sub_nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b) uwtable {134; CHECK-LABEL: sub_nxv64i1:135; CHECK: // %bb.0:136; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill137; CHECK-NEXT: .cfi_def_cfa_offset 16138; CHECK-NEXT: .cfi_offset w29, -16139; CHECK-NEXT: addvl sp, sp, #-1140; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG141; CHECK-NEXT: str p8, [sp, #3, mul vl] // 2-byte Spill142; CHECK-NEXT: str p7, [sp, #4, mul vl] // 2-byte Spill143; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill144; CHECK-NEXT: ptrue p6.b145; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill146; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill147; CHECK-NEXT: ldr p4, [x0]148; CHECK-NEXT: ldr p5, [x1]149; CHECK-NEXT: ldr p7, [x2]150; CHECK-NEXT: ldr p8, [x3]151; CHECK-NEXT: eor p0.b, p6/z, p0.b, p4.b152; CHECK-NEXT: eor p1.b, p6/z, p1.b, p5.b153; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload154; CHECK-NEXT: eor p2.b, p6/z, p2.b, p7.b155; CHECK-NEXT: ldr p7, [sp, #4, mul vl] // 2-byte Reload156; CHECK-NEXT: eor p3.b, p6/z, p3.b, p8.b157; CHECK-NEXT: ldr p8, [sp, #3, mul vl] // 2-byte Reload158; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload159; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload160; CHECK-NEXT: addvl sp, sp, #1161; CHECK-NEXT: .cfi_def_cfa wsp, 16162; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload163; CHECK-NEXT: .cfi_def_cfa_offset 0164; CHECK-NEXT: .cfi_restore w29165; CHECK-NEXT: ret166 %res = sub <vscale x 64 x i1> %a, %b167 ret <vscale x 64 x i1> %res;168}169